SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[sram_ctrl_prim_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[sram_ctrl_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[0]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[1] | 178773179 | 0 | T1 | 8410 | T2 | 106745 | T3 | 6920 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 178772992 | 1 | T1 | 8410 | T2 | 106745 | T3 | 6920 | ||||
values[1] | 22 | 1 | T63 | 1 | T64 | 2 | T122 | 1 | ||||
values[2] | 3 | 1 | T63 | 1 | T123 | 1 | T124 | 1 | ||||
values[3] | 85 | 1 | T62 | 2 | T63 | 2 | T64 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 178772998 | 1 | T1 | 8410 | T2 | 106745 | T3 | 6920 | ||||
values[1] | 12 | 1 | T62 | 1 | T63 | 2 | T64 | 1 | ||||
values[2] | 6 | 1 | T125 | 1 | T123 | 1 | T126 | 1 | ||||
values[3] | 92 | 1 | T62 | 4 | T63 | 2 | T64 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 178772899 | 1 | T1 | 8410 | T2 | 106745 | T3 | 6920 | ||||
auto[TlIntgErrCmd] | 99 | 1 | T62 | 4 | T63 | 5 | T64 | 7 | ||||
auto[TlIntgErrData] | 93 | 1 | T62 | 2 | T63 | 4 | T64 | 7 | ||||
auto[TlIntgErrBoth] | 88 | 1 | T62 | 4 | T63 | 1 | T64 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | ||||
auto[0] | 513685 | 0 | T1 | 1 | T2 | 24 | T3 | 4863 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 513498 | 1 | T1 | 1 | T2 | 24 | T3 | 4863 | ||||
values[1] | 23 | 1 | T63 | 3 | T64 | 1 | T122 | 1 | ||||
values[2] | 7 | 1 | T62 | 1 | T64 | 1 | T122 | 1 | ||||
values[3] | 83 | 1 | T62 | 6 | T63 | 2 | T64 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 513500 | 1 | T1 | 1 | T2 | 24 | T3 | 4863 | ||||
values[1] | 24 | 1 | T63 | 1 | T122 | 1 | T125 | 3 | ||||
values[2] | 5 | 1 | T63 | 1 | T64 | 1 | T125 | 1 | ||||
values[3] | 85 | 1 | T62 | 3 | T63 | 1 | T64 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 513405 | 1 | T1 | 1 | T2 | 24 | T3 | 4863 | ||||
auto[TlIntgErrCmd] | 95 | 1 | T62 | 7 | T63 | 6 | T64 | 4 | ||||
auto[TlIntgErrData] | 93 | 1 | T62 | 1 | T63 | 2 | T64 | 9 | ||||
auto[TlIntgErrBoth] | 92 | 1 | T62 | 2 | T63 | 2 | T64 | 7 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |