Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16570039	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

165199930

1

T1

1578

T2

109334

T3

2813

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89504033	1			T1	4181		T2	60081		T3	688
values[0x0]	44493152	1			T1	1410		T2	28996		T3	1058
values[0x1]	47772784	1			T1	2819		T2	31021		T3	1067

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8429115	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

173340854

1

T1

5027

T2

114781

T3

2813

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	553824	1			T1	34		T3	4		T10	725
valid_sources[0x01]	543309	1			T1	22		T2	3449		T3	13
valid_sources[0x02]	539538	1			T1	43		T3	10		T9	11
valid_sources[0x03]	567432	1			T1	29		T3	6		T9	14
valid_sources[0x04]	562084	1			T1	54		T3	7		T9	44
valid_sources[0x05]	554083	1			T1	19		T3	10		T9	29
valid_sources[0x06]	566380	1			T1	25		T3	13		T9	45
valid_sources[0x07]	550323	1			T1	30		T2	2102		T3	7
valid_sources[0x08]	582666	1			T1	33		T3	9		T9	18
valid_sources[0x09]	593200	1			T1	35		T3	9		T9	6
valid_sources[0x0a]	733992	1			T1	25		T3	8		T9	11
valid_sources[0x0b]	601888	1			T1	33		T3	10		T9	3
valid_sources[0x0c]	1268069	1			T1	23		T3	6		T9	25
valid_sources[0x0d]	550451	1			T1	45		T3	9		T9	6
valid_sources[0x0e]	537509	1			T1	33		T3	11		T9	15
valid_sources[0x0f]	555384	1			T1	41		T3	15		T9	4
valid_sources[0x10]	638269	1			T1	39		T3	7		T9	25
valid_sources[0x11]	614456	1			T1	27		T3	8		T9	29
valid_sources[0x12]	2979293	1			T1	43		T3	17		T9	16
valid_sources[0x13]	570083	1			T1	25		T3	8		T9	24
valid_sources[0x14]	550106	1			T1	24		T3	4		T9	12
valid_sources[0x15]	584384	1			T1	17		T3	13		T9	62
valid_sources[0x16]	549113	1			T1	45		T3	12		T9	61
valid_sources[0x17]	1048750	1			T1	21		T3	8		T9	26
valid_sources[0x18]	571936	1			T1	29		T3	19		T9	4
valid_sources[0x19]	550167	1			T1	43		T3	6		T9	39
valid_sources[0x1a]	581966	1			T1	36		T3	6		T9	1
valid_sources[0x1b]	626377	1			T1	28		T3	7		T9	52
valid_sources[0x1c]	558208	1			T1	14		T3	5		T9	54
valid_sources[0x1d]	2118368	1			T1	24		T3	6		T10	794
valid_sources[0x1e]	563631	1			T1	45		T3	7		T9	24
valid_sources[0x1f]	648267	1			T1	35		T3	11		T9	34
valid_sources[0x20]	597827	1			T1	51		T3	10		T9	20
valid_sources[0x21]	602477	1			T1	24		T3	16		T9	37
valid_sources[0x22]	645739	1			T1	20		T3	13		T9	61
valid_sources[0x23]	566349	1			T1	27		T3	14		T10	772
valid_sources[0x24]	538556	1			T1	32		T3	10		T9	44
valid_sources[0x25]	578909	1			T1	38		T3	15		T9	53
valid_sources[0x26]	544160	1			T1	39		T3	16		T9	19
valid_sources[0x27]	533019	1			T1	18		T3	11		T9	24
valid_sources[0x28]	581667	1			T1	45		T3	10		T9	57
valid_sources[0x29]	589050	1			T1	39		T3	12		T9	39
valid_sources[0x2a]	570869	1			T1	27		T3	9		T9	35
valid_sources[0x2b]	560543	1			T1	29		T3	16		T9	14
valid_sources[0x2c]	544564	1			T1	39		T3	8		T9	20
valid_sources[0x2d]	620539	1			T1	21		T3	14		T9	1
valid_sources[0x2e]	570572	1			T1	31		T3	4		T9	24
valid_sources[0x2f]	540976	1			T1	47		T3	13		T9	28
valid_sources[0x30]	546104	1			T1	33		T3	11		T9	15
valid_sources[0x31]	585316	1			T1	26		T3	4		T9	11
valid_sources[0x32]	565106	1			T1	25		T3	4		T9	5
valid_sources[0x33]	1401224	1			T1	15		T3	7		T9	29
valid_sources[0x34]	533426	1			T1	23		T3	9		T9	20
valid_sources[0x35]	601365	1			T1	28		T3	12		T9	16
valid_sources[0x36]	573421	1			T1	27		T3	17		T10	736
valid_sources[0x37]	1910276	1			T1	47		T3	4		T9	18
valid_sources[0x38]	561505	1			T1	32		T3	9		T9	8
valid_sources[0x39]	639344	1			T1	24		T3	10		T9	49
valid_sources[0x3a]	569548	1			T1	46		T3	12		T9	37
valid_sources[0x3b]	1663501	1			T1	29		T3	8		T9	31
valid_sources[0x3c]	564794	1			T1	34		T2	2605		T3	12
valid_sources[0x3d]	598666	1			T1	38		T3	12		T9	24
valid_sources[0x3e]	652429	1			T1	15		T3	9		T9	19
valid_sources[0x3f]	555356	1			T1	18		T3	8		T9	92
valid_sources[0x40]	573749	1			T1	33		T3	4		T9	29
valid_sources[0x41]	546449	1			T1	39		T3	15		T9	39
valid_sources[0x42]	740498	1			T1	67		T3	6		T9	25
valid_sources[0x43]	549763	1			T1	36		T3	22		T10	795
valid_sources[0x44]	612166	1			T1	36		T3	18		T9	40
valid_sources[0x45]	536377	1			T1	18		T3	5		T9	6
valid_sources[0x46]	585853	1			T1	51		T3	22		T9	11
valid_sources[0x47]	548810	1			T1	38		T3	7		T9	31
valid_sources[0x48]	540330	1			T1	39		T3	8		T9	17
valid_sources[0x49]	665662	1			T1	55		T3	8		T4	5000
valid_sources[0x4a]	570073	1			T1	45		T3	7		T9	6
valid_sources[0x4b]	548891	1			T1	28		T3	13		T9	19
valid_sources[0x4c]	2147270	1			T1	41		T3	10		T10	745
valid_sources[0x4d]	598821	1			T1	37		T3	10		T9	16
valid_sources[0x4e]	569919	1			T1	28		T2	22384		T3	16
valid_sources[0x4f]	605142	1			T1	24		T3	10		T9	46
valid_sources[0x50]	661981	1			T1	18		T3	4		T9	22
valid_sources[0x51]	548449	1			T1	20		T3	10		T9	41
valid_sources[0x52]	600321	1			T1	25		T3	11		T9	16
valid_sources[0x53]	562034	1			T1	30		T3	9		T9	26
valid_sources[0x54]	557576	1			T1	32		T3	18		T9	34
valid_sources[0x55]	553970	1			T1	31		T9	31		T10	751
valid_sources[0x56]	597191	1			T1	37		T3	13		T9	4
valid_sources[0x57]	805669	1			T1	37		T3	9		T9	14
valid_sources[0x58]	584293	1			T1	26		T3	13		T9	46
valid_sources[0x59]	561815	1			T1	42		T3	15		T9	19
valid_sources[0x5a]	552596	1			T1	21		T3	8		T9	49
valid_sources[0x5b]	571517	1			T1	25		T3	6		T9	86
valid_sources[0x5c]	536059	1			T1	43		T3	9		T9	26
valid_sources[0x5d]	574262	1			T1	32		T3	9		T9	21
valid_sources[0x5e]	619864	1			T1	35		T3	19		T9	7
valid_sources[0x5f]	696752	1			T1	41		T3	6		T9	35
valid_sources[0x60]	621906	1			T1	46		T3	6		T9	78
valid_sources[0x61]	593888	1			T1	36		T3	8		T9	39
valid_sources[0x62]	582037	1			T1	25		T3	11		T9	40
valid_sources[0x63]	535656	1			T1	49		T3	9		T9	17
valid_sources[0x64]	597707	1			T1	43		T2	9351		T3	7
valid_sources[0x65]	542770	1			T1	34		T3	17		T9	81
valid_sources[0x66]	554656	1			T1	26		T3	11		T9	42
valid_sources[0x67]	548099	1			T1	32		T3	17		T9	32
valid_sources[0x68]	631746	1			T1	36		T3	28		T9	37
valid_sources[0x69]	805648	1			T1	12		T3	18		T9	59
valid_sources[0x6a]	548498	1			T1	40		T2	428		T3	7
valid_sources[0x6b]	564523	1			T1	27		T3	10		T9	10
valid_sources[0x6c]	563141	1			T1	31		T3	7		T9	1
valid_sources[0x6d]	610520	1			T1	41		T2	47404		T3	12
valid_sources[0x6e]	617479	1			T1	43		T3	9		T9	68
valid_sources[0x6f]	577362	1			T1	19		T3	4		T9	2
valid_sources[0x70]	557134	1			T1	34		T3	13		T9	11
valid_sources[0x71]	559396	1			T1	31		T3	6		T9	47
valid_sources[0x72]	552344	1			T1	55		T3	7		T9	8
valid_sources[0x73]	571622	1			T1	32		T3	20		T9	25
valid_sources[0x74]	574552	1			T1	16		T3	20		T9	22
valid_sources[0x75]	1568988	1			T1	35		T3	11		T9	31
valid_sources[0x76]	555152	1			T1	28		T3	3		T9	35
valid_sources[0x77]	589445	1			T1	28		T3	8		T9	9
valid_sources[0x78]	577818	1			T1	24		T3	8		T9	18
valid_sources[0x79]	586872	1			T1	34		T3	18		T9	109
valid_sources[0x7a]	541268	1			T1	30		T3	2		T9	45
valid_sources[0x7b]	549349	1			T1	34		T3	2		T9	26
valid_sources[0x7c]	598281	1			T1	27		T3	20		T9	12
valid_sources[0x7d]	563397	1			T1	29		T2	5764		T3	15
valid_sources[0x7e]	544785	1			T1	41		T3	12		T9	31
valid_sources[0x7f]	587280	1			T1	31		T2	445		T3	16
valid_sources[0x80]	585988	1			T1	42		T3	15		T9	37

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

81175265

1

T1

818

T2

54634

T3

688

values[0x0]

all_enables

biggest_size

42022659

1

T1

363

T2

27425

T3

1058

values[0x1]

all_enables

biggest_size

42002006

1

T1

397

T2

27275

T3

1067

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44952	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

178968

1

T2

7

T3

2309

T8

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	60259	1			T3	621		T5	15		T6	96
values[0x0]	78921	1			T2	12		T3	913		T8	2
values[0x1]	84740	1			T1	1		T2	12		T3	898

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34243	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

189677

1

T2

12

T3

2366

T8

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	731	1			T11	1		T42	2		T26	9
valid_sources[0x01]	929	1			T10	3		T42	5		T26	20
valid_sources[0x02]	902	1			T10	2		T12	1		T5	2
valid_sources[0x03]	720	1			T42	3		T26	9		T27	6
valid_sources[0x04]	639	1			T12	2		T6	14		T42	2
valid_sources[0x05]	815	1			T3	49		T5	1		T42	1
valid_sources[0x06]	764	1			T6	3		T42	2		T26	14
valid_sources[0x07]	845	1			T3	1		T10	2		T42	1
valid_sources[0x08]	943	1			T12	2		T42	2		T26	17
valid_sources[0x09]	778	1			T3	1		T42	2		T26	13
valid_sources[0x0a]	1112	1			T3	17		T12	1		T42	1
valid_sources[0x0b]	852	1			T3	1		T42	2		T26	19
valid_sources[0x0c]	939	1			T5	2		T42	3		T26	17
valid_sources[0x0d]	727	1			T42	1		T26	10		T48	1
valid_sources[0x0e]	756	1			T3	8		T5	1		T42	1
valid_sources[0x0f]	886	1			T42	1		T26	12		T27	9
valid_sources[0x10]	992	1			T42	4		T26	16		T54	1
valid_sources[0x11]	754	1			T5	1		T42	1		T26	12
valid_sources[0x12]	726	1			T3	1		T42	2		T26	14
valid_sources[0x13]	862	1			T3	36		T42	1		T26	10
valid_sources[0x14]	741	1			T42	1		T26	14		T27	12
valid_sources[0x15]	771	1			T3	19		T10	1		T42	2
valid_sources[0x16]	961	1			T6	27		T42	3		T26	17
valid_sources[0x17]	723	1			T42	3		T26	8		T43	1
valid_sources[0x18]	843	1			T10	1		T12	1		T5	2
valid_sources[0x19]	973	1			T3	1		T6	3		T42	3
valid_sources[0x1a]	774	1			T5	1		T42	4		T26	21
valid_sources[0x1b]	853	1			T42	1		T26	10		T7	1
valid_sources[0x1c]	778	1			T3	47		T25	1		T26	10
valid_sources[0x1d]	754	1			T42	2		T26	9		T54	1
valid_sources[0x1e]	694	1			T42	4		T26	16		T27	10
valid_sources[0x1f]	728	1			T3	7		T12	2		T26	13
valid_sources[0x20]	1169	1			T42	2		T26	6		T54	3
valid_sources[0x21]	1018	1			T42	1		T26	11		T54	4
valid_sources[0x22]	935	1			T3	11		T42	2		T26	10
valid_sources[0x23]	675	1			T3	4		T26	12		T43	3
valid_sources[0x24]	745	1			T42	5		T26	14		T43	2
valid_sources[0x25]	982	1			T5	1		T6	16		T42	1
valid_sources[0x26]	885	1			T26	16		T54	2		T24	3
valid_sources[0x27]	686	1			T3	21		T42	1		T26	13
valid_sources[0x28]	828	1			T42	3		T26	18		T27	2
valid_sources[0x29]	951	1			T10	1		T42	1		T26	16
valid_sources[0x2a]	793	1			T8	12		T12	1		T5	1
valid_sources[0x2b]	799	1			T26	17		T54	2		T24	3
valid_sources[0x2c]	773	1			T3	38		T42	2		T26	11
valid_sources[0x2d]	745	1			T42	1		T26	18		T48	1
valid_sources[0x2e]	1702	1			T12	1		T26	10		T27	14
valid_sources[0x2f]	878	1			T42	1		T26	18		T54	3
valid_sources[0x30]	704	1			T3	1		T42	1		T26	8
valid_sources[0x31]	811	1			T10	4		T42	2		T26	14
valid_sources[0x32]	751	1			T3	7		T42	3		T26	9
valid_sources[0x33]	825	1			T42	3		T26	12		T54	2
valid_sources[0x34]	906	1			T3	6		T26	14		T43	2
valid_sources[0x35]	855	1			T42	1		T26	19		T27	10
valid_sources[0x36]	961	1			T6	27		T42	5		T26	19
valid_sources[0x37]	944	1			T26	10		T54	6		T27	8
valid_sources[0x38]	836	1			T42	2		T26	12		T140	2
valid_sources[0x39]	701	1			T5	2		T6	2		T42	7
valid_sources[0x3a]	838	1			T10	1		T42	3		T26	12
valid_sources[0x3b]	1310	1			T3	1		T10	2		T42	2
valid_sources[0x3c]	717	1			T26	12		T43	1		T24	2
valid_sources[0x3d]	1163	1			T42	3		T26	12		T27	4
valid_sources[0x3e]	726	1			T6	24		T26	15		T27	8
valid_sources[0x3f]	823	1			T12	1		T42	1		T26	16
valid_sources[0x40]	1376	1			T12	1		T42	1		T26	16
valid_sources[0x41]	815	1			T3	6		T12	2		T42	3
valid_sources[0x42]	1106	1			T12	1		T42	1		T26	14
valid_sources[0x43]	873	1			T9	2		T12	1		T5	1
valid_sources[0x44]	792	1			T3	1		T42	4		T26	8
valid_sources[0x45]	770	1			T12	1		T5	1		T42	1
valid_sources[0x46]	661	1			T3	3		T12	1		T42	1
valid_sources[0x47]	726	1			T3	1		T10	1		T42	2
valid_sources[0x48]	747	1			T3	4		T12	1		T42	4
valid_sources[0x49]	859	1			T3	14		T42	3		T26	16
valid_sources[0x4a]	975	1			T3	82		T42	3		T26	17
valid_sources[0x4b]	789	1			T26	13		T44	1		T43	2
valid_sources[0x4c]	1095	1			T12	1		T26	11		T44	1
valid_sources[0x4d]	792	1			T3	26		T42	1		T26	9
valid_sources[0x4e]	966	1			T12	2		T42	3		T26	16
valid_sources[0x4f]	778	1			T26	16		T14	2		T27	5
valid_sources[0x50]	988	1			T12	1		T42	4		T26	7
valid_sources[0x51]	752	1			T10	3		T26	14		T44	1
valid_sources[0x52]	748	1			T3	2		T42	2		T26	11
valid_sources[0x53]	788	1			T3	28		T10	1		T57	2
valid_sources[0x54]	1059	1			T12	2		T42	3		T26	19
valid_sources[0x55]	1261	1			T3	204		T42	1		T26	11
valid_sources[0x56]	790	1			T5	1		T42	1		T26	17
valid_sources[0x57]	681	1			T42	2		T26	18		T54	2
valid_sources[0x58]	959	1			T10	2		T25	2		T6	3
valid_sources[0x59]	1038	1			T26	8		T27	10		T46	1
valid_sources[0x5a]	608	1			T42	1		T26	9		T24	6
valid_sources[0x5b]	1294	1			T3	63		T12	1		T42	1
valid_sources[0x5c]	842	1			T3	3		T10	2		T42	4
valid_sources[0x5d]	693	1			T12	1		T42	2		T26	8
valid_sources[0x5e]	1199	1			T3	134		T10	1		T57	2
valid_sources[0x5f]	751	1			T42	3		T26	14		T54	9
valid_sources[0x60]	737	1			T3	7		T10	4		T42	2
valid_sources[0x61]	860	1			T3	2		T42	1		T26	19
valid_sources[0x62]	975	1			T42	1		T26	16		T27	10
valid_sources[0x63]	802	1			T3	1		T10	1		T12	3
valid_sources[0x64]	913	1			T3	21		T10	2		T26	12
valid_sources[0x65]	726	1			T12	1		T42	3		T26	17
valid_sources[0x66]	1131	1			T12	1		T42	4		T26	6
valid_sources[0x67]	679	1			T3	2		T42	2		T26	17
valid_sources[0x68]	925	1			T3	1		T12	1		T42	3
valid_sources[0x69]	680	1			T10	3		T26	13		T24	1
valid_sources[0x6a]	840	1			T26	18		T54	2		T24	1
valid_sources[0x6b]	697	1			T26	13		T27	15		T15	2
valid_sources[0x6c]	932	1			T3	6		T12	1		T26	13
valid_sources[0x6d]	1535	1			T3	43		T42	5		T26	18
valid_sources[0x6e]	901	1			T3	2		T42	1		T26	16
valid_sources[0x6f]	687	1			T3	73		T10	1		T26	7
valid_sources[0x70]	853	1			T11	1		T42	2		T26	20
valid_sources[0x71]	719	1			T5	1		T42	2		T26	9
valid_sources[0x72]	1110	1			T3	3		T10	2		T26	20
valid_sources[0x73]	799	1			T3	3		T26	11		T27	6
valid_sources[0x74]	1009	1			T3	113		T42	1		T26	18
valid_sources[0x75]	677	1			T10	2		T42	2		T26	15
valid_sources[0x76]	796	1			T12	1		T42	3		T26	13
valid_sources[0x77]	644	1			T42	1		T26	15		T23	5
valid_sources[0x78]	692	1			T12	1		T42	6		T26	14
valid_sources[0x79]	874	1			T3	54		T10	3		T42	2
valid_sources[0x7a]	844	1			T3	94		T42	1		T26	13
valid_sources[0x7b]	863	1			T42	1		T26	22		T54	2
valid_sources[0x7c]	859	1			T42	3		T26	21		T19	9
valid_sources[0x7d]	846	1			T3	2		T10	4		T6	18
valid_sources[0x7e]	799	1			T5	1		T42	5		T26	10
valid_sources[0x7f]	894	1			T10	1		T26	15		T54	1
valid_sources[0x80]	848	1			T25	1		T42	1		T26	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47483

1

T3

573

T5

9

T6

54

values[0x0]

all_enables

biggest_size

67197

1

T2

2

T3

905

T10

19

values[0x1]

all_enables

biggest_size

64288

1

T2

5

T3

831

T8

3