Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16527988

1

T1

6832

T2

9578

T3

3702

full_word

162245191

1

T1

1578

T2

97167

T3

3218

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	178772899	1			T1	8410		T2	106745		T3	6920
auto[TlIntgErrCmd]	99	1			T62	4		T63	5		T64	7
auto[TlIntgErrData]	93	1			T62	2		T63	4		T64	7
auto[TlIntgErrBoth]	88	1			T62	4		T63	1		T64	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86387724

1

T1

4181

T2

46728

T3

1546

auto[1]

92385455

1

T1

4229

T2

60017

T3

5374

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8092169	1			T1	3363		T2	4261		T3	765
auto[TlIntgErrNone]	partial	auto[1]	8435560	1			T1	3469		T2	5317		T3	2937
auto[TlIntgErrNone]	full_word	auto[0]	78295420	1			T1	818		T2	42467		T3	781
auto[TlIntgErrNone]	full_word	auto[1]	83949750	1			T1	760		T2	54700		T3	2437
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T62	1		T63	2		T64	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T62	3		T63	3		T64	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T123	1		T127	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T64	2		T128	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T62	1		T63	1		T64	3
auto[TlIntgErrData]	partial	auto[1]	43	1			T62	1		T63	3		T64	3
auto[TlIntgErrData]	full_word	auto[0]	2	1			T122	1		T127	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T64	1		T130	1		T124	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T63	1		T64	5		T122	3
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T62	3		T64	1		T128	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T62	1		T131	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T122	1		T132	1		-	-