Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	642101	1			T9	163		T5	1		T43	5940
auto[1]	11222646	1			T2	4287		T4	4966		T9	487
auto[2]	472404	1			T9	96		T5	2		T7	1
auto[3]	10960673	1			T2	3272		T4	5032		T9	413

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14360490	1			T2	6326		T4	8303		T9	13
auto[1]	2209167	1			T2	581		T4	798		T9	118
auto[2]	2255807	1			T2	607		T4	825		T9	144
auto[3]	4472360	1			T2	45		T4	72		T9	884

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9849064

1

T2

7559

T4

9998

T9

1159

auto[1]

13448760

1

T12

3

T25

168649

T6

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	245398	1			T9	4		T5	1		T43	4922
auto[0]	auto[0]	auto[1]	26121	1			T9	19		T43	488		T23	3
auto[0]	auto[0]	auto[2]	25760	1			T9	15		T43	482		T47	217
auto[0]	auto[0]	auto[3]	57755	1			T9	125		T43	48		T23	2
auto[0]	auto[1]	auto[0]	3634589	1			T2	3584		T4	4124		T9	6
auto[0]	auto[1]	auto[1]	373184	1			T2	313		T4	388		T9	81
auto[0]	auto[1]	auto[2]	391694	1			T2	367		T4	415		T9	42
auto[0]	auto[1]	auto[3]	328883	1			T2	23		T4	39		T9	358
auto[0]	auto[2]	auto[0]	158763	1			T7	1		T43	3231		T23	23
auto[0]	auto[2]	auto[1]	19831	1			T43	312		T23	5		T47	102
auto[0]	auto[2]	auto[2]	21195	1			T9	18		T5	2		T43	284
auto[0]	auto[2]	auto[3]	41410	1			T9	78		T43	42		T47	9
auto[0]	auto[3]	auto[0]	3473558	1			T2	2742		T4	4179		T9	3
auto[0]	auto[3]	auto[1]	372249	1			T2	268		T4	410		T9	18
auto[0]	auto[3]	auto[2]	380344	1			T2	240		T4	410		T9	69
auto[0]	auto[3]	auto[3]	298330	1			T2	22		T4	33		T9	323
auto[1]	auto[0]	auto[0]	9390	1			T49	76		T21	1		T136	1
auto[1]	auto[0]	auto[1]	42465	1			T49	353		T136	1		T134	3854
auto[1]	auto[0]	auto[2]	42657	1			T49	364		T134	3970		T137	777
auto[1]	auto[0]	auto[3]	192555	1			T49	1611		T134	17547		T135	1
auto[1]	auto[1]	auto[0]	3419779	1			T12	1		T25	70167		T57	6
auto[1]	auto[1]	auto[1]	686466	1			T12	1		T25	6211		T81	6269
auto[1]	auto[1]	auto[2]	678532	1			T25	7070		T81	7026		T107	14933
auto[1]	auto[1]	auto[3]	1709519	1			T25	626		T81	664		T107	67712
auto[1]	auto[2]	auto[0]	5747	1			T134	784		T121	2		T138	1162
auto[1]	auto[2]	auto[1]	26071	1			T134	3511		T138	5277		T139	3527
auto[1]	auto[2]	auto[2]	36444	1			T49	329		T134	2724		T137	723
auto[1]	auto[2]	auto[3]	162943	1			T49	1467		T134	11833		T137	3217
auto[1]	auto[3]	auto[0]	3413266	1			T12	1		T25	70312		T6	1
auto[1]	auto[3]	auto[1]	662780	1			T25	7164		T81	7020		T107	15138
auto[1]	auto[3]	auto[2]	679181	1			T25	6484		T71	1		T81	6328
auto[1]	auto[3]	auto[3]	1680965	1			T25	615		T71	1		T81	596