SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.00 | 100.00 | 100.00 | 100.00 | 95.00 | 50.00 | u_tlul_lc_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 2703 | 2703 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 5406 |
gen_no_flops.OutputDelay_A | 1149421057 | 1149302193 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2703 | 2703 | 0 | 0 |
T1 | 3 | 3 | 0 | 0 |
T2 | 3 | 3 | 0 | 0 |
T3 | 3 | 3 | 0 | 0 |
T4 | 3 | 3 | 0 | 0 |
T8 | 3 | 3 | 0 | 0 |
T9 | 3 | 3 | 0 | 0 |
T10 | 3 | 3 | 0 | 0 |
T11 | 3 | 3 | 0 | 0 |
T12 | 3 | 3 | 0 | 0 |
T13 | 3 | 3 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 347106 | 346884 | 0 | 0 |
T2 | 1732152 | 1731951 | 0 | 0 |
T3 | 159576 | 159192 | 0 | 0 |
T4 | 133272 | 133047 | 0 | 0 |
T8 | 5499 | 5325 | 0 | 0 |
T9 | 325671 | 325482 | 0 | 0 |
T10 | 1574934 | 1574748 | 0 | 0 |
T11 | 1468044 | 1467891 | 0 | 0 |
T12 | 726795 | 726699 | 0 | 0 |
T13 | 1507950 | 1507776 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 5406 |
T1 | 231404 | 231250 | 0 | 6 |
T2 | 1154768 | 1154628 | 0 | 6 |
T3 | 106384 | 106062 | 0 | 6 |
T4 | 88848 | 88692 | 0 | 6 |
T8 | 3666 | 3544 | 0 | 6 |
T9 | 217114 | 216982 | 0 | 6 |
T10 | 1049956 | 1049826 | 0 | 6 |
T11 | 978696 | 978588 | 0 | 6 |
T12 | 484530 | 484462 | 0 | 6 |
T13 | 1005300 | 1005178 | 0 | 6 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1149421057 | 1149302193 | 0 | 0 |
T1 | 115702 | 115628 | 0 | 0 |
T2 | 577384 | 577317 | 0 | 0 |
T3 | 53192 | 53064 | 0 | 0 |
T4 | 44424 | 44349 | 0 | 0 |
T8 | 1833 | 1775 | 0 | 0 |
T9 | 108557 | 108494 | 0 | 0 |
T10 | 524978 | 524916 | 0 | 0 |
T11 | 489348 | 489297 | 0 | 0 |
T12 | 242265 | 242233 | 0 | 0 |
T13 | 502650 | 502592 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 901 | 901 | 0 | 0 |
OutputsKnown_A | 1149421057 | 1149302193 | 0 | 0 |
gen_flops.OutputDelay_A | 1149421057 | 1149288892 | 0 | 2703 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 901 | 901 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1149421057 | 1149302193 | 0 | 0 |
T1 | 115702 | 115628 | 0 | 0 |
T2 | 577384 | 577317 | 0 | 0 |
T3 | 53192 | 53064 | 0 | 0 |
T4 | 44424 | 44349 | 0 | 0 |
T8 | 1833 | 1775 | 0 | 0 |
T9 | 108557 | 108494 | 0 | 0 |
T10 | 524978 | 524916 | 0 | 0 |
T11 | 489348 | 489297 | 0 | 0 |
T12 | 242265 | 242233 | 0 | 0 |
T13 | 502650 | 502592 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1149421057 | 1149288892 | 0 | 2703 |
T1 | 115702 | 115625 | 0 | 3 |
T2 | 577384 | 577314 | 0 | 3 |
T3 | 53192 | 53031 | 0 | 3 |
T4 | 44424 | 44346 | 0 | 3 |
T8 | 1833 | 1772 | 0 | 3 |
T9 | 108557 | 108491 | 0 | 3 |
T10 | 524978 | 524913 | 0 | 3 |
T11 | 489348 | 489294 | 0 | 3 |
T12 | 242265 | 242231 | 0 | 3 |
T13 | 502650 | 502589 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 901 | 901 | 0 | 0 |
OutputsKnown_A | 1149421057 | 1149302193 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1149421057 | 1149302193 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 901 | 901 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1149421057 | 1149302193 | 0 | 0 |
T1 | 115702 | 115628 | 0 | 0 |
T2 | 577384 | 577317 | 0 | 0 |
T3 | 53192 | 53064 | 0 | 0 |
T4 | 44424 | 44349 | 0 | 0 |
T8 | 1833 | 1775 | 0 | 0 |
T9 | 108557 | 108494 | 0 | 0 |
T10 | 524978 | 524916 | 0 | 0 |
T11 | 489348 | 489297 | 0 | 0 |
T12 | 242265 | 242233 | 0 | 0 |
T13 | 502650 | 502592 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1149421057 | 1149302193 | 0 | 0 |
T1 | 115702 | 115628 | 0 | 0 |
T2 | 577384 | 577317 | 0 | 0 |
T3 | 53192 | 53064 | 0 | 0 |
T4 | 44424 | 44349 | 0 | 0 |
T8 | 1833 | 1775 | 0 | 0 |
T9 | 108557 | 108494 | 0 | 0 |
T10 | 524978 | 524916 | 0 | 0 |
T11 | 489348 | 489297 | 0 | 0 |
T12 | 242265 | 242233 | 0 | 0 |
T13 | 502650 | 502592 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 901 | 901 | 0 | 0 |
OutputsKnown_A | 1149421057 | 1149302193 | 0 | 0 |
gen_flops.OutputDelay_A | 1149421057 | 1149288892 | 0 | 2703 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 901 | 901 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1149421057 | 1149302193 | 0 | 0 |
T1 | 115702 | 115628 | 0 | 0 |
T2 | 577384 | 577317 | 0 | 0 |
T3 | 53192 | 53064 | 0 | 0 |
T4 | 44424 | 44349 | 0 | 0 |
T8 | 1833 | 1775 | 0 | 0 |
T9 | 108557 | 108494 | 0 | 0 |
T10 | 524978 | 524916 | 0 | 0 |
T11 | 489348 | 489297 | 0 | 0 |
T12 | 242265 | 242233 | 0 | 0 |
T13 | 502650 | 502592 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1149421057 | 1149288892 | 0 | 2703 |
T1 | 115702 | 115625 | 0 | 3 |
T2 | 577384 | 577314 | 0 | 3 |
T3 | 53192 | 53031 | 0 | 3 |
T4 | 44424 | 44346 | 0 | 3 |
T8 | 1833 | 1772 | 0 | 3 |
T9 | 108557 | 108491 | 0 | 3 |
T10 | 524978 | 524913 | 0 | 3 |
T11 | 489348 | 489294 | 0 | 3 |
T12 | 242265 | 242231 | 0 | 3 |
T13 | 502650 | 502589 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |