Line Coverage for Module :
prim_subreg
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Module :
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL=0,Mubi=0 + DW=1,SwAccess=5,RESVAL=1,Mubi=0 + DW=1,SwAccess=2,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T5,T6 |
Cond Coverage for Module :
prim_subreg ( parameter DW=4,SwAccess=0,RESVAL=9,Mubi=1 + DW=4,SwAccess=3,RESVAL=9,Mubi=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_subreg
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T5,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T5,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_status_readback_error
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 6 | 85.71 |
ALWAYS | 56 | 4 | 3 | 75.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
0 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_status_readback_error
| Total | Covered | Percent |
Conditions | 2 | 1 | 50.00 |
Logical | 2 | 1 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_status_readback_error
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
3 |
60.00 |
TERNARY |
64 |
2 |
1 |
50.00 |
IF |
56 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_status_sram_alert
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 6 | 85.71 |
ALWAYS | 56 | 4 | 3 | 75.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
0 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_status_sram_alert
| Total | Covered | Percent |
Conditions | 2 | 1 | 50.00 |
Logical | 2 | 1 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_status_sram_alert
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
3 |
60.00 |
TERNARY |
64 |
2 |
1 |
50.00 |
IF |
56 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_readback_regwen
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 6 | 85.71 |
ALWAYS | 56 | 4 | 3 | 75.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
0 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_readback_regwen
| Total | Covered | Percent |
Conditions | 2 | 1 | 50.00 |
Logical | 2 | 1 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_readback_regwen
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
3 |
60.00 |
TERNARY |
64 |
2 |
1 |
50.00 |
IF |
56 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_status_bus_integ_error
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_status_bus_integ_error
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T16,T17,T18 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_status_bus_integ_error
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T16,T17,T18 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_status_init_error
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_status_init_error
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T16,T17,T18 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_status_init_error
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T16,T17,T18 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_status_escalated
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_status_escalated
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T6,T7 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_status_escalated
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T6,T7 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_status_scr_key_valid
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_status_scr_key_valid
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_status_scr_key_valid
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_status_scr_key_seed_valid
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_status_scr_key_seed_valid
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_status_scr_key_seed_valid
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_status_init_done
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_status_init_done
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_status_init_done
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_exec_regwen
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_exec_regwen
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T43,T20 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_exec_regwen
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T43,T20 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T6,T43,T20 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_exec
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_exec
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T2,T12,T6 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_exec
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T2,T12,T6 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T2,T12,T6 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_ctrl_regwen
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_ctrl_regwen
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T6,T43,T20 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_ctrl_regwen
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T43,T20 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T6,T43,T20 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_ctrl_renew_scr_key
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_ctrl_renew_scr_key
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_ctrl_renew_scr_key
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_ctrl_init
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_ctrl_init
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_ctrl_init
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_scr_key_rotated
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_scr_key_rotated
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_scr_key_rotated
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg_regs.u_readback
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg_regs.u_readback
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T8,T10 |
Branch Coverage for Instance : tb.dut.u_reg_regs.u_readback
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T8,T10 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T8,T10 |
0 |
0 |
Covered |
T1,T2,T3 |