Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1160033784	266557	0	0
ctrl_regwen_rd_A	1160033784	4125	0	0
exec_rd_A	1160033784	4116	0	0
exec_regwen_rd_A	1160033784	4160	0	0
readback_rd_A	1160033784	2670	0	0
readback_regwen_rd_A	1160033784	2417	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160033784	266557	0	0
T3	53192	2675	0	0
T4	44424	0	0	0
T5	666311	0	0	0
T8	1833	0	0	0
T9	108557	0	0	0
T10	524978	0	0	0
T11	489348	0	0	0
T12	242265	0	0	0
T13	502650	0	0	0
T25	501172	0	0	0
T26	0	5488	0	0
T27	0	3725	0	0
T50	0	9548	0	0
T51	0	6953	0	0
T55	0	7238	0	0
T61	0	8284	0	0
T66	0	4720	0	0
T67	0	1168	0	0
T68	0	2053	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160033784	4125	0	0
T3	53192	268	0	0
T4	44424	0	0	0
T5	666311	0	0	0
T8	1833	0	0	0
T9	108557	0	0	0
T10	524978	0	0	0
T11	489348	0	0	0
T12	242265	0	0	0
T13	502650	0	0	0
T25	501172	0	0	0
T27	0	173	0	0
T51	0	195	0	0
T55	0	432	0	0
T114	0	179	0	0
T115	0	311	0	0
T116	0	271	0	0
T117	0	74	0	0
T118	0	235	0	0
T119	0	72	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160033784	4116	0	0
T3	53192	237	0	0
T4	44424	0	0	0
T5	666311	0	0	0
T8	1833	0	0	0
T9	108557	0	0	0
T10	524978	0	0	0
T11	489348	0	0	0
T12	242265	0	0	0
T13	502650	0	0	0
T25	501172	0	0	0
T27	0	119	0	0
T51	0	185	0	0
T55	0	372	0	0
T114	0	163	0	0
T115	0	318	0	0
T116	0	288	0	0
T117	0	107	0	0
T118	0	228	0	0
T119	0	88	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160033784	4160	0	0
T3	53192	261	0	0
T4	44424	0	0	0
T5	666311	0	0	0
T8	1833	0	0	0
T9	108557	0	0	0
T10	524978	0	0	0
T11	489348	0	0	0
T12	242265	0	0	0
T13	502650	0	0	0
T25	501172	0	0	0
T27	0	111	0	0
T51	0	254	0	0
T55	0	478	0	0
T114	0	165	0	0
T115	0	354	0	0
T116	0	154	0	0
T117	0	88	0	0
T118	0	309	0	0
T119	0	112	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160033784	2670	0	0
T3	53192	207	0	0
T4	44424	0	0	0
T5	666311	0	0	0
T8	1833	0	0	0
T9	108557	0	0	0
T10	524978	0	0	0
T11	489348	0	0	0
T12	242265	0	0	0
T13	502650	0	0	0
T25	501172	0	0	0
T27	0	158	0	0
T51	0	227	0	0
T55	0	356	0	0
T114	0	113	0	0
T115	0	243	0	0
T116	0	227	0	0
T117	0	70	0	0
T118	0	202	0	0
T119	0	97	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1160033784	2417	0	0
T3	53192	208	0	0
T4	44424	0	0	0
T5	666311	0	0	0
T8	1833	0	0	0
T9	108557	0	0	0
T10	524978	0	0	0
T11	489348	0	0	0
T12	242265	0	0	0
T13	502650	0	0	0
T25	501172	0	0	0
T27	0	116	0	0
T51	0	170	0	0
T55	0	413	0	0
T114	0	112	0	0
T115	0	195	0	0
T116	0	167	0	0
T117	0	60	0	0
T118	0	169	0	0
T119	0	67	0	0