Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16464131

1

T1

15870

T3

176935

T4

62050

full_word

164388552

1

T1

157199

T3

39332

T4

3252

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	180852373	1			T1	173069		T3	216267		T4	65302
auto[TlIntgErrCmd]	105	1			T65	8		T66	4		T67	6
auto[TlIntgErrData]	98	1			T65	5		T66	4		T67	8
auto[TlIntgErrBoth]	107	1			T65	7		T66	2		T67	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87638033

1

T1

86478

T3

107802

T4

32619

auto[1]

93214650

1

T1

86591

T3

108465

T4

32683

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8086503	1			T1	7892		T3	88171		T4	32370
auto[TlIntgErrNone]	partial	auto[1]	8377347	1			T1	7978		T3	88764		T4	29680
auto[TlIntgErrNone]	full_word	auto[0]	79551398	1			T1	78586		T3	19631		T4	249
auto[TlIntgErrNone]	full_word	auto[1]	84837125	1			T1	78613		T3	19701		T4	3003
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T65	2		T66	1		T67	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T65	6		T66	3		T67	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T118	1		T122	1		T124	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T121	1		T120	1		-	-
auto[TlIntgErrData]	partial	auto[0]	45	1			T65	3		T66	3		T67	5
auto[TlIntgErrData]	partial	auto[1]	43	1			T65	2		T67	3		T118	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T66	1		T121	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T126	1		T127	1		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T65	2		T67	2		T121	3
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T65	4		T66	2		T67	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T65	1		T127	1		T122	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T67	1		T118	1		T121	1