Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	867721	1			T3	4546		T4	1789		T5	4723
auto[1]	11559152	1			T1	72724		T3	12708		T4	5106
auto[2]	658152	1			T3	3362		T4	1200		T5	3522
auto[3]	11284440	1			T1	72863		T3	11671		T4	4547

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14654194	1			T1	120037		T3	535		T4	13
auto[1]	2340295	1			T1	12196		T3	3205		T4	139
auto[2]	2385523	1			T1	12112		T3	4470		T4	680
auto[3]	4989453	1			T1	1242		T3	24077		T4	11810

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9749844

1

T1

23

T3

4

T4

12641

auto[1]

14619621

1

T1

145564

T3

32283

T4

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	349765	1			T10	3297		T6	9674		T37	235
auto[0]	auto[0]	auto[1]	36500	1			T4	9		T10	336		T6	949
auto[0]	auto[0]	auto[2]	36617	1			T4	19		T5	1		T10	335
auto[0]	auto[0]	auto[3]	29642	1			T4	1760		T5	1		T10	28
auto[0]	auto[1]	auto[0]	3370187	1			T1	10		T4	1		T10	1372
auto[0]	auto[1]	auto[1]	357198	1			T4	39		T5	2		T10	250
auto[0]	auto[1]	auto[2]	382150	1			T1	2		T4	271		T5	1
auto[0]	auto[1]	auto[3]	468253	1			T3	3		T4	4795		T5	3
auto[0]	auto[2]	auto[0]	252029	1			T10	1338		T6	5373		T38	11
auto[0]	auto[2]	auto[1]	27038	1			T10	151		T6	554		T38	36
auto[0]	auto[2]	auto[2]	29922	1			T4	3		T10	212		T6	838
auto[0]	auto[2]	auto[3]	22351	1			T4	1197		T10	17		T6	84
auto[0]	auto[3]	auto[0]	3215725	1			T1	11		T4	12		T10	418
auto[0]	auto[3]	auto[1]	361389	1			T4	91		T10	52		T6	204
auto[0]	auto[3]	auto[2]	378756	1			T3	1		T4	387		T10	229
auto[0]	auto[3]	auto[3]	432322	1			T4	4057		T5	1		T10	27
auto[1]	auto[0]	auto[0]	13774	1			T3	130		T5	149		T6	1
auto[1]	auto[0]	auto[1]	61682	1			T3	674		T5	727		T109	1621
auto[1]	auto[0]	auto[2]	61668	1			T3	679		T5	687		T109	1672
auto[1]	auto[0]	auto[3]	278073	1			T3	3063		T4	1		T5	3158
auto[1]	auto[1]	auto[0]	3722620	1			T1	60003		T3	259		T5	278
auto[1]	auto[1]	auto[1]	742263	1			T1	6085		T3	1986		T5	2058
auto[1]	auto[1]	auto[2]	717388	1			T1	6011		T3	1134		T5	1250
auto[1]	auto[1]	auto[3]	1799093	1			T1	613		T3	9326		T5	9209
auto[1]	auto[2]	auto[0]	11023	1			T109	208		T132	702		T133	1
auto[1]	auto[2]	auto[1]	49569	1			T109	958		T132	3375		T134	2371
auto[1]	auto[2]	auto[2]	48639	1			T3	593		T5	615		T109	1860
auto[1]	auto[2]	auto[3]	217581	1			T3	2769		T5	2907		T109	7945
auto[1]	auto[3]	auto[0]	3719071	1			T1	60013		T3	146		T5	117
auto[1]	auto[3]	auto[1]	704656	1			T1	6111		T3	545		T5	537
auto[1]	auto[3]	auto[2]	730383	1			T1	6099		T3	2063		T5	1997
auto[1]	auto[3]	auto[3]	1742138	1			T1	629		T3	8916		T5	8929