Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1233513482	229430	0	0
ctrl_regwen_rd_A	1233513482	5731	0	0
exec_rd_A	1233513482	4999	0	0
exec_regwen_rd_A	1233513482	5666	0	0
readback_rd_A	1233513482	4589	0	0
readback_regwen_rd_A	1233513482	3809	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233513482	229430	0	0
T8	909226	0	0	0
T20	379741	10706	0	0
T21	560423	0	0	0
T22	24927	1159	0	0
T23	0	6509	0	0
T38	49377	0	0	0
T39	405591	0	0	0
T44	524960	0	0	0
T45	138343	0	0	0
T49	0	7111	0	0
T57	143536	0	0	0
T58	287715	0	0	0
T59	0	2948	0	0
T72	0	1855	0	0
T73	0	1870	0	0
T74	0	2005	0	0
T75	0	1583	0	0
T76	0	1864	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233513482	5731	0	0
T8	909226	0	0	0
T20	379741	448	0	0
T21	560423	0	0	0
T22	24927	97	0	0
T38	49377	0	0	0
T39	405591	0	0	0
T44	524960	0	0	0
T45	138343	0	0	0
T46	0	378	0	0
T57	143536	0	0	0
T58	287715	0	0	0
T72	0	153	0	0
T73	0	175	0	0
T111	0	275	0	0
T112	0	156	0	0
T113	0	222	0	0
T114	0	261	0	0
T115	0	65	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233513482	4999	0	0
T8	909226	0	0	0
T20	379741	385	0	0
T21	560423	0	0	0
T22	24927	96	0	0
T38	49377	0	0	0
T39	405591	0	0	0
T44	524960	0	0	0
T45	138343	0	0	0
T46	0	268	0	0
T57	143536	0	0	0
T58	287715	0	0	0
T72	0	126	0	0
T73	0	151	0	0
T111	0	225	0	0
T112	0	122	0	0
T113	0	232	0	0
T114	0	178	0	0
T115	0	97	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233513482	5666	0	0
T8	909226	0	0	0
T20	379741	401	0	0
T21	560423	0	0	0
T22	24927	108	0	0
T38	49377	0	0	0
T39	405591	0	0	0
T44	524960	0	0	0
T45	138343	0	0	0
T46	0	412	0	0
T57	143536	0	0	0
T58	287715	0	0	0
T72	0	173	0	0
T73	0	209	0	0
T111	0	231	0	0
T112	0	152	0	0
T113	0	222	0	0
T114	0	216	0	0
T115	0	110	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233513482	4589	0	0
T8	909226	0	0	0
T20	379741	316	0	0
T21	560423	0	0	0
T22	24927	143	0	0
T38	49377	0	0	0
T39	405591	0	0	0
T44	524960	0	0	0
T45	138343	0	0	0
T46	0	265	0	0
T57	143536	0	0	0
T58	287715	0	0	0
T72	0	99	0	0
T73	0	194	0	0
T111	0	234	0	0
T112	0	161	0	0
T113	0	242	0	0
T114	0	229	0	0
T115	0	57	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233513482	3809	0	0
T8	909226	0	0	0
T20	379741	278	0	0
T21	560423	0	0	0
T22	24927	97	0	0
T38	49377	0	0	0
T39	405591	0	0	0
T44	524960	0	0	0
T45	138343	0	0	0
T46	0	291	0	0
T57	143536	0	0	0
T58	287715	0	0	0
T72	0	141	0	0
T73	0	140	0	0
T111	0	282	0	0
T112	0	118	0	0
T113	0	161	0	0
T114	0	116	0	0
T115	0	68	0	0