Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	362614086	1			T1	45802		T2	328758		T3	389438
instr_valid_dis	318592739	1			T1	45802		T3	389438		T8	3110
instr_en	30333270	1			T2	328758		T10	307666		T19	507266

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	18374904	1			T10	177024		T19	17526		T20	167770
sram_ifetch_valid_disable	319225384	1			T1	45802		T2	141456		T3	389438
sram_ifetch_enable	25013798	1			T2	187302		T10	215134		T19	261566

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	362614086	1			T1	45802		T2	328758		T3	389438
hw_debug_en_valid_off	322694830	1			T1	45802		T2	118694		T3	389438
hw_debug_en_on	27169508	1			T2	171300		T10	200940		T19	159808

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	319225384	1			T1	45802		T2	141456		T3	389438
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	300739663	1			T1	45802		T3	389438		T8	3110
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	12467410	1			T2	141456		T10	165646		T19	228174
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	8174814	1			T10	85400		T20	98488		T6	20544
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	3671730	1			T10	45890		T6	20544		T63	11982
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	3655614	1			T10	39510		T20	98488		T73	100
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	7608166	1			T19	17526		T20	40512		T6	45214
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2268570	1			T63	4388		T145	76244		T140	24408
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	4350788	1			T19	17526		T20	40512		T140	35248
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	11797148	1			T2	122442		T10	103840		T19	25508
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3261144	1			T10	37784		T20	100		T6	58630
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4365560	1			T2	122442		T10	66056		T19	25508

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8913748	1			T2	187302		T10	77874		T19	261566
lc_exec_en	7764194	1			T2	48858		T10	97100		T19	116774
valid_exec_dis	311713490	1			T1	45802		T2	19014		T3	389438
invalid_exec_dis	43388702	1			T2	187302		T10	392158		T19	279092