Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	151472544	1			T1	9562		T2	88263		T3	176914
triple_byte_access	2904819	1			T1	200		T2	1640		T3	3585
halfword_access	4451239	1			T1	288		T2	2667		T3	5265
byte_access	6216291	1			T1	392		T2	3495		T3	7169
zero_access	1866900	1			T1	75		T2	842		T3	1786

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83319251

1

T1

5165

T2

63816

T3

97279

auto[1]

83592542

1

T1

5352

T2

33091

T3

97440

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	75454513	1			T1	4675		T2	58231		T3	88289
auto[0]	triple_byte_access	1390559	1			T1	96		T2	1049		T3	1838
auto[0]	halfword_access	2179762	1			T1	160		T2	1738		T3	2681
auto[0]	byte_access	3184652	1			T1	196		T2	2253		T3	3614
auto[0]	zero_access	1109765	1			T1	38		T2	545		T3	857
auto[1]	word_access	76018031	1			T1	4887		T2	30032		T3	88625
auto[1]	triple_byte_access	1514260	1			T1	104		T2	591		T3	1747
auto[1]	halfword_access	2271477	1			T1	128		T2	929		T3	2584
auto[1]	byte_access	3031639	1			T1	196		T2	1242		T3	3555
auto[1]	zero_access	757135	1			T1	37		T2	297		T3	929