Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16062199	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

161117797

1

T1

149595

T2

199147

T3

3202

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	87155417	1			T1	82034		T2	109844		T3	31770
values[0x0]	43407876	1			T1	40049		T2	52227		T3	10031
values[0x1]	46616703	1			T1	42385		T2	56909		T3	21552

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8165153	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

169014843

1

T1

157041

T2

209152

T3

28690

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	540576	1			T1	536		T3	556		T5	10
valid_sources[0x01]	760133	1			T1	688		T2	6425		T3	373
valid_sources[0x02]	763049	1			T1	713		T3	153		T5	3
valid_sources[0x03]	586300	1			T1	641		T3	59		T5	9
valid_sources[0x04]	547291	1			T1	676		T3	324		T5	10
valid_sources[0x05]	573518	1			T1	614		T3	206		T5	9
valid_sources[0x06]	571867	1			T1	722		T3	73		T5	10
valid_sources[0x07]	568476	1			T1	710		T3	137		T5	14
valid_sources[0x08]	563123	1			T1	652		T3	167		T5	17
valid_sources[0x09]	552400	1			T1	582		T3	206		T5	18
valid_sources[0x0a]	547531	1			T1	606		T3	316		T5	7
valid_sources[0x0b]	558357	1			T1	645		T3	284		T5	10
valid_sources[0x0c]	608066	1			T1	633		T3	105		T5	10
valid_sources[0x0d]	525615	1			T1	582		T3	141		T5	5
valid_sources[0x0e]	558862	1			T1	570		T3	197		T5	8
valid_sources[0x0f]	551830	1			T1	664		T3	287		T5	17
valid_sources[0x10]	565320	1			T1	597		T3	219		T5	10
valid_sources[0x11]	599535	1			T1	664		T3	506		T5	13
valid_sources[0x12]	1438789	1			T1	585		T3	145		T5	21
valid_sources[0x13]	577315	1			T1	665		T3	551		T5	8
valid_sources[0x14]	542044	1			T1	639		T3	273		T5	11
valid_sources[0x15]	545962	1			T1	635		T3	395		T5	14
valid_sources[0x16]	1498488	1			T1	619		T3	307		T5	8
valid_sources[0x17]	577434	1			T1	599		T3	237		T5	16
valid_sources[0x18]	555706	1			T1	563		T3	403		T5	6
valid_sources[0x19]	576459	1			T1	718		T3	168		T5	17
valid_sources[0x1a]	597071	1			T1	647		T3	184		T5	11
valid_sources[0x1b]	573053	1			T1	690		T3	148		T5	8
valid_sources[0x1c]	529175	1			T1	605		T3	328		T5	14
valid_sources[0x1d]	561310	1			T1	551		T3	142		T5	14
valid_sources[0x1e]	4874737	1			T1	642		T3	261		T5	12
valid_sources[0x1f]	538267	1			T1	688		T3	401		T5	9
valid_sources[0x20]	543120	1			T1	609		T3	170		T5	14
valid_sources[0x21]	581575	1			T1	681		T3	189		T5	16
valid_sources[0x22]	557331	1			T1	626		T3	146		T5	6
valid_sources[0x23]	611955	1			T1	660		T3	72		T5	12
valid_sources[0x24]	552465	1			T1	606		T2	12640		T3	82
valid_sources[0x25]	548426	1			T1	641		T2	13985		T3	290
valid_sources[0x26]	946829	1			T1	608		T3	274		T5	6
valid_sources[0x27]	544317	1			T1	699		T3	214		T5	26
valid_sources[0x28]	555162	1			T1	649		T3	263		T5	6
valid_sources[0x29]	553071	1			T1	623		T3	409		T5	6
valid_sources[0x2a]	600557	1			T1	661		T2	8858		T3	52
valid_sources[0x2b]	760731	1			T1	675		T3	226		T5	16
valid_sources[0x2c]	589320	1			T1	632		T3	218		T5	3
valid_sources[0x2d]	567350	1			T1	668		T3	145		T5	4
valid_sources[0x2e]	616228	1			T1	670		T2	44159		T3	410
valid_sources[0x2f]	1694259	1			T1	682		T3	231		T5	17
valid_sources[0x30]	609648	1			T1	690		T3	188		T5	7
valid_sources[0x31]	1974759	1			T1	704		T3	204		T5	10
valid_sources[0x32]	537629	1			T1	622		T3	145		T5	14
valid_sources[0x33]	540130	1			T1	624		T3	227		T5	11
valid_sources[0x34]	538420	1			T1	572		T3	440		T5	22
valid_sources[0x35]	3539497	1			T1	565		T3	251		T5	12
valid_sources[0x36]	573897	1			T1	610		T3	339		T5	15
valid_sources[0x37]	550347	1			T1	602		T3	327		T5	12
valid_sources[0x38]	563259	1			T1	639		T3	150		T5	4
valid_sources[0x39]	652660	1			T1	610		T3	234		T5	22
valid_sources[0x3a]	609570	1			T1	684		T3	216		T5	16
valid_sources[0x3b]	542678	1			T1	630		T3	135		T5	7
valid_sources[0x3c]	1862503	1			T1	700		T3	192		T5	19
valid_sources[0x3d]	574298	1			T1	654		T3	407		T5	8
valid_sources[0x3e]	525351	1			T1	715		T3	200		T5	8
valid_sources[0x3f]	621589	1			T1	634		T3	279		T5	8
valid_sources[0x40]	567786	1			T1	612		T3	100		T5	6
valid_sources[0x41]	583396	1			T1	590		T3	432		T5	4
valid_sources[0x42]	538976	1			T1	703		T3	268		T5	13
valid_sources[0x43]	536696	1			T1	633		T3	276		T5	11
valid_sources[0x44]	542345	1			T1	667		T3	135		T5	30
valid_sources[0x45]	553435	1			T1	646		T3	167		T5	13
valid_sources[0x46]	542779	1			T1	638		T3	166		T5	12
valid_sources[0x47]	558238	1			T1	616		T3	177		T5	15
valid_sources[0x48]	612852	1			T1	620		T3	370		T5	11
valid_sources[0x49]	543216	1			T1	691		T3	552		T5	5
valid_sources[0x4a]	550356	1			T1	671		T3	389		T5	18
valid_sources[0x4b]	547316	1			T1	698		T3	199		T5	19
valid_sources[0x4c]	532304	1			T1	628		T3	131		T5	9
valid_sources[0x4d]	528978	1			T1	606		T3	267		T5	19
valid_sources[0x4e]	1017419	1			T1	649		T3	261		T5	13
valid_sources[0x4f]	552684	1			T1	660		T3	133		T5	12
valid_sources[0x50]	1449184	1			T1	623		T3	217		T5	20
valid_sources[0x51]	570032	1			T1	667		T3	126		T5	11
valid_sources[0x52]	800592	1			T1	681		T3	112		T5	6
valid_sources[0x53]	567859	1			T1	643		T3	103		T5	6
valid_sources[0x54]	617299	1			T1	601		T3	231		T5	11
valid_sources[0x55]	567836	1			T1	561		T3	201		T5	20
valid_sources[0x56]	544741	1			T1	611		T3	154		T5	6
valid_sources[0x57]	554522	1			T1	618		T2	22490		T3	199
valid_sources[0x58]	576205	1			T1	688		T3	213		T5	16
valid_sources[0x59]	557926	1			T1	590		T3	191		T5	12
valid_sources[0x5a]	633936	1			T1	660		T2	30194		T3	441
valid_sources[0x5b]	581061	1			T1	622		T3	191		T5	18
valid_sources[0x5c]	2890733	1			T1	570		T3	243		T5	8
valid_sources[0x5d]	733354	1			T1	717		T3	294		T5	11
valid_sources[0x5e]	755955	1			T1	682		T3	263		T5	15
valid_sources[0x5f]	540721	1			T1	666		T3	241		T5	15
valid_sources[0x60]	549953	1			T1	621		T2	14345		T3	229
valid_sources[0x61]	563203	1			T1	696		T3	401		T5	11
valid_sources[0x62]	561151	1			T1	631		T3	247		T5	10
valid_sources[0x63]	573716	1			T1	716		T3	297		T5	7
valid_sources[0x64]	581592	1			T1	710		T3	277		T5	18
valid_sources[0x65]	562073	1			T1	647		T3	251		T5	10
valid_sources[0x66]	583249	1			T1	658		T3	266		T5	16
valid_sources[0x67]	553559	1			T1	574		T3	194		T5	17
valid_sources[0x68]	570401	1			T1	639		T3	174		T5	7
valid_sources[0x69]	562003	1			T1	650		T3	244		T5	4
valid_sources[0x6a]	784110	1			T1	691		T3	179		T5	23
valid_sources[0x6b]	540395	1			T1	603		T3	199		T5	18
valid_sources[0x6c]	547094	1			T1	656		T3	241		T5	4
valid_sources[0x6d]	565097	1			T1	687		T3	187		T5	13
valid_sources[0x6e]	621452	1			T1	611		T3	319		T5	14
valid_sources[0x6f]	569201	1			T1	620		T3	155		T5	13
valid_sources[0x70]	539796	1			T1	580		T3	674		T5	24
valid_sources[0x71]	560155	1			T1	651		T3	299		T5	15
valid_sources[0x72]	767397	1			T1	604		T3	291		T5	19
valid_sources[0x73]	531558	1			T1	649		T3	114		T5	14
valid_sources[0x74]	583969	1			T1	606		T3	888		T5	17
valid_sources[0x75]	558315	1			T1	627		T3	384		T5	13
valid_sources[0x76]	544276	1			T1	599		T3	206		T5	8
valid_sources[0x77]	546745	1			T1	624		T3	255		T5	7
valid_sources[0x78]	565791	1			T1	677		T3	161		T5	17
valid_sources[0x79]	588576	1			T1	644		T3	371		T5	22
valid_sources[0x7a]	572983	1			T1	645		T3	156		T5	8
valid_sources[0x7b]	552551	1			T1	600		T3	449		T5	13
valid_sources[0x7c]	536321	1			T1	638		T3	201		T5	9
valid_sources[0x7d]	565494	1			T1	622		T3	356		T5	24
valid_sources[0x7e]	554055	1			T1	642		T3	296		T5	5
valid_sources[0x7f]	604802	1			T1	677		T3	199		T5	11
valid_sources[0x80]	577514	1			T1	613		T2	22		T3	253

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

79082866

1

T1

74624

T2

99942

T3

283

values[0x0]

all_enables

biggest_size

41010886

1

T1

37775

T2

49282

T3

1408

values[0x1]

all_enables

biggest_size

41024045

1

T1

37196

T2

49923

T3

1511

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45756	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

164638

1

T1

4

T2

8

T5

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	57415	1			T5	27		T24	19		T23	2349
values[0x0]	73790	1			T1	17		T2	16		T3	2
values[0x1]	79189	1			T1	9		T2	22		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35086	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

175308

1

T1

5

T2

11

T5

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	911	1			T2	3		T23	53		T6	2
valid_sources[0x01]	776	1			T23	27		T22	1		T25	9
valid_sources[0x02]	771	1			T2	1		T23	38		T6	3
valid_sources[0x03]	942	1			T1	1		T23	44		T6	1
valid_sources[0x04]	984	1			T38	2		T23	27		T6	1
valid_sources[0x05]	986	1			T23	40		T6	2		T25	11
valid_sources[0x06]	663	1			T23	20		T6	2		T25	12
valid_sources[0x07]	899	1			T23	34		T25	2		T26	2
valid_sources[0x08]	672	1			T2	1		T38	1		T23	10
valid_sources[0x09]	1177	1			T23	23		T6	1		T22	1
valid_sources[0x0a]	710	1			T23	30		T6	3		T7	1
valid_sources[0x0b]	628	1			T1	1		T23	29		T6	1
valid_sources[0x0c]	676	1			T24	4		T23	28		T6	3
valid_sources[0x0d]	697	1			T12	1		T23	37		T22	1
valid_sources[0x0e]	1213	1			T23	30		T6	1		T7	2
valid_sources[0x0f]	877	1			T23	50		T6	1		T22	3
valid_sources[0x10]	992	1			T23	30		T6	1		T7	1
valid_sources[0x11]	784	1			T23	39		T6	2		T22	1
valid_sources[0x12]	630	1			T23	17		T6	1		T25	14
valid_sources[0x13]	840	1			T1	1		T23	37		T6	2
valid_sources[0x14]	671	1			T5	4		T23	51		T25	7
valid_sources[0x15]	601	1			T23	37		T7	1		T25	12
valid_sources[0x16]	709	1			T23	41		T6	1		T7	1
valid_sources[0x17]	772	1			T23	36		T25	11		T26	7
valid_sources[0x18]	889	1			T23	24		T6	1		T25	6
valid_sources[0x19]	866	1			T1	1		T38	4		T23	32
valid_sources[0x1a]	899	1			T24	2		T23	13		T25	7
valid_sources[0x1b]	613	1			T23	31		T22	2		T25	13
valid_sources[0x1c]	784	1			T23	36		T6	1		T7	1
valid_sources[0x1d]	1002	1			T23	31		T6	3		T13	1
valid_sources[0x1e]	871	1			T23	28		T6	1		T25	8
valid_sources[0x1f]	902	1			T4	2		T23	23		T6	1
valid_sources[0x20]	789	1			T24	1		T23	39		T25	6
valid_sources[0x21]	788	1			T2	8		T38	5		T24	1
valid_sources[0x22]	762	1			T23	38		T6	2		T25	8
valid_sources[0x23]	1082	1			T23	34		T6	1		T22	2
valid_sources[0x24]	649	1			T23	29		T6	2		T25	8
valid_sources[0x25]	890	1			T2	2		T11	1		T23	29
valid_sources[0x26]	706	1			T24	3		T23	30		T6	1
valid_sources[0x27]	838	1			T23	33		T6	1		T7	1
valid_sources[0x28]	769	1			T23	44		T6	1		T7	2
valid_sources[0x29]	683	1			T38	4		T23	42		T25	10
valid_sources[0x2a]	767	1			T23	28		T6	1		T7	1
valid_sources[0x2b]	730	1			T23	35		T6	1		T25	9
valid_sources[0x2c]	855	1			T9	2		T23	44		T6	1
valid_sources[0x2d]	1021	1			T5	4		T23	51		T25	12
valid_sources[0x2e]	836	1			T23	43		T6	4		T25	8
valid_sources[0x2f]	676	1			T23	32		T6	1		T25	16
valid_sources[0x30]	835	1			T23	55		T6	1		T25	10
valid_sources[0x31]	707	1			T23	26		T6	1		T25	15
valid_sources[0x32]	826	1			T38	2		T23	31		T6	1
valid_sources[0x33]	624	1			T1	1		T38	1		T24	2
valid_sources[0x34]	909	1			T23	24		T6	1		T25	13
valid_sources[0x35]	1008	1			T5	6		T23	40		T6	3
valid_sources[0x36]	832	1			T23	34		T6	1		T25	12
valid_sources[0x37]	904	1			T23	24		T22	1		T25	7
valid_sources[0x38]	923	1			T23	34		T6	1		T7	1
valid_sources[0x39]	734	1			T23	28		T6	1		T7	1
valid_sources[0x3a]	1362	1			T23	40		T6	3		T25	7
valid_sources[0x3b]	859	1			T23	18		T25	12		T26	15
valid_sources[0x3c]	1051	1			T23	25		T6	1		T25	9
valid_sources[0x3d]	782	1			T24	1		T23	53		T6	1
valid_sources[0x3e]	1001	1			T5	1		T23	25		T22	2
valid_sources[0x3f]	793	1			T24	3		T23	33		T7	1
valid_sources[0x40]	898	1			T23	31		T22	1		T25	2
valid_sources[0x41]	942	1			T23	30		T6	1		T25	7
valid_sources[0x42]	898	1			T23	35		T7	2		T25	7
valid_sources[0x43]	807	1			T23	39		T6	2		T22	1
valid_sources[0x44]	894	1			T4	1		T24	3		T23	44
valid_sources[0x45]	682	1			T23	46		T6	1		T22	2
valid_sources[0x46]	777	1			T5	3		T38	8		T23	42
valid_sources[0x47]	795	1			T2	1		T23	30		T6	2
valid_sources[0x48]	763	1			T2	1		T23	56		T25	13
valid_sources[0x49]	605	1			T23	29		T6	1		T7	2
valid_sources[0x4a]	795	1			T23	37		T6	1		T7	1
valid_sources[0x4b]	737	1			T38	3		T23	53		T6	1
valid_sources[0x4c]	646	1			T12	1		T24	5		T23	40
valid_sources[0x4d]	870	1			T23	36		T6	1		T25	12
valid_sources[0x4e]	705	1			T23	23		T6	1		T7	2
valid_sources[0x4f]	763	1			T23	68		T25	10		T26	14
valid_sources[0x50]	638	1			T23	21		T25	7		T32	1
valid_sources[0x51]	809	1			T5	2		T24	1		T23	44
valid_sources[0x52]	987	1			T23	25		T7	1		T25	5
valid_sources[0x53]	738	1			T1	1		T23	48		T6	3
valid_sources[0x54]	644	1			T23	48		T22	1		T25	7
valid_sources[0x55]	670	1			T23	35		T7	1		T25	10
valid_sources[0x56]	609	1			T1	1		T23	48		T6	1
valid_sources[0x57]	791	1			T38	6		T23	29		T25	9
valid_sources[0x58]	680	1			T23	25		T6	1		T25	10
valid_sources[0x59]	771	1			T5	2		T23	22		T6	1
valid_sources[0x5a]	646	1			T1	1		T23	26		T6	1
valid_sources[0x5b]	929	1			T2	2		T23	28		T6	1
valid_sources[0x5c]	994	1			T24	1		T23	45		T22	1
valid_sources[0x5d]	657	1			T23	49		T25	11		T26	8
valid_sources[0x5e]	911	1			T23	43		T6	1		T25	11
valid_sources[0x5f]	775	1			T2	3		T24	1		T23	40
valid_sources[0x60]	706	1			T24	4		T23	16		T6	2
valid_sources[0x61]	958	1			T24	2		T23	33		T13	1
valid_sources[0x62]	666	1			T1	1		T23	47		T6	2
valid_sources[0x63]	999	1			T23	39		T6	1		T22	1
valid_sources[0x64]	858	1			T23	20		T6	1		T22	1
valid_sources[0x65]	922	1			T1	1		T24	3		T23	59
valid_sources[0x66]	795	1			T23	36		T6	2		T7	1
valid_sources[0x67]	710	1			T23	31		T25	10		T26	8
valid_sources[0x68]	686	1			T24	2		T23	14		T6	1
valid_sources[0x69]	647	1			T23	32		T6	3		T25	7
valid_sources[0x6a]	996	1			T4	9		T38	5		T23	52
valid_sources[0x6b]	1325	1			T2	2		T23	26		T25	16
valid_sources[0x6c]	754	1			T23	31		T7	1		T25	6
valid_sources[0x6d]	655	1			T23	54		T25	8		T26	14
valid_sources[0x6e]	839	1			T23	33		T22	1		T25	8
valid_sources[0x6f]	944	1			T23	59		T6	1		T7	1
valid_sources[0x70]	690	1			T1	1		T23	36		T6	1
valid_sources[0x71]	640	1			T23	31		T7	1		T22	1
valid_sources[0x72]	606	1			T1	1		T24	7		T23	35
valid_sources[0x73]	681	1			T23	49		T6	1		T7	1
valid_sources[0x74]	684	1			T23	60		T25	11		T26	17
valid_sources[0x75]	857	1			T23	36		T6	1		T7	1
valid_sources[0x76]	900	1			T24	2		T23	32		T25	12
valid_sources[0x77]	759	1			T23	31		T25	13		T26	12
valid_sources[0x78]	847	1			T23	41		T25	12		T26	12
valid_sources[0x79]	768	1			T24	4		T23	20		T6	1
valid_sources[0x7a]	879	1			T23	18		T6	1		T7	2
valid_sources[0x7b]	859	1			T38	1		T23	15		T6	2
valid_sources[0x7c]	1106	1			T23	38		T7	1		T25	11
valid_sources[0x7d]	798	1			T24	1		T23	62		T6	1
valid_sources[0x7e]	689	1			T23	40		T25	9		T26	6
valid_sources[0x7f]	1166	1			T24	1		T23	42		T6	1
valid_sources[0x80]	597	1			T23	46		T25	10		T26	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44185

1

T5

11

T24

10

T23

2181

values[0x0]

all_enables

biggest_size

61770

1

T1

4

T2

3

T5

4

values[0x1]

all_enables

biggest_size

58683

1

T2

5

T5

6

T4

1