Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15989873

1

T1

14873

T2

19833

T3

60151

full_word

158062351

1

T1

149595

T2

199147

T3

3202

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	174051924	1			T1	164468		T2	218980		T3	63353
auto[TlIntgErrCmd]	95	1			T55	4		T56	3		T57	5
auto[TlIntgErrData]	108	1			T55	4		T56	3		T57	9
auto[TlIntgErrBoth]	97	1			T55	2		T56	4		T57	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83927940

1

T1

82034

T2

109844

T3

31770

auto[1]

90124284

1

T1

82434

T2

109136

T3

31583

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7821697	1			T1	7410		T2	9902		T3	31487
auto[TlIntgErrNone]	partial	auto[1]	8167899	1			T1	7463		T2	9931		T3	28664
auto[TlIntgErrNone]	full_word	auto[0]	76106117	1			T1	74624		T2	99942		T3	283
auto[TlIntgErrNone]	full_word	auto[1]	81956211	1			T1	74971		T2	99205		T3	2919
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T55	2		T56	1		T118	1
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T55	2		T56	2		T57	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T121	1		T124	1		T125	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T57	1		T119	1		T126	1
auto[TlIntgErrData]	partial	auto[0]	42	1			T55	2		T56	1		T57	2
auto[TlIntgErrData]	partial	auto[1]	54	1			T55	2		T56	1		T57	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T57	1		T121	1		T122	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T56	1		T57	1		T123	2
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T55	2		T57	2		T118	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1			T56	3		T57	4		T118	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T56	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T127	1		T128	1		-	-