Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	816172	1			T10	15716		T6	42		T40	286
auto[1]	11361539	1			T1	34137		T2	49475		T5	390
auto[2]	617789	1			T10	14120		T6	33		T40	147
auto[3]	11117271	1			T1	34523		T2	49445		T5	437

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14704359	1			T1	57312		T2	81760		T5	675
auto[1]	2304672	1			T1	5367		T2	8148		T5	73
auto[2]	2328548	1			T1	5497		T2	8172		T5	70
auto[3]	4575192	1			T1	484		T2	840		T5	9

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8758009

1

T1

68659

T2

98918

T5

827

auto[1]

15154762

1

T1

1

T2

2

T12

220053

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	375839	1			T10	12964		T6	30		T40	226
auto[0]	auto[0]	auto[1]	39534	1			T10	1280		T6	4		T40	23
auto[0]	auto[0]	auto[2]	39434	1			T10	1359		T6	7		T40	33
auto[0]	auto[0]	auto[3]	78142	1			T10	113		T6	1		T40	4
auto[0]	auto[1]	auto[0]	3067817	1			T1	28512		T2	40908		T5	325
auto[0]	auto[1]	auto[1]	327640	1			T1	2491		T2	4053		T5	24
auto[0]	auto[1]	auto[2]	327296	1			T1	2905		T2	4076		T5	35
auto[0]	auto[1]	auto[3]	281074	1			T1	229		T2	437		T5	6
auto[0]	auto[2]	auto[0]	278813	1			T10	12008		T7	1		T22	1257
auto[0]	auto[2]	auto[1]	33758	1			T10	1135		T22	116		T69	174
auto[0]	auto[2]	auto[2]	30615	1			T10	890		T6	30		T40	138
auto[0]	auto[2]	auto[3]	55011	1			T10	87		T6	3		T40	9
auto[0]	auto[3]	auto[0]	2932666	1			T1	28799		T2	40850		T5	350
auto[0]	auto[3]	auto[1]	310159	1			T1	2876		T2	4095		T5	49
auto[0]	auto[3]	auto[2]	331186	1			T1	2592		T2	4096		T5	35
auto[0]	auto[3]	auto[3]	249025	1			T1	255		T2	403		T5	3
auto[1]	auto[0]	auto[0]	9521	1			T39	627		T102	160		T103	121
auto[1]	auto[0]	auto[1]	41672	1			T39	3004		T102	644		T103	496
auto[1]	auto[0]	auto[2]	42166	1			T39	3057		T35	1		T102	661
auto[1]	auto[0]	auto[3]	189864	1			T39	13481		T35	1		T102	3023
auto[1]	auto[1]	auto[0]	4017765	1			T2	1		T12	91986		T39	100
auto[1]	auto[1]	auto[1]	766538	1			T12	8038		T39	3012		T98	6147
auto[1]	auto[1]	auto[2]	767031	1			T12	9204		T39	517		T98	6073
auto[1]	auto[1]	auto[3]	1806378	1			T12	838		T39	13736		T98	631
auto[1]	auto[2]	auto[0]	6918	1			T39	644		T133	357		T134	1
auto[1]	auto[2]	auto[1]	30623	1			T39	2715		T35	1		T133	1686
auto[1]	auto[2]	auto[2]	33116	1			T39	1949		T102	623		T103	431
auto[1]	auto[2]	auto[3]	148935	1			T39	9108		T35	1		T102	2719
auto[1]	auto[3]	auto[0]	4015020	1			T1	1		T2	1		T12	91622
auto[1]	auto[3]	auto[1]	754748	1			T12	9182		T39	295		T98	6045
auto[1]	auto[3]	auto[2]	757704	1			T12	8309		T39	2148		T98	6008
auto[1]	auto[3]	auto[3]	1766763	1			T12	874		T39	9365		T98	660