Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1233219357	247218	0	0
ctrl_regwen_rd_A	1233219357	3883	0	0
exec_rd_A	1233219357	3630	0	0
exec_regwen_rd_A	1233219357	3925	0	0
readback_rd_A	1233219357	2179	0	0
readback_regwen_rd_A	1233219357	1689	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233219357	247218	0	0
T6	329199	0	0	0
T7	100576	0	0	0
T13	1610	0	0	0
T22	310193	0	0	0
T23	308384	16417	0	0
T25	0	3822	0	0
T26	0	3548	0	0
T27	34163	0	0	0
T40	216219	0	0	0
T42	432077	0	0	0
T48	0	4189	0	0
T51	0	4475	0	0
T53	0	8732	0	0
T62	0	2003	0	0
T63	0	5409	0	0
T64	0	2952	0	0
T65	0	2286	0	0
T66	78607	0	0	0
T67	172403	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233219357	3883	0	0
T16	93524	0	0	0
T25	105680	205	0	0
T30	96859	0	0	0
T31	324952	0	0	0
T32	33916	0	0	0
T39	159762	0	0	0
T43	0	217	0	0
T59	0	91	0	0
T68	517100	0	0	0
T69	131178	0	0	0
T98	400919	0	0	0
T106	0	231	0	0
T107	0	257	0	0
T108	0	226	0	0
T109	0	231	0	0
T110	0	304	0	0
T111	0	141	0	0
T112	0	202	0	0
T113	68466	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233219357	3630	0	0
T16	93524	0	0	0
T25	105680	130	0	0
T30	96859	0	0	0
T31	324952	0	0	0
T32	33916	0	0	0
T39	159762	0	0	0
T43	0	126	0	0
T59	0	75	0	0
T68	517100	0	0	0
T69	131178	0	0	0
T98	400919	0	0	0
T106	0	274	0	0
T107	0	222	0	0
T108	0	173	0	0
T109	0	226	0	0
T110	0	286	0	0
T111	0	155	0	0
T112	0	167	0	0
T113	68466	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233219357	3925	0	0
T16	93524	0	0	0
T25	105680	219	0	0
T30	96859	0	0	0
T31	324952	0	0	0
T32	33916	0	0	0
T39	159762	0	0	0
T43	0	118	0	0
T59	0	83	0	0
T68	517100	0	0	0
T69	131178	0	0	0
T98	400919	0	0	0
T106	0	310	0	0
T107	0	304	0	0
T108	0	185	0	0
T109	0	249	0	0
T110	0	315	0	0
T111	0	145	0	0
T112	0	145	0	0
T113	68466	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233219357	2179	0	0
T16	93524	0	0	0
T25	105680	82	0	0
T30	96859	0	0	0
T31	324952	0	0	0
T32	33916	0	0	0
T39	159762	0	0	0
T43	0	189	0	0
T68	517100	0	0	0
T69	131178	0	0	0
T98	400919	0	0	0
T106	0	201	0	0
T107	0	250	0	0
T108	0	246	0	0
T109	0	263	0	0
T110	0	380	0	0
T111	0	138	0	0
T112	0	281	0	0
T113	68466	0	0	0
T114	0	5	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1233219357	1689	0	0
T16	93524	0	0	0
T25	105680	143	0	0
T30	96859	0	0	0
T31	324952	0	0	0
T32	33916	0	0	0
T39	159762	0	0	0
T43	0	200	0	0
T68	517100	0	0	0
T69	131178	0	0	0
T98	400919	0	0	0
T106	0	192	0	0
T107	0	192	0	0
T108	0	131	0	0
T109	0	202	0	0
T110	0	253	0	0
T111	0	114	0	0
T112	0	180	0	0
T113	68466	0	0	0
T115	0	1	0	0