Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16777432	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

164982759

1

T1

200082

T2

196606

T4

1476

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89497546	1			T1	109697		T2	65536		T4	870
values[0x0]	44464594	1			T1	53112		T2	65646		T4	430
values[0x1]	47798051	1			T1	56988		T2	65424		T4	508

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8526583	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

173233608

1

T1

209961

T2

196606

T4

1629

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	555571	1			T2	768		T4	4		T5	385
valid_sources[0x01]	589038	1			T2	827		T4	7		T5	396
valid_sources[0x02]	568332	1			T2	753		T4	7		T5	428
valid_sources[0x03]	573409	1			T2	753		T4	8		T5	431
valid_sources[0x04]	571943	1			T2	765		T4	6		T5	426
valid_sources[0x05]	651910	1			T2	813		T4	9		T5	456
valid_sources[0x06]	591941	1			T2	793		T4	6		T5	434
valid_sources[0x07]	1607453	1			T1	6418		T2	717		T4	7
valid_sources[0x08]	622550	1			T2	795		T4	4		T5	412
valid_sources[0x09]	566390	1			T2	751		T4	5		T5	414
valid_sources[0x0a]	562900	1			T2	757		T4	11		T5	417
valid_sources[0x0b]	587839	1			T2	694		T4	3		T5	368
valid_sources[0x0c]	553692	1			T2	721		T4	5		T5	415
valid_sources[0x0d]	570760	1			T2	677		T4	7		T5	427
valid_sources[0x0e]	578215	1			T2	686		T4	6		T5	405
valid_sources[0x0f]	557795	1			T2	812		T4	6		T5	400
valid_sources[0x10]	573386	1			T2	898		T4	4		T5	398
valid_sources[0x11]	636271	1			T2	778		T4	10		T5	419
valid_sources[0x12]	617493	1			T2	581		T4	6		T5	399
valid_sources[0x13]	571291	1			T2	776		T4	6		T5	405
valid_sources[0x14]	612898	1			T2	731		T4	7		T5	384
valid_sources[0x15]	583183	1			T2	813		T4	5		T5	411
valid_sources[0x16]	560681	1			T2	840		T4	8		T5	381
valid_sources[0x17]	567529	1			T2	762		T4	5		T5	388
valid_sources[0x18]	556418	1			T2	849		T4	6		T5	418
valid_sources[0x19]	758206	1			T2	710		T4	9		T5	414
valid_sources[0x1a]	583751	1			T2	775		T4	9		T5	394
valid_sources[0x1b]	649372	1			T2	701		T4	9		T5	431
valid_sources[0x1c]	666197	1			T2	771		T4	11		T5	429
valid_sources[0x1d]	1917905	1			T2	823		T4	6		T5	405
valid_sources[0x1e]	556550	1			T2	753		T4	12		T5	405
valid_sources[0x1f]	575991	1			T2	679		T4	7		T5	397
valid_sources[0x20]	570900	1			T2	626		T4	9		T5	425
valid_sources[0x21]	2200010	1			T2	803		T4	11		T5	438
valid_sources[0x22]	581916	1			T2	741		T4	6		T5	414
valid_sources[0x23]	661728	1			T2	690		T4	4		T5	455
valid_sources[0x24]	1989474	1			T2	704		T4	7		T5	386
valid_sources[0x25]	710509	1			T2	739		T4	12		T5	413
valid_sources[0x26]	608405	1			T2	769		T4	9		T5	402
valid_sources[0x27]	618035	1			T2	783		T4	10		T5	424
valid_sources[0x28]	555826	1			T2	724		T4	6		T5	422
valid_sources[0x29]	561218	1			T2	706		T4	9		T5	385
valid_sources[0x2a]	597467	1			T2	736		T4	4		T5	455
valid_sources[0x2b]	565625	1			T2	733		T4	4		T5	439
valid_sources[0x2c]	657110	1			T2	708		T4	1		T5	433
valid_sources[0x2d]	812636	1			T2	765		T4	3		T5	418
valid_sources[0x2e]	831451	1			T1	11454		T2	700		T4	5
valid_sources[0x2f]	570380	1			T2	830		T4	5		T5	400
valid_sources[0x30]	586490	1			T2	708		T4	4		T5	405
valid_sources[0x31]	573810	1			T2	883		T4	8		T5	395
valid_sources[0x32]	625130	1			T2	843		T4	2		T5	380
valid_sources[0x33]	597686	1			T2	787		T4	8		T5	402
valid_sources[0x34]	563354	1			T2	682		T4	6		T5	414
valid_sources[0x35]	600082	1			T2	783		T4	5		T5	414
valid_sources[0x36]	593162	1			T2	708		T4	8		T5	431
valid_sources[0x37]	678380	1			T2	807		T4	9		T5	414
valid_sources[0x38]	603426	1			T2	733		T4	7		T5	423
valid_sources[0x39]	587890	1			T2	841		T4	4		T5	408
valid_sources[0x3a]	549895	1			T2	794		T4	11		T5	405
valid_sources[0x3b]	575946	1			T2	836		T4	9		T5	404
valid_sources[0x3c]	642172	1			T2	794		T4	7		T5	401
valid_sources[0x3d]	3418089	1			T2	748		T4	14		T5	427
valid_sources[0x3e]	594440	1			T1	30551		T2	734		T4	4
valid_sources[0x3f]	560258	1			T2	674		T4	7		T5	453
valid_sources[0x40]	600902	1			T2	773		T4	9		T5	422
valid_sources[0x41]	748274	1			T2	762		T4	3		T5	410
valid_sources[0x42]	557369	1			T2	759		T4	6		T5	418
valid_sources[0x43]	585117	1			T2	754		T4	12		T5	440
valid_sources[0x44]	558154	1			T2	766		T4	3		T5	386
valid_sources[0x45]	599717	1			T2	825		T4	9		T5	414
valid_sources[0x46]	581674	1			T2	701		T4	7		T5	426
valid_sources[0x47]	584757	1			T2	757		T4	7		T5	400
valid_sources[0x48]	581234	1			T2	811		T4	4		T5	407
valid_sources[0x49]	636262	1			T2	732		T4	3		T5	401
valid_sources[0x4a]	694301	1			T2	730		T4	5		T5	410
valid_sources[0x4b]	569241	1			T2	767		T4	6		T5	397
valid_sources[0x4c]	563314	1			T2	805		T4	4		T5	394
valid_sources[0x4d]	576738	1			T2	694		T4	9		T5	427
valid_sources[0x4e]	624163	1			T2	842		T4	8		T5	446
valid_sources[0x4f]	593826	1			T2	805		T4	7		T5	429
valid_sources[0x50]	574970	1			T2	692		T4	9		T5	399
valid_sources[0x51]	2530178	1			T2	783		T4	4		T5	392
valid_sources[0x52]	590113	1			T2	806		T4	3		T5	427
valid_sources[0x53]	577336	1			T2	834		T4	7		T5	452
valid_sources[0x54]	608436	1			T2	800		T4	16		T5	392
valid_sources[0x55]	616123	1			T2	762		T4	9		T5	415
valid_sources[0x56]	1321011	1			T2	814		T4	7		T5	418
valid_sources[0x57]	601212	1			T2	723		T4	12		T5	407
valid_sources[0x58]	590254	1			T1	4198		T2	791		T4	11
valid_sources[0x59]	574730	1			T2	623		T4	12		T5	416
valid_sources[0x5a]	589047	1			T2	535		T4	8		T5	417
valid_sources[0x5b]	594212	1			T2	785		T4	7		T5	388
valid_sources[0x5c]	615622	1			T2	745		T4	8		T5	469
valid_sources[0x5d]	622088	1			T2	825		T4	7		T5	450
valid_sources[0x5e]	566722	1			T2	723		T4	5		T5	404
valid_sources[0x5f]	2098343	1			T2	731		T4	5		T5	432
valid_sources[0x60]	580894	1			T2	637		T4	7		T5	431
valid_sources[0x61]	619210	1			T2	818		T4	8		T5	370
valid_sources[0x62]	564158	1			T2	709		T4	10		T5	390
valid_sources[0x63]	599788	1			T2	806		T4	8		T5	399
valid_sources[0x64]	573120	1			T1	4519		T2	794		T4	11
valid_sources[0x65]	593598	1			T2	699		T4	5		T5	429
valid_sources[0x66]	557683	1			T2	688		T4	5		T5	423
valid_sources[0x67]	621242	1			T1	2503		T2	688		T4	6
valid_sources[0x68]	572322	1			T2	793		T4	6		T5	401
valid_sources[0x69]	626044	1			T2	801		T4	2		T5	381
valid_sources[0x6a]	1426221	1			T2	701		T4	8		T5	414
valid_sources[0x6b]	574347	1			T2	678		T4	9		T5	414
valid_sources[0x6c]	575409	1			T2	767		T4	10		T5	406
valid_sources[0x6d]	684561	1			T2	767		T4	7		T5	433
valid_sources[0x6e]	562080	1			T2	681		T4	4		T5	383
valid_sources[0x6f]	1898860	1			T2	737		T4	5		T5	398
valid_sources[0x70]	2185785	1			T2	735		T4	8		T5	396
valid_sources[0x71]	1602863	1			T2	811		T4	5		T5	449
valid_sources[0x72]	750482	1			T2	829		T4	7		T5	423
valid_sources[0x73]	612752	1			T2	702		T4	8		T5	413
valid_sources[0x74]	627947	1			T2	671		T4	11		T5	420
valid_sources[0x75]	570983	1			T2	837		T4	6		T5	396
valid_sources[0x76]	602116	1			T2	784		T4	2		T5	451
valid_sources[0x77]	616256	1			T2	698		T4	7		T5	387
valid_sources[0x78]	598064	1			T1	17768		T2	773		T4	2
valid_sources[0x79]	562197	1			T2	696		T4	9		T5	399
valid_sources[0x7a]	559684	1			T2	740		T4	11		T5	409
valid_sources[0x7b]	612043	1			T2	749		T4	3		T5	458
valid_sources[0x7c]	609541	1			T2	837		T4	6		T5	428
valid_sources[0x7d]	565319	1			T2	838		T4	2		T5	420
valid_sources[0x7e]	595820	1			T2	778		T4	5		T5	433
valid_sources[0x7f]	609666	1			T2	804		T4	8		T5	424
valid_sources[0x80]	593613	1			T2	789		T4	10		T5	429

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

81067443

1

T1

99811

T2

65536

T4

727

values[0x0]

all_enables

biggest_size

41960277

1

T1

50159

T2

65646

T4

373

values[0x1]

all_enables

biggest_size

41955039

1

T1

50112

T2

65424

T4

376

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46492	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

172842

1

T1

4

T2

16

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	59182	1			T25	827		T26	810		T6	13
values[0x0]	77195	1			T1	9		T2	45		T3	6
values[0x1]	82957	1			T1	11		T2	32		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35529	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

183805

1

T1

6

T2

21

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	686	1			T10	1		T26	9		T100	1
valid_sources[0x01]	833	1			T2	3		T9	1		T25	3
valid_sources[0x02]	1001	1			T9	2		T26	12		T60	2
valid_sources[0x03]	710	1			T25	3		T26	7		T7	5
valid_sources[0x04]	842	1			T11	2		T26	9		T15	1
valid_sources[0x05]	602	1			T9	1		T25	11		T26	3
valid_sources[0x06]	843	1			T1	1		T25	3		T26	18
valid_sources[0x07]	727	1			T9	2		T19	1		T26	11
valid_sources[0x08]	1259	1			T9	1		T25	378		T19	1
valid_sources[0x09]	797	1			T26	9		T60	2		T58	13
valid_sources[0x0a]	900	1			T25	168		T26	11		T20	1
valid_sources[0x0b]	1158	1			T25	1		T26	11		T71	1
valid_sources[0x0c]	1579	1			T10	1		T25	1		T26	4
valid_sources[0x0d]	913	1			T26	13		T60	2		T24	1
valid_sources[0x0e]	756	1			T9	3		T10	1		T25	2
valid_sources[0x0f]	705	1			T48	1		T26	7		T6	2
valid_sources[0x10]	787	1			T1	4		T2	1		T9	2
valid_sources[0x11]	934	1			T26	15		T7	1		T60	1
valid_sources[0x12]	645	1			T26	6		T29	1		T60	3
valid_sources[0x13]	899	1			T9	2		T26	21		T154	2
valid_sources[0x14]	839	1			T26	11		T7	2		T60	1
valid_sources[0x15]	962	1			T9	1		T10	1		T46	1
valid_sources[0x16]	885	1			T26	15		T60	3		T148	1
valid_sources[0x17]	970	1			T2	7		T26	16		T60	2
valid_sources[0x18]	803	1			T9	1		T10	2		T14	4
valid_sources[0x19]	890	1			T3	1		T26	17		T68	3
valid_sources[0x1a]	961	1			T25	23		T26	10		T6	3
valid_sources[0x1b]	921	1			T26	13		T20	2		T7	1
valid_sources[0x1c]	760	1			T25	2		T26	6		T60	1
valid_sources[0x1d]	748	1			T5	13		T10	1		T26	12
valid_sources[0x1e]	1040	1			T25	1		T26	12		T60	1
valid_sources[0x1f]	721	1			T9	1		T19	2		T26	14
valid_sources[0x20]	619	1			T9	3		T25	1		T26	6
valid_sources[0x21]	768	1			T9	1		T25	2		T26	16
valid_sources[0x22]	790	1			T9	1		T19	2		T26	4
valid_sources[0x23]	1032	1			T10	1		T25	4		T26	17
valid_sources[0x24]	946	1			T45	196		T26	17		T7	1
valid_sources[0x25]	896	1			T9	3		T25	9		T26	16
valid_sources[0x26]	720	1			T9	1		T26	21		T50	3
valid_sources[0x27]	741	1			T26	7		T27	1		T30	1
valid_sources[0x28]	777	1			T2	1		T19	2		T26	6
valid_sources[0x29]	769	1			T25	8		T26	19		T60	2
valid_sources[0x2a]	870	1			T26	15		T60	1		T24	2
valid_sources[0x2b]	804	1			T25	2		T26	13		T7	2
valid_sources[0x2c]	696	1			T9	1		T26	7		T60	1
valid_sources[0x2d]	717	1			T2	1		T26	12		T60	1
valid_sources[0x2e]	703	1			T3	1		T9	1		T26	12
valid_sources[0x2f]	787	1			T9	1		T25	1		T26	19
valid_sources[0x30]	837	1			T26	12		T60	2		T155	1
valid_sources[0x31]	1246	1			T2	2		T25	1		T26	10
valid_sources[0x32]	761	1			T25	5		T19	1		T26	12
valid_sources[0x33]	1196	1			T3	1		T26	11		T29	2
valid_sources[0x34]	1114	1			T25	2		T26	6		T7	1
valid_sources[0x35]	854	1			T9	1		T10	1		T26	10
valid_sources[0x36]	956	1			T10	2		T26	15		T30	3
valid_sources[0x37]	888	1			T9	1		T25	8		T26	9
valid_sources[0x38]	937	1			T26	16		T50	6		T60	2
valid_sources[0x39]	760	1			T25	2		T26	21		T31	1
valid_sources[0x3a]	1077	1			T25	3		T26	19		T60	1
valid_sources[0x3b]	787	1			T2	1		T26	19		T60	1
valid_sources[0x3c]	1273	1			T26	5		T30	1		T7	1
valid_sources[0x3d]	835	1			T2	4		T9	1		T26	11
valid_sources[0x3e]	727	1			T2	2		T9	1		T25	1
valid_sources[0x3f]	744	1			T9	1		T48	1		T26	7
valid_sources[0x40]	836	1			T9	2		T10	1		T25	2
valid_sources[0x41]	877	1			T9	2		T25	3		T26	8
valid_sources[0x42]	817	1			T2	1		T26	16		T28	17
valid_sources[0x43]	698	1			T9	1		T26	14		T29	1
valid_sources[0x44]	873	1			T2	1		T26	11		T69	1
valid_sources[0x45]	955	1			T9	1		T25	90		T26	3
valid_sources[0x46]	628	1			T9	1		T10	2		T25	1
valid_sources[0x47]	666	1			T2	1		T25	12		T26	9
valid_sources[0x48]	751	1			T10	1		T25	13		T26	11
valid_sources[0x49]	729	1			T26	11		T15	1		T30	1
valid_sources[0x4a]	1132	1			T26	10		T60	3		T58	20
valid_sources[0x4b]	794	1			T26	22		T7	4		T60	1
valid_sources[0x4c]	804	1			T26	16		T6	1		T60	3
valid_sources[0x4d]	794	1			T25	2		T79	1		T26	23
valid_sources[0x4e]	686	1			T25	1		T26	10		T60	1
valid_sources[0x4f]	821	1			T9	1		T10	1		T25	126
valid_sources[0x50]	945	1			T9	2		T26	7		T50	9
valid_sources[0x51]	1289	1			T9	2		T25	78		T26	10
valid_sources[0x52]	814	1			T26	10		T29	1		T6	1
valid_sources[0x53]	1190	1			T26	14		T115	1		T20	2
valid_sources[0x54]	913	1			T2	6		T9	1		T19	1
valid_sources[0x55]	887	1			T26	4		T49	2		T7	2
valid_sources[0x56]	692	1			T3	1		T26	20		T60	1
valid_sources[0x57]	1112	1			T9	1		T26	4		T29	2
valid_sources[0x58]	1069	1			T25	8		T26	7		T6	1
valid_sources[0x59]	932	1			T26	15		T52	11		T60	2
valid_sources[0x5a]	986	1			T26	17		T7	2		T60	1
valid_sources[0x5b]	811	1			T9	1		T26	21		T7	1
valid_sources[0x5c]	795	1			T25	93		T26	10		T60	3
valid_sources[0x5d]	860	1			T2	1		T10	1		T26	17
valid_sources[0x5e]	832	1			T9	1		T26	17		T7	1
valid_sources[0x5f]	795	1			T26	7		T29	3		T58	9
valid_sources[0x60]	867	1			T26	11		T15	1		T30	1
valid_sources[0x61]	1294	1			T9	3		T26	12		T49	4
valid_sources[0x62]	707	1			T51	4		T26	7		T60	2
valid_sources[0x63]	723	1			T2	2		T9	1		T26	8
valid_sources[0x64]	717	1			T25	3		T51	2		T26	10
valid_sources[0x65]	635	1			T1	6		T26	12		T50	5
valid_sources[0x66]	1008	1			T9	1		T10	2		T25	2
valid_sources[0x67]	743	1			T26	24		T7	2		T60	1
valid_sources[0x68]	666	1			T4	2		T26	13		T60	2
valid_sources[0x69]	1060	1			T26	18		T60	1		T24	3
valid_sources[0x6a]	778	1			T25	13		T26	6		T7	1
valid_sources[0x6b]	744	1			T3	1		T10	1		T26	11
valid_sources[0x6c]	815	1			T26	20		T20	1		T60	3
valid_sources[0x6d]	875	1			T9	1		T25	2		T26	11
valid_sources[0x6e]	725	1			T25	1		T26	18		T7	1
valid_sources[0x6f]	1143	1			T26	5		T6	2		T60	1
valid_sources[0x70]	740	1			T26	6		T60	2		T58	6
valid_sources[0x71]	794	1			T3	1		T9	1		T26	7
valid_sources[0x72]	1015	1			T26	13		T30	1		T58	13
valid_sources[0x73]	794	1			T2	3		T9	1		T25	1
valid_sources[0x74]	930	1			T1	6		T25	2		T26	9
valid_sources[0x75]	661	1			T25	3		T26	7		T58	16
valid_sources[0x76]	717	1			T25	1		T26	15		T7	2
valid_sources[0x77]	956	1			T19	2		T26	11		T29	2
valid_sources[0x78]	686	1			T26	6		T7	2		T60	1
valid_sources[0x79]	895	1			T25	76		T26	14		T6	1
valid_sources[0x7a]	652	1			T25	4		T26	12		T60	1
valid_sources[0x7b]	800	1			T9	2		T25	2		T26	11
valid_sources[0x7c]	817	1			T10	1		T19	2		T26	17
valid_sources[0x7d]	707	1			T9	2		T12	3		T26	19
valid_sources[0x7e]	771	1			T2	1		T9	2		T10	1
valid_sources[0x7f]	679	1			T10	1		T25	1		T26	22
valid_sources[0x80]	768	1			T3	1		T26	15		T7	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45572

1

T25

757

T26

752

T6

8

values[0x0]

all_enables

biggest_size

65150

1

T1

3

T2

11

T3

2

values[0x1]

all_enables

biggest_size

62120

1

T1

1

T2

5

T5

2