Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16667311

1

T1

19715

T4

332

T5

9676

full_word

161521925

1

T1

200082

T2

196606

T4

1476

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	178188886	1			T1	219797		T2	196606		T4	1808
auto[TlIntgErrCmd]	130	1			T72	4		T73	6		T74	4
auto[TlIntgErrData]	119	1			T72	4		T73	6		T74	2
auto[TlIntgErrBoth]	101	1			T72	12		T73	8		T74	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85814207

1

T1

109697

T2

65536

T4

870

auto[1]

92375029

1

T1

110100

T2

131070

T4

938

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8138324	1			T1	9886		T4	143		T5	4855
auto[TlIntgErrNone]	partial	auto[1]	8528666	1			T1	9829		T4	189		T5	4821
auto[TlIntgErrNone]	full_word	auto[0]	77675725	1			T1	99811		T2	65536		T4	727
auto[TlIntgErrNone]	full_word	auto[1]	83846171	1			T1	100271		T2	131070		T4	749
auto[TlIntgErrCmd]	partial	auto[0]	56	1			T73	1		T74	2		T129	3
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T72	4		T73	3		T74	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T73	1		T137	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T73	1		T74	1		T131	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T72	4		T73	2		T74	2
auto[TlIntgErrData]	partial	auto[1]	56	1			T73	3		T133	4		T129	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T73	1		T138	1		T139	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T129	1		T134	1		T132	2
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T72	4		T74	3		T133	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T72	7		T73	6		T74	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T73	1		T140	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T72	1		T73	1		T129	2