Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	707864	1			T5	267		T12	929		T46	4
auto[1]	11360541	1			T1	50909		T4	869		T5	2180
auto[2]	524365	1			T5	130		T12	603		T46	3
auto[3]	11115957	1			T1	50884		T4	937		T5	2088

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14895917	1			T1	84602		T4	1163		T5	3302
auto[1]	2219457	1			T1	8186		T4	311		T5	515
auto[2]	2269704	1			T1	8226		T4	268		T5	751
auto[3]	4323649	1			T1	779		T4	64		T5	97

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9822700

1

T1

101790

T4

1806

T5

4665

auto[1]

13886027

1

T1

3

T10

1

T48

120461

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	295234	1			T5	215		T12	1		T46	4
auto[0]	auto[0]	auto[1]	30506	1			T5	24		T12	9		T47	55
auto[0]	auto[0]	auto[2]	30590	1			T5	25		T12	8		T47	47
auto[0]	auto[0]	auto[3]	61310	1			T5	3		T12	911		T47	5
auto[0]	auto[1]	auto[0]	3528023	1			T1	42295		T4	566		T5	1655
auto[0]	auto[1]	auto[1]	365453	1			T1	4102		T4	160		T5	346
auto[0]	auto[1]	auto[2]	384918	1			T1	4144		T4	116		T5	149
auto[0]	auto[1]	auto[3]	365012	1			T1	367		T4	27		T5	30
auto[0]	auto[2]	auto[0]	204490	1			T46	3		T47	517		T30	860
auto[0]	auto[2]	auto[1]	24886	1			T47	60		T30	73		T100	379
auto[0]	auto[2]	auto[2]	25941	1			T5	114		T12	8		T47	43
auto[0]	auto[2]	auto[3]	44424	1			T5	16		T12	595		T47	2
auto[0]	auto[3]	auto[0]	3383816	1			T1	42305		T4	597		T5	1432
auto[0]	auto[3]	auto[1]	366446	1			T1	4083		T4	151		T5	145
auto[0]	auto[3]	auto[2]	378300	1			T1	4082		T4	152		T5	463
auto[0]	auto[3]	auto[3]	333351	1			T1	412		T4	37		T5	48
auto[1]	auto[0]	auto[0]	9592	1			T148	208		T149	505		T150	153
auto[1]	auto[0]	auto[1]	43562	1			T148	939		T149	2314		T150	717
auto[1]	auto[0]	auto[2]	43418	1			T148	911		T149	2256		T150	791
auto[1]	auto[0]	auto[3]	193652	1			T100	2		T148	4238		T149	10030
auto[1]	auto[1]	auto[0]	3736012	1			T1	1		T48	49994		T51	93553
auto[1]	auto[1]	auto[1]	694460	1			T48	4811		T51	8419		T61	5167
auto[1]	auto[1]	auto[2]	685112	1			T48	5055		T51	9189		T61	5787
auto[1]	auto[1]	auto[3]	1601551	1			T48	519		T51	804		T61	554
auto[1]	auto[2]	auto[0]	5785	1			T149	330		T151	771		T152	707
auto[1]	auto[2]	auto[1]	26351	1			T149	1339		T151	3492		T152	3172
auto[1]	auto[2]	auto[2]	34883	1			T148	864		T149	2036		T150	620
auto[1]	auto[2]	auto[3]	157605	1			T148	3814		T149	9590		T153	2
auto[1]	auto[3]	auto[0]	3732965	1			T1	1		T10	1		T48	49897
auto[1]	auto[3]	auto[1]	667793	1			T1	1		T48	4827		T51	9250
auto[1]	auto[3]	auto[2]	686542	1			T48	4866		T51	8453		T61	5308
auto[1]	auto[3]	auto[3]	1566744	1			T48	492		T51	838		T61	538