Line Coverage for Module :
prim_mubi8_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Module :
prim_mubi8_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1160126933 |
1160003591 |
0 |
0 |
T1 |
101864 |
101858 |
0 |
0 |
T2 |
394234 |
394165 |
0 |
0 |
T3 |
962 |
896 |
0 |
0 |
T4 |
68621 |
68552 |
0 |
0 |
T5 |
110344 |
110335 |
0 |
0 |
T9 |
692092 |
692036 |
0 |
0 |
T10 |
171582 |
171576 |
0 |
0 |
T11 |
69437 |
69383 |
0 |
0 |
T12 |
235786 |
235727 |
0 |
0 |
T13 |
78004 |
77925 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1160126933 |
1159990473 |
0 |
2700 |
T1 |
101864 |
101857 |
0 |
3 |
T2 |
394234 |
394162 |
0 |
3 |
T3 |
962 |
893 |
0 |
3 |
T4 |
68621 |
68549 |
0 |
3 |
T5 |
110344 |
110334 |
0 |
3 |
T9 |
692092 |
692033 |
0 |
3 |
T10 |
171582 |
171576 |
0 |
3 |
T11 |
69437 |
69380 |
0 |
3 |
T12 |
235786 |
235724 |
0 |
3 |
T13 |
78004 |
77922 |
0 |
3 |