Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1171581423	258391	0	0
ctrl_regwen_rd_A	1171581423	4781	0	0
exec_rd_A	1171581423	4365	0	0
exec_regwen_rd_A	1171581423	4469	0	0
readback_rd_A	1171581423	3143	0	0
readback_regwen_rd_A	1171581423	2609	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171581423	258391	0	0
T14	1106	0	0	0
T19	318073	0	0	0
T25	107282	4522	0	0
T26	97859	5214	0	0
T28	0	1724	0	0
T45	103555	0	0	0
T46	89722	0	0	0
T48	266840	0	0	0
T51	513852	0	0	0
T53	0	4351	0	0
T54	0	5564	0	0
T55	0	4497	0	0
T58	0	5185	0	0
T61	330608	0	0	0
T63	0	9719	0	0
T64	0	7355	0	0
T66	0	4107	0	0
T79	78625	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171581423	4781	0	0
T14	1106	0	0	0
T19	318073	0	0	0
T25	107282	298	0	0
T26	97859	0	0	0
T45	103555	0	0	0
T46	89722	0	0	0
T48	266840	0	0	0
T51	513852	0	0	0
T55	0	305	0	0
T61	330608	0	0	0
T79	78625	0	0	0
T118	0	124	0	0
T119	0	57	0	0
T120	0	195	0	0
T121	0	176	0	0
T122	0	225	0	0
T123	0	182	0	0
T124	0	343	0	0
T125	0	168	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171581423	4365	0	0
T14	1106	0	0	0
T19	318073	0	0	0
T25	107282	218	0	0
T26	97859	0	0	0
T45	103555	0	0	0
T46	89722	0	0	0
T48	266840	0	0	0
T51	513852	0	0	0
T55	0	269	0	0
T61	330608	0	0	0
T79	78625	0	0	0
T118	0	150	0	0
T119	0	57	0	0
T120	0	204	0	0
T121	0	191	0	0
T122	0	249	0	0
T123	0	166	0	0
T124	0	263	0	0
T125	0	156	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171581423	4469	0	0
T14	1106	0	0	0
T19	318073	0	0	0
T25	107282	253	0	0
T26	97859	0	0	0
T45	103555	0	0	0
T46	89722	0	0	0
T48	266840	0	0	0
T51	513852	0	0	0
T55	0	287	0	0
T61	330608	0	0	0
T79	78625	0	0	0
T118	0	121	0	0
T119	0	79	0	0
T120	0	251	0	0
T121	0	238	0	0
T122	0	161	0	0
T123	0	149	0	0
T124	0	397	0	0
T125	0	171	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171581423	3143	0	0
T14	1106	0	0	0
T19	318073	0	0	0
T25	107282	214	0	0
T26	97859	0	0	0
T45	103555	0	0	0
T46	89722	0	0	0
T48	266840	0	0	0
T51	513852	0	0	0
T55	0	282	0	0
T61	330608	0	0	0
T79	78625	0	0	0
T118	0	104	0	0
T119	0	24	0	0
T120	0	171	0	0
T121	0	191	0	0
T122	0	237	0	0
T123	0	170	0	0
T124	0	405	0	0
T125	0	117	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1171581423	2609	0	0
T14	1106	0	0	0
T19	318073	0	0	0
T25	107282	161	0	0
T26	97859	0	0	0
T45	103555	0	0	0
T46	89722	0	0	0
T48	266840	0	0	0
T51	513852	0	0	0
T55	0	188	0	0
T61	330608	0	0	0
T79	78625	0	0	0
T118	0	127	0	0
T119	0	22	0	0
T120	0	163	0	0
T121	0	139	0	0
T122	0	179	0	0
T123	0	124	0	0
T124	0	272	0	0
T125	0	131	0	0