Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16184208	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

151417855

1

T1

720896

T2

1290

T3

112183

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82362279	1			T1	360448		T2	719		T3	61635
values[0x0]	41011587	1			T1	180149		T2	363		T3	29990
values[0x1]	44228197	1			T1	180299		T2	356		T3	31836

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8231882	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

159370181

1

T1

720896

T2

1362

T3

117846

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	508755	1			T1	2789		T2	1		T3	530
valid_sources[0x01]	544151	1			T1	2844		T2	7		T3	517
valid_sources[0x02]	540773	1			T1	2874		T2	2		T3	462
valid_sources[0x03]	547640	1			T1	2777		T2	11		T3	443
valid_sources[0x04]	553037	1			T1	2867		T2	1		T3	484
valid_sources[0x05]	962047	1			T1	2803		T2	6		T3	488
valid_sources[0x06]	509407	1			T1	2866		T2	11		T3	443
valid_sources[0x07]	540796	1			T1	2783		T2	1		T3	475
valid_sources[0x08]	523565	1			T1	2832		T2	7		T3	520
valid_sources[0x09]	520903	1			T1	2769		T2	6		T3	429
valid_sources[0x0a]	563232	1			T1	2781		T2	1		T3	494
valid_sources[0x0b]	547031	1			T1	2818		T2	1		T3	461
valid_sources[0x0c]	1885426	1			T1	2939		T2	11		T3	488
valid_sources[0x0d]	512050	1			T1	2845		T2	9		T3	484
valid_sources[0x0e]	522495	1			T1	2831		T2	10		T3	498
valid_sources[0x0f]	533959	1			T1	2813		T2	1		T3	521
valid_sources[0x10]	513108	1			T1	2753		T2	14		T3	526
valid_sources[0x11]	611330	1			T1	2835		T2	7		T3	450
valid_sources[0x12]	530421	1			T1	2791		T2	3		T3	493
valid_sources[0x13]	581133	1			T1	2881		T3	508		T4	32
valid_sources[0x14]	508454	1			T1	2890		T2	5		T3	473
valid_sources[0x15]	572362	1			T1	2761		T2	1		T3	521
valid_sources[0x16]	558267	1			T1	2928		T2	10		T3	478
valid_sources[0x17]	533311	1			T1	2789		T2	13		T3	499
valid_sources[0x18]	1776254	1			T1	2828		T3	487		T4	27
valid_sources[0x19]	576066	1			T1	2770		T3	510		T4	27
valid_sources[0x1a]	517850	1			T1	2799		T2	8		T3	458
valid_sources[0x1b]	530363	1			T1	2758		T2	7		T3	486
valid_sources[0x1c]	1428744	1			T1	2766		T2	5		T3	471
valid_sources[0x1d]	552068	1			T1	2794		T2	6		T3	500
valid_sources[0x1e]	502732	1			T1	2930		T2	4		T3	505
valid_sources[0x1f]	526046	1			T1	2770		T2	4		T3	453
valid_sources[0x20]	537322	1			T1	2704		T2	3		T3	544
valid_sources[0x21]	2140912	1			T1	2874		T2	2		T3	517
valid_sources[0x22]	546909	1			T1	2840		T2	10		T3	498
valid_sources[0x23]	1195109	1			T1	2774		T2	6		T3	478
valid_sources[0x24]	549283	1			T1	2850		T2	18		T3	446
valid_sources[0x25]	516284	1			T1	2851		T2	3		T3	492
valid_sources[0x26]	534074	1			T1	2725		T2	12		T3	481
valid_sources[0x27]	509089	1			T1	2734		T2	15		T3	495
valid_sources[0x28]	573439	1			T1	2844		T2	6		T3	466
valid_sources[0x29]	1129010	1			T1	2829		T2	2		T3	462
valid_sources[0x2a]	1369038	1			T1	2806		T2	5		T3	452
valid_sources[0x2b]	535372	1			T1	2764		T2	4		T3	503
valid_sources[0x2c]	547775	1			T1	2852		T2	12		T3	500
valid_sources[0x2d]	540904	1			T1	2831		T2	4		T3	512
valid_sources[0x2e]	571440	1			T1	2814		T2	8		T3	501
valid_sources[0x2f]	531065	1			T1	2737		T2	3		T3	444
valid_sources[0x30]	541469	1			T1	2918		T2	8		T3	508
valid_sources[0x31]	619120	1			T1	2726		T2	6		T3	485
valid_sources[0x32]	539041	1			T1	2728		T2	11		T3	449
valid_sources[0x33]	528263	1			T1	2841		T2	9		T3	463
valid_sources[0x34]	592161	1			T1	2897		T2	2		T3	468
valid_sources[0x35]	512118	1			T1	2882		T2	3		T3	487
valid_sources[0x36]	530509	1			T1	2743		T3	529		T4	30
valid_sources[0x37]	512749	1			T1	2804		T3	442		T4	33
valid_sources[0x38]	2023571	1			T1	2814		T2	4		T3	550
valid_sources[0x39]	719086	1			T1	2814		T2	6		T3	473
valid_sources[0x3a]	511884	1			T1	2611		T2	24		T3	511
valid_sources[0x3b]	550666	1			T1	2825		T2	5		T3	479
valid_sources[0x3c]	515565	1			T1	2873		T3	516		T4	29
valid_sources[0x3d]	745752	1			T1	2859		T2	6		T3	488
valid_sources[0x3e]	540866	1			T1	2797		T2	1		T3	475
valid_sources[0x3f]	540928	1			T1	2716		T2	4		T3	475
valid_sources[0x40]	515770	1			T1	2766		T2	11		T3	470
valid_sources[0x41]	558725	1			T1	2714		T2	4		T3	447
valid_sources[0x42]	525197	1			T1	2870		T2	2		T3	508
valid_sources[0x43]	558928	1			T1	2825		T2	1		T3	386
valid_sources[0x44]	524755	1			T1	2863		T2	1		T3	493
valid_sources[0x45]	555293	1			T1	2749		T2	4		T3	462
valid_sources[0x46]	750014	1			T1	2851		T2	20		T3	476
valid_sources[0x47]	528933	1			T1	2840		T2	1		T3	435
valid_sources[0x48]	1044322	1			T1	2879		T2	1		T3	470
valid_sources[0x49]	516606	1			T1	2868		T3	484		T4	27
valid_sources[0x4a]	536283	1			T1	2838		T2	8		T3	472
valid_sources[0x4b]	513904	1			T1	2829		T2	7		T3	437
valid_sources[0x4c]	521412	1			T1	2750		T2	14		T3	462
valid_sources[0x4d]	759245	1			T1	2776		T2	5		T3	477
valid_sources[0x4e]	583115	1			T1	2788		T2	6		T3	467
valid_sources[0x4f]	524267	1			T1	2818		T2	4		T3	454
valid_sources[0x50]	2113368	1			T1	2828		T2	10		T3	466
valid_sources[0x51]	521082	1			T1	2901		T2	1		T3	486
valid_sources[0x52]	550058	1			T1	2823		T2	1		T3	500
valid_sources[0x53]	562254	1			T1	2755		T2	4		T3	537
valid_sources[0x54]	552507	1			T1	2754		T2	7		T3	479
valid_sources[0x55]	583352	1			T1	2822		T2	5		T3	466
valid_sources[0x56]	562232	1			T1	2819		T2	17		T3	565
valid_sources[0x57]	516918	1			T1	2844		T2	2		T3	502
valid_sources[0x58]	504180	1			T1	2756		T2	2		T3	452
valid_sources[0x59]	569677	1			T1	2709		T2	8		T3	477
valid_sources[0x5a]	1888536	1			T1	2840		T2	18		T3	489
valid_sources[0x5b]	542200	1			T1	2827		T2	6		T3	452
valid_sources[0x5c]	540314	1			T1	2819		T3	450		T4	35
valid_sources[0x5d]	540374	1			T1	2720		T2	4		T3	464
valid_sources[0x5e]	631425	1			T1	2849		T3	483		T4	33
valid_sources[0x5f]	574764	1			T1	2770		T2	13		T3	449
valid_sources[0x60]	526408	1			T1	2847		T2	2		T3	439
valid_sources[0x61]	597070	1			T1	2734		T2	6		T3	469
valid_sources[0x62]	563823	1			T1	2811		T2	11		T3	486
valid_sources[0x63]	512273	1			T1	2832		T2	3		T3	507
valid_sources[0x64]	518744	1			T1	2847		T2	1		T3	532
valid_sources[0x65]	533564	1			T1	2892		T2	4		T3	476
valid_sources[0x66]	527349	1			T1	2851		T2	4		T3	486
valid_sources[0x67]	571304	1			T1	2768		T2	9		T3	496
valid_sources[0x68]	512419	1			T1	2778		T2	3		T3	541
valid_sources[0x69]	541436	1			T1	2830		T2	3		T3	483
valid_sources[0x6a]	514018	1			T1	2816		T2	5		T3	431
valid_sources[0x6b]	546229	1			T1	2891		T2	7		T3	457
valid_sources[0x6c]	1362059	1			T1	2741		T2	3		T3	462
valid_sources[0x6d]	569064	1			T1	2869		T2	5		T3	446
valid_sources[0x6e]	624677	1			T1	2748		T2	1		T3	485
valid_sources[0x6f]	584886	1			T1	2756		T2	3		T3	491
valid_sources[0x70]	572236	1			T1	2847		T2	4		T3	486
valid_sources[0x71]	597878	1			T1	2900		T2	4		T3	447
valid_sources[0x72]	560711	1			T1	2711		T2	17		T3	509
valid_sources[0x73]	538856	1			T1	2812		T2	3		T3	504
valid_sources[0x74]	511080	1			T1	2837		T2	2		T3	519
valid_sources[0x75]	524142	1			T1	2715		T2	7		T3	542
valid_sources[0x76]	580281	1			T1	2797		T2	9		T3	515
valid_sources[0x77]	550076	1			T1	2776		T2	2		T3	488
valid_sources[0x78]	505489	1			T1	2823		T2	1		T3	501
valid_sources[0x79]	624208	1			T1	2778		T2	2		T3	484
valid_sources[0x7a]	563918	1			T1	2894		T3	418		T4	20
valid_sources[0x7b]	519786	1			T1	2808		T2	4		T3	488
valid_sources[0x7c]	547549	1			T1	2819		T2	1		T3	459
valid_sources[0x7d]	527579	1			T1	2820		T2	11		T3	471
valid_sources[0x7e]	510148	1			T1	2797		T2	6		T3	447
valid_sources[0x7f]	523307	1			T1	2814		T2	4		T3	478
valid_sources[0x80]	915902	1			T1	2824		T2	4		T3	451

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

74228512

1

T1

360448

T2

635

T3

56047

values[0x0]

all_enables

biggest_size

38596306

1

T1

180149

T2

344

T3

28241

values[0x1]

all_enables

biggest_size

38593037

1

T1

180299

T2

311

T3

27895

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47606	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

174750

1

T1

3

T2

5

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	60475	1			T2	14		T4	912		T26	10
values[0x0]	77961	1			T1	7		T2	7		T3	17
values[0x1]	83920	1			T1	4		T2	4		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

185796

1

T1

3

T2

7

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	986	1			T4	14		T24	13		T20	3
valid_sources[0x01]	989	1			T3	1		T4	11		T39	6
valid_sources[0x02]	784	1			T4	17		T26	2		T39	2
valid_sources[0x03]	970	1			T4	10		T26	3		T39	7
valid_sources[0x04]	737	1			T1	1		T4	12		T26	1
valid_sources[0x05]	812	1			T4	12		T24	14		T25	23
valid_sources[0x06]	792	1			T4	16		T24	16		T44	19
valid_sources[0x07]	974	1			T4	11		T26	1		T5	2
valid_sources[0x08]	836	1			T4	13		T39	4		T24	11
valid_sources[0x09]	1040	1			T4	16		T24	12		T44	27
valid_sources[0x0a]	957	1			T4	16		T24	23		T44	21
valid_sources[0x0b]	942	1			T4	11		T24	24		T44	20
valid_sources[0x0c]	682	1			T4	8		T24	29		T44	15
valid_sources[0x0d]	810	1			T2	25		T4	19		T6	1
valid_sources[0x0e]	1168	1			T4	17		T24	16		T44	7
valid_sources[0x0f]	714	1			T4	8		T129	1		T6	1
valid_sources[0x10]	806	1			T4	10		T24	12		T44	14
valid_sources[0x11]	1138	1			T4	14		T24	3		T44	14
valid_sources[0x12]	673	1			T3	1		T4	9		T24	21
valid_sources[0x13]	910	1			T4	30		T24	15		T44	6
valid_sources[0x14]	681	1			T4	11		T59	2		T24	14
valid_sources[0x15]	811	1			T3	2		T4	12		T6	1
valid_sources[0x16]	875	1			T4	9		T22	4		T24	16
valid_sources[0x17]	1117	1			T4	12		T24	5		T25	11
valid_sources[0x18]	776	1			T4	12		T39	3		T24	13
valid_sources[0x19]	878	1			T1	1		T4	11		T24	13
valid_sources[0x1a]	797	1			T4	10		T14	1		T24	12
valid_sources[0x1b]	735	1			T4	13		T22	5		T129	2
valid_sources[0x1c]	853	1			T4	15		T22	3		T24	14
valid_sources[0x1d]	1006	1			T4	12		T16	1		T24	13
valid_sources[0x1e]	789	1			T4	16		T38	13		T39	1
valid_sources[0x1f]	832	1			T3	5		T4	15		T59	1
valid_sources[0x20]	1173	1			T4	22		T129	1		T24	18
valid_sources[0x21]	693	1			T1	1		T4	12		T24	9
valid_sources[0x22]	830	1			T4	19		T24	19		T44	17
valid_sources[0x23]	732	1			T4	8		T5	1		T24	6
valid_sources[0x24]	652	1			T4	14		T13	2		T24	11
valid_sources[0x25]	687	1			T4	15		T24	18		T44	17
valid_sources[0x26]	977	1			T4	16		T8	1		T39	3
valid_sources[0x27]	881	1			T4	17		T24	16		T25	54
valid_sources[0x28]	712	1			T4	13		T6	1		T24	11
valid_sources[0x29]	790	1			T4	10		T24	18		T20	1
valid_sources[0x2a]	906	1			T4	10		T24	22		T44	11
valid_sources[0x2b]	795	1			T4	14		T22	4		T129	2
valid_sources[0x2c]	729	1			T4	7		T8	1		T39	1
valid_sources[0x2d]	1003	1			T4	13		T14	1		T57	2
valid_sources[0x2e]	893	1			T4	19		T10	1		T22	4
valid_sources[0x2f]	1050	1			T4	17		T24	11		T25	1
valid_sources[0x30]	785	1			T4	18		T8	2		T16	1
valid_sources[0x31]	1359	1			T4	12		T21	1		T24	11
valid_sources[0x32]	825	1			T4	13		T24	24		T20	1
valid_sources[0x33]	680	1			T4	11		T6	1		T24	9
valid_sources[0x34]	994	1			T4	9		T22	2		T39	4
valid_sources[0x35]	947	1			T4	25		T24	17		T44	10
valid_sources[0x36]	807	1			T4	8		T39	2		T24	8
valid_sources[0x37]	1091	1			T4	6		T16	1		T24	21
valid_sources[0x38]	724	1			T4	13		T11	1		T24	9
valid_sources[0x39]	1521	1			T4	17		T26	1		T129	2
valid_sources[0x3a]	752	1			T3	1		T4	13		T24	3
valid_sources[0x3b]	967	1			T4	17		T26	1		T24	16
valid_sources[0x3c]	1081	1			T4	15		T5	9		T16	1
valid_sources[0x3d]	777	1			T4	17		T24	13		T44	30
valid_sources[0x3e]	812	1			T4	18		T22	3		T6	1
valid_sources[0x3f]	646	1			T4	7		T13	2		T6	1
valid_sources[0x40]	665	1			T4	14		T39	11		T24	17
valid_sources[0x41]	921	1			T4	13		T24	13		T25	166
valid_sources[0x42]	687	1			T4	9		T39	16		T24	8
valid_sources[0x43]	857	1			T4	13		T22	1		T24	10
valid_sources[0x44]	833	1			T4	17		T14	1		T24	11
valid_sources[0x45]	708	1			T4	18		T26	1		T39	1
valid_sources[0x46]	835	1			T4	13		T39	4		T6	1
valid_sources[0x47]	969	1			T3	3		T4	14		T21	1
valid_sources[0x48]	923	1			T4	24		T7	80		T6	1
valid_sources[0x49]	935	1			T4	20		T22	1		T16	1
valid_sources[0x4a]	664	1			T4	13		T24	13		T44	11
valid_sources[0x4b]	943	1			T4	6		T21	2		T39	2
valid_sources[0x4c]	819	1			T4	18		T6	1		T24	13
valid_sources[0x4d]	723	1			T4	19		T26	1		T39	1
valid_sources[0x4e]	826	1			T4	20		T24	15		T20	1
valid_sources[0x4f]	631	1			T4	19		T39	2		T24	16
valid_sources[0x50]	739	1			T4	11		T39	1		T14	1
valid_sources[0x51]	1026	1			T4	14		T5	1		T15	1
valid_sources[0x52]	876	1			T4	13		T24	23		T44	23
valid_sources[0x53]	1106	1			T4	6		T21	1		T22	6
valid_sources[0x54]	1392	1			T4	11		T19	4		T26	2
valid_sources[0x55]	812	1			T4	9		T6	1		T24	11
valid_sources[0x56]	1085	1			T4	13		T24	12		T20	3
valid_sources[0x57]	908	1			T4	17		T59	1		T39	1
valid_sources[0x58]	754	1			T4	8		T22	4		T39	5
valid_sources[0x59]	1057	1			T4	23		T59	2		T131	2
valid_sources[0x5a]	805	1			T4	12		T21	1		T39	1
valid_sources[0x5b]	732	1			T4	11		T39	10		T24	13
valid_sources[0x5c]	736	1			T4	11		T24	10		T44	24
valid_sources[0x5d]	841	1			T4	10		T39	6		T24	17
valid_sources[0x5e]	684	1			T4	13		T39	2		T24	16
valid_sources[0x5f]	976	1			T4	13		T129	1		T132	1
valid_sources[0x60]	1008	1			T4	13		T24	16		T25	1
valid_sources[0x61]	971	1			T4	21		T24	30		T20	2
valid_sources[0x62]	783	1			T4	15		T14	1		T24	23
valid_sources[0x63]	1078	1			T4	14		T24	20		T44	13
valid_sources[0x64]	1038	1			T4	12		T24	8		T25	190
valid_sources[0x65]	790	1			T4	10		T24	13		T20	1
valid_sources[0x66]	794	1			T4	11		T24	8		T20	1
valid_sources[0x67]	709	1			T4	7		T26	1		T5	4
valid_sources[0x68]	919	1			T4	16		T39	1		T24	14
valid_sources[0x69]	791	1			T4	25		T93	3		T24	11
valid_sources[0x6a]	688	1			T4	12		T24	14		T44	17
valid_sources[0x6b]	823	1			T4	8		T39	1		T6	1
valid_sources[0x6c]	1206	1			T4	12		T19	1		T14	1
valid_sources[0x6d]	825	1			T4	8		T9	1		T6	2
valid_sources[0x6e]	1532	1			T4	15		T24	14		T44	19
valid_sources[0x6f]	876	1			T1	1		T4	13		T16	1
valid_sources[0x70]	807	1			T4	13		T26	3		T28	1
valid_sources[0x71]	1051	1			T4	10		T24	21		T44	22
valid_sources[0x72]	599	1			T4	13		T21	1		T16	2
valid_sources[0x73]	936	1			T3	2		T4	12		T39	2
valid_sources[0x74]	735	1			T4	24		T24	5		T20	1
valid_sources[0x75]	705	1			T4	12		T19	3		T26	1
valid_sources[0x76]	898	1			T4	20		T39	9		T24	12
valid_sources[0x77]	823	1			T4	9		T24	15		T44	16
valid_sources[0x78]	1101	1			T4	15		T26	2		T24	8
valid_sources[0x79]	1066	1			T4	9		T24	16		T44	36
valid_sources[0x7a]	662	1			T4	13		T24	9		T44	5
valid_sources[0x7b]	958	1			T4	8		T24	6		T44	10
valid_sources[0x7c]	750	1			T3	4		T4	20		T22	2
valid_sources[0x7d]	835	1			T4	7		T59	2		T129	1
valid_sources[0x7e]	786	1			T4	15		T22	1		T39	6
valid_sources[0x7f]	802	1			T4	13		T24	15		T44	10
valid_sources[0x80]	764	1			T4	17		T24	14		T44	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46721

1

T2

5

T4

845

T26

6

values[0x0]

all_enables

biggest_size

65369

1

T1

1

T3

8

T4

1153

values[0x1]

all_enables

biggest_size

62660

1

T1

2

T3

1

T4

1211