Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16104433

1

T2

57

T3

9630

T4

4636

full_word

148102619

1

T1

720896

T2

426

T3

95824

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	164206762	1			T1	720896		T2	483		T3	105454
auto[TlIntgErrCmd]	100	1			T54	8		T55	2		T56	6
auto[TlIntgErrData]	96	1			T54	3		T55	3		T56	8
auto[TlIntgErrBoth]	94	1			T54	9		T55	5		T56	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78853606

1

T1

360448

T2

248

T3

43628

auto[1]

85353446

1

T1

360448

T2

235

T3

61826

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7860449	1			T2	33		T3	3940		T4	1003
auto[TlIntgErrNone]	partial	auto[1]	8243717	1			T2	24		T3	5690		T4	3633
auto[TlIntgErrNone]	full_word	auto[0]	70993044	1			T1	360448		T2	215		T3	39688
auto[TlIntgErrNone]	full_word	auto[1]	77109552	1			T1	360448		T2	211		T3	56136
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T54	2		T55	2		T56	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T54	3		T56	3		T109	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T54	1		T56	1		T111	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T54	2		T109	1		T118	1
auto[TlIntgErrData]	partial	auto[0]	34	1			T56	2		T109	1		T119	2
auto[TlIntgErrData]	partial	auto[1]	57	1			T54	3		T55	3		T56	5
auto[TlIntgErrData]	full_word	auto[0]	3	1			T56	1		T116	1		T120	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T119	1		T118	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T54	4		T55	1		T56	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T54	5		T55	4		T56	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T114	1		T120	1		T121	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T111	1		T122	1		-	-