Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	842331	1			T3	15		T10	1899		T11	1436
auto[1]	10599861	1			T2	221		T3	249		T8	35027
auto[2]	658079	1			T3	12		T10	1487		T11	1273
auto[3]	10346137	1			T2	209		T3	159		T8	35059

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13687537	1			T2	345		T3	319		T8	58498
auto[1]	2161759	1			T2	33		T3	55		T8	5525
auto[2]	2204507	1			T2	48		T3	52		T8	5546
auto[3]	4392605	1			T2	4		T3	9		T8	517

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8636620

1

T2

430

T3

435

T8

70085

auto[1]

13809788

1

T8

1

T10

14928

T11

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	394008	1			T3	14		T11	1173		T21	2
auto[0]	auto[0]	auto[1]	41186	1			T11	128		T21	1		T22	3
auto[0]	auto[0]	auto[2]	41494	1			T3	1		T11	123		T22	2
auto[0]	auto[0]	auto[3]	69975	1			T11	12		T130	72		T129	1
auto[0]	auto[1]	auto[0]	3019038	1			T2	180		T3	185		T8	29239
auto[0]	auto[1]	auto[1]	324102	1			T2	10		T3	44		T8	2599
auto[0]	auto[1]	auto[2]	323027	1			T2	27		T3	15		T8	2927
auto[0]	auto[1]	auto[3]	281434	1			T2	4		T3	5		T8	261
auto[0]	auto[2]	auto[0]	287615	1			T11	1076		T37	388		T81	6
auto[0]	auto[2]	auto[1]	32815	1			T11	103		T37	26		T81	779
auto[0]	auto[2]	auto[2]	34140	1			T3	11		T11	85		T21	3
auto[0]	auto[2]	auto[3]	53677	1			T3	1		T11	8		T21	1
auto[0]	auto[3]	auto[0]	2851050	1			T2	165		T3	120		T8	29258
auto[0]	auto[3]	auto[1]	301145	1			T2	23		T3	11		T8	2926
auto[0]	auto[3]	auto[2]	327205	1			T2	21		T3	25		T8	2619
auto[0]	auto[3]	auto[3]	254709	1			T3	3		T8	256		T11	14
auto[1]	auto[0]	auto[0]	9895	1			T10	53		T57	545		T93	470
auto[1]	auto[0]	auto[1]	44088	1			T10	286		T57	2357		T93	2275
auto[1]	auto[0]	auto[2]	43752	1			T10	263		T57	2356		T93	2193
auto[1]	auto[0]	auto[3]	197933	1			T10	1297		T57	10558		T93	9888
auto[1]	auto[1]	auto[0]	3559951	1			T8	1		T10	123		T13	2928
auto[1]	auto[1]	auto[1]	701141	1			T10	991		T13	12338		T40	9320
auto[1]	auto[1]	auto[2]	699720	1			T10	544		T13	13145		T40	10352
auto[1]	auto[1]	auto[3]	1691448	1			T10	4270		T13	54221		T40	905
auto[1]	auto[2]	auto[0]	6676	1			T11	1		T57	464		T93	297
auto[1]	auto[2]	auto[1]	30572	1			T57	2195		T93	1258		T34	3021
auto[1]	auto[2]	auto[2]	38930	1			T10	266		T57	2018		T93	2133
auto[1]	auto[2]	auto[3]	173654	1			T10	1221		T57	8928		T93	9475
auto[1]	auto[3]	auto[0]	3559304	1			T10	60		T13	3010		T40	103555
auto[1]	auto[3]	auto[1]	686710	1			T10	225		T13	13328		T40	10282
auto[1]	auto[3]	auto[2]	696239	1			T10	956		T13	12007		T40	9193
auto[1]	auto[3]	auto[3]	1669775	1			T10	4373		T13	54608		T40	889