Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1161107690	259015	0	0
ctrl_regwen_rd_A	1161107690	4768	0	0
exec_rd_A	1161107690	4406	0	0
exec_regwen_rd_A	1161107690	5174	0	0
readback_rd_A	1161107690	3424	0	0
readback_regwen_rd_A	1161107690	2873	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161107690	259015	0	0
T4	130751	4454	0	0
T8	485795	0	0	0
T9	1036	0	0	0
T10	639059	0	0	0
T11	131150	0	0	0
T12	261622	0	0	0
T13	581888	0	0	0
T19	239368	0	0	0
T24	0	5279	0	0
T25	0	1078	0	0
T38	547693	0	0	0
T40	548134	0	0	0
T44	0	5930	0	0
T49	0	8471	0	0
T51	0	3249	0	0
T53	0	11305	0	0
T64	0	3771	0	0
T65	0	1262	0	0
T66	0	4224	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161107690	4768	0	0
T20	119671	0	0	0
T25	30613	83	0	0
T29	33798	0	0	0
T43	0	330	0	0
T44	89851	0	0	0
T51	0	165	0	0
T64	0	359	0	0
T65	0	125	0	0
T81	491740	0	0	0
T94	400028	0	0	0
T97	0	134	0	0
T98	0	511	0	0
T99	0	262	0	0
T100	0	670	0	0
T101	0	68	0	0
T102	149363	0	0	0
T103	73600	0	0	0
T104	1552	0	0	0
T105	788893	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161107690	4406	0	0
T20	119671	0	0	0
T25	30613	106	0	0
T29	33798	0	0	0
T43	0	371	0	0
T44	89851	0	0	0
T51	0	113	0	0
T64	0	318	0	0
T65	0	93	0	0
T81	491740	0	0	0
T94	400028	0	0	0
T97	0	97	0	0
T98	0	460	0	0
T99	0	215	0	0
T100	0	582	0	0
T101	0	127	0	0
T102	149363	0	0	0
T103	73600	0	0	0
T104	1552	0	0	0
T105	788893	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161107690	5174	0	0
T20	119671	0	0	0
T25	30613	130	0	0
T29	33798	0	0	0
T43	0	332	0	0
T44	89851	0	0	0
T51	0	150	0	0
T64	0	327	0	0
T65	0	63	0	0
T81	491740	0	0	0
T94	400028	0	0	0
T97	0	170	0	0
T98	0	540	0	0
T99	0	280	0	0
T100	0	716	0	0
T101	0	97	0	0
T102	149363	0	0	0
T103	73600	0	0	0
T104	1552	0	0	0
T105	788893	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161107690	3424	0	0
T20	119671	0	0	0
T25	30613	120	0	0
T29	33798	0	0	0
T43	0	278	0	0
T44	89851	0	0	0
T51	0	167	0	0
T64	0	255	0	0
T65	0	66	0	0
T81	491740	0	0	0
T94	400028	0	0	0
T97	0	145	0	0
T98	0	511	0	0
T99	0	276	0	0
T100	0	633	0	0
T101	0	56	0	0
T102	149363	0	0	0
T103	73600	0	0	0
T104	1552	0	0	0
T105	788893	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1161107690	2873	0	0
T20	119671	0	0	0
T25	30613	63	0	0
T29	33798	0	0	0
T43	0	298	0	0
T44	89851	0	0	0
T51	0	117	0	0
T64	0	241	0	0
T65	0	90	0	0
T81	491740	0	0	0
T94	400028	0	0	0
T97	0	135	0	0
T98	0	446	0	0
T99	0	188	0	0
T100	0	509	0	0
T101	0	68	0	0
T102	149363	0	0	0
T103	73600	0	0	0
T104	1552	0	0	0
T105	788893	0	0	0