Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15997492	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

148679690

1

T1

18320

T2

1029

T3

2856

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	80979372	1			T1	50877		T2	2881		T3	781
values[0x0]	40264175	1			T1	16644		T2	960		T3	1044
values[0x1]	43433635	1			T1	33683		T2	1935		T3	1034

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8133252	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

156543930

1

T1

60103

T2

3428

T3

2858

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	564338	1			T1	372		T2	26		T3	5
valid_sources[0x01]	604859	1			T1	358		T2	22		T3	11
valid_sources[0x02]	541311	1			T1	417		T2	13		T3	16
valid_sources[0x03]	565234	1			T1	398		T2	12		T3	9
valid_sources[0x04]	548729	1			T1	353		T2	15		T3	5
valid_sources[0x05]	577260	1			T1	406		T2	18		T3	21
valid_sources[0x06]	549883	1			T1	391		T2	30		T3	7
valid_sources[0x07]	544752	1			T1	401		T2	21		T3	13
valid_sources[0x08]	590783	1			T1	376		T2	21		T3	17
valid_sources[0x09]	570171	1			T1	370		T2	28		T3	7
valid_sources[0x0a]	532132	1			T1	408		T2	18		T3	14
valid_sources[0x0b]	530003	1			T1	427		T2	22		T3	11
valid_sources[0x0c]	555816	1			T1	360		T2	19		T3	2
valid_sources[0x0d]	654018	1			T1	430		T2	20		T3	6
valid_sources[0x0e]	550917	1			T1	384		T2	17		T3	13
valid_sources[0x0f]	553157	1			T1	433		T2	30		T3	15
valid_sources[0x10]	543600	1			T1	393		T2	26		T3	8
valid_sources[0x11]	535279	1			T1	424		T2	26		T3	8
valid_sources[0x12]	533462	1			T1	367		T2	16		T3	9
valid_sources[0x13]	555833	1			T1	403		T2	21		T3	8
valid_sources[0x14]	531893	1			T1	419		T2	24		T3	11
valid_sources[0x15]	543776	1			T1	393		T2	30		T3	7
valid_sources[0x16]	549257	1			T1	372		T2	21		T3	7
valid_sources[0x17]	537691	1			T1	384		T2	22		T3	14
valid_sources[0x18]	558217	1			T1	404		T2	22		T3	8
valid_sources[0x19]	572739	1			T1	400		T2	21		T3	10
valid_sources[0x1a]	545715	1			T1	393		T2	26		T3	12
valid_sources[0x1b]	526116	1			T1	409		T2	12		T3	5
valid_sources[0x1c]	595753	1			T1	399		T2	26		T3	11
valid_sources[0x1d]	562649	1			T1	369		T2	27		T3	8
valid_sources[0x1e]	522620	1			T1	386		T2	23		T3	5
valid_sources[0x1f]	531129	1			T1	361		T2	14		T3	15
valid_sources[0x20]	549536	1			T1	381		T2	14		T3	11
valid_sources[0x21]	666359	1			T1	370		T2	23		T3	11
valid_sources[0x22]	539512	1			T1	367		T2	22		T3	9
valid_sources[0x23]	540210	1			T1	409		T2	29		T3	7
valid_sources[0x24]	593951	1			T1	396		T2	14		T3	9
valid_sources[0x25]	521295	1			T1	402		T2	27		T3	8
valid_sources[0x26]	1394162	1			T1	396		T2	26		T3	11
valid_sources[0x27]	531640	1			T1	373		T2	32		T3	7
valid_sources[0x28]	540182	1			T1	398		T2	27		T3	13
valid_sources[0x29]	558390	1			T1	412		T2	19		T3	12
valid_sources[0x2a]	523994	1			T1	393		T2	24		T3	12
valid_sources[0x2b]	546278	1			T1	400		T2	21		T3	12
valid_sources[0x2c]	535079	1			T1	409		T2	30		T3	11
valid_sources[0x2d]	542301	1			T1	352		T2	26		T3	7
valid_sources[0x2e]	1627374	1			T1	365		T2	23		T3	15
valid_sources[0x2f]	2426758	1			T1	378		T2	24		T3	12
valid_sources[0x30]	1217238	1			T1	387		T2	23		T3	14
valid_sources[0x31]	579318	1			T1	394		T2	18		T3	11
valid_sources[0x32]	529869	1			T1	373		T2	21		T3	9
valid_sources[0x33]	533668	1			T1	410		T2	23		T3	10
valid_sources[0x34]	544961	1			T1	402		T2	14		T3	16
valid_sources[0x35]	544425	1			T1	422		T2	26		T3	12
valid_sources[0x36]	611014	1			T1	429		T2	24		T3	11
valid_sources[0x37]	538447	1			T1	437		T2	30		T3	8
valid_sources[0x38]	580804	1			T1	414		T2	24		T3	12
valid_sources[0x39]	563602	1			T1	422		T2	20		T3	7
valid_sources[0x3a]	545000	1			T1	379		T2	30		T3	23
valid_sources[0x3b]	553290	1			T1	383		T2	22		T3	15
valid_sources[0x3c]	526440	1			T1	382		T2	29		T3	16
valid_sources[0x3d]	584441	1			T1	395		T2	24		T3	15
valid_sources[0x3e]	940505	1			T1	373		T2	25		T3	6
valid_sources[0x3f]	557870	1			T1	378		T2	22		T3	13
valid_sources[0x40]	533491	1			T1	398		T2	23		T3	19
valid_sources[0x41]	553146	1			T1	408		T2	23		T3	10
valid_sources[0x42]	583521	1			T1	407		T2	19		T3	7
valid_sources[0x43]	2099731	1			T1	371		T2	14		T3	13
valid_sources[0x44]	543318	1			T1	362		T2	15		T3	11
valid_sources[0x45]	604087	1			T1	398		T2	23		T3	12
valid_sources[0x46]	542754	1			T1	404		T2	21		T3	7
valid_sources[0x47]	559979	1			T1	406		T2	26		T3	20
valid_sources[0x48]	577766	1			T1	414		T2	23		T3	7
valid_sources[0x49]	644295	1			T1	400		T2	21		T3	12
valid_sources[0x4a]	532996	1			T1	407		T2	19		T3	11
valid_sources[0x4b]	586900	1			T1	370		T2	19		T3	10
valid_sources[0x4c]	537896	1			T1	369		T2	28		T3	9
valid_sources[0x4d]	587989	1			T1	413		T2	23		T3	9
valid_sources[0x4e]	544415	1			T1	415		T2	18		T3	14
valid_sources[0x4f]	561073	1			T1	383		T2	31		T3	7
valid_sources[0x50]	529096	1			T1	378		T2	16		T3	9
valid_sources[0x51]	527035	1			T1	381		T2	29		T3	15
valid_sources[0x52]	602749	1			T1	404		T2	34		T3	17
valid_sources[0x53]	760562	1			T1	390		T2	25		T3	11
valid_sources[0x54]	563821	1			T1	412		T2	25		T3	12
valid_sources[0x55]	528387	1			T1	391		T2	20		T3	13
valid_sources[0x56]	536178	1			T1	407		T2	31		T3	7
valid_sources[0x57]	536672	1			T1	394		T2	18		T3	10
valid_sources[0x58]	549277	1			T1	385		T2	28		T3	12
valid_sources[0x59]	531300	1			T1	352		T2	24		T3	19
valid_sources[0x5a]	589773	1			T1	428		T2	19		T3	6
valid_sources[0x5b]	567777	1			T1	351		T2	29		T3	16
valid_sources[0x5c]	596516	1			T1	428		T2	32		T3	17
valid_sources[0x5d]	550794	1			T1	380		T2	29		T3	11
valid_sources[0x5e]	564969	1			T1	385		T2	16		T3	15
valid_sources[0x5f]	527780	1			T1	412		T2	24		T3	12
valid_sources[0x60]	586943	1			T1	354		T2	18		T3	14
valid_sources[0x61]	540140	1			T1	375		T2	21		T3	8
valid_sources[0x62]	734546	1			T1	386		T2	17		T3	4
valid_sources[0x63]	552662	1			T1	367		T2	21		T3	10
valid_sources[0x64]	668427	1			T1	419		T2	13		T3	14
valid_sources[0x65]	558206	1			T1	407		T2	24		T3	7
valid_sources[0x66]	539518	1			T1	383		T2	24		T3	12
valid_sources[0x67]	521828	1			T1	472		T2	21		T3	9
valid_sources[0x68]	558686	1			T1	359		T2	15		T3	10
valid_sources[0x69]	606167	1			T1	399		T2	26		T3	9
valid_sources[0x6a]	565399	1			T1	347		T2	21		T3	11
valid_sources[0x6b]	534784	1			T1	404		T2	18		T3	10
valid_sources[0x6c]	586705	1			T1	402		T2	22		T3	8
valid_sources[0x6d]	528530	1			T1	382		T2	23		T3	8
valid_sources[0x6e]	630799	1			T1	409		T2	33		T3	19
valid_sources[0x6f]	543853	1			T1	398		T2	21		T3	2
valid_sources[0x70]	542839	1			T1	378		T2	17		T3	10
valid_sources[0x71]	524643	1			T1	397		T2	21		T3	12
valid_sources[0x72]	540162	1			T1	402		T2	26		T3	7
valid_sources[0x73]	570054	1			T1	390		T2	18		T3	10
valid_sources[0x74]	533993	1			T1	398		T2	18		T3	8
valid_sources[0x75]	2138598	1			T1	381		T2	18		T3	6
valid_sources[0x76]	554829	1			T1	375		T2	20		T3	13
valid_sources[0x77]	568266	1			T1	381		T2	23		T3	10
valid_sources[0x78]	538034	1			T1	405		T2	17		T3	19
valid_sources[0x79]	547325	1			T1	399		T2	15		T3	11
valid_sources[0x7a]	557571	1			T1	389		T2	22		T3	11
valid_sources[0x7b]	677644	1			T1	429		T2	22		T3	10
valid_sources[0x7c]	536833	1			T1	369		T2	25		T3	13
valid_sources[0x7d]	545462	1			T1	403		T2	21		T3	10
valid_sources[0x7e]	538273	1			T1	398		T2	22		T3	15
valid_sources[0x7f]	578239	1			T1	410		T2	26		T3	16
valid_sources[0x80]	543022	1			T1	418		T2	17		T3	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72935885

1

T1

9306

T2

518

T3

781

values[0x0]

all_enables

biggest_size

37878830

1

T1

4533

T2

259

T3

1043

values[0x1]

all_enables

biggest_size

37864975

1

T1

4481

T2

252

T3

1032

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43986	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

168341

1

T3

1241

T4

3

T9

39

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	58020	1			T3	353		T5	86		T11	2
values[0x0]	74328	1			T1	1		T3	440		T4	10
values[0x1]	79979	1			T1	1		T2	1		T3	531

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33755	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

178572

1

T1

1

T2

1

T3

1279

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1103	1			T5	1		T23	25		T7	1
valid_sources[0x01]	938	1			T10	2		T5	1		T11	9
valid_sources[0x02]	671	1			T23	17		T71	10		T48	12
valid_sources[0x03]	722	1			T10	2		T5	1		T23	27
valid_sources[0x04]	914	1			T25	2		T23	26		T24	9
valid_sources[0x05]	749	1			T5	2		T25	3		T23	25
valid_sources[0x06]	814	1			T23	19		T24	5		T41	1
valid_sources[0x07]	908	1			T5	4		T23	23		T24	6
valid_sources[0x08]	900	1			T1	1		T5	5		T23	26
valid_sources[0x09]	843	1			T10	12		T6	1		T23	20
valid_sources[0x0a]	748	1			T10	1		T5	2		T6	1
valid_sources[0x0b]	1501	1			T3	1		T4	1		T5	1
valid_sources[0x0c]	850	1			T10	5		T23	20		T26	1
valid_sources[0x0d]	903	1			T23	21		T7	1		T24	5
valid_sources[0x0e]	674	1			T5	1		T23	26		T7	1
valid_sources[0x0f]	1142	1			T5	2		T6	1		T23	24
valid_sources[0x10]	1111	1			T5	3		T23	16		T7	3
valid_sources[0x11]	975	1			T5	1		T23	25		T58	1
valid_sources[0x12]	665	1			T23	26		T24	13		T134	1
valid_sources[0x13]	772	1			T10	2		T23	18		T7	2
valid_sources[0x14]	876	1			T5	3		T23	25		T24	7
valid_sources[0x15]	846	1			T3	3		T5	2		T23	13
valid_sources[0x16]	609	1			T5	1		T23	17		T7	1
valid_sources[0x17]	665	1			T6	1		T23	21		T24	15
valid_sources[0x18]	644	1			T23	22		T24	7		T21	1
valid_sources[0x19]	750	1			T5	2		T23	20		T24	7
valid_sources[0x1a]	667	1			T5	1		T23	22		T7	2
valid_sources[0x1b]	1012	1			T5	2		T23	21		T26	1
valid_sources[0x1c]	839	1			T5	1		T12	1		T81	6
valid_sources[0x1d]	853	1			T5	2		T23	30		T7	1
valid_sources[0x1e]	931	1			T25	1		T23	18		T24	18
valid_sources[0x1f]	789	1			T3	2		T5	2		T23	20
valid_sources[0x20]	663	1			T6	1		T23	18		T7	1
valid_sources[0x21]	1045	1			T5	1		T6	1		T23	11
valid_sources[0x22]	1233	1			T2	1		T3	1		T5	2
valid_sources[0x23]	971	1			T5	3		T12	2		T23	20
valid_sources[0x24]	774	1			T10	2		T23	21		T24	18
valid_sources[0x25]	880	1			T5	3		T23	23		T7	1
valid_sources[0x26]	1004	1			T5	1		T53	1		T23	20
valid_sources[0x27]	877	1			T5	6		T23	19		T7	1
valid_sources[0x28]	675	1			T5	1		T23	14		T24	6
valid_sources[0x29]	707	1			T23	14		T7	1		T24	6
valid_sources[0x2a]	777	1			T3	1		T4	1		T10	3
valid_sources[0x2b]	681	1			T5	1		T23	22		T7	1
valid_sources[0x2c]	758	1			T40	26		T23	16		T24	11
valid_sources[0x2d]	706	1			T5	2		T23	14		T7	1
valid_sources[0x2e]	697	1			T5	1		T23	23		T7	1
valid_sources[0x2f]	847	1			T23	15		T24	11		T37	16
valid_sources[0x30]	672	1			T4	1		T5	1		T23	30
valid_sources[0x31]	611	1			T6	1		T23	26		T7	2
valid_sources[0x32]	620	1			T10	2		T5	1		T23	27
valid_sources[0x33]	808	1			T5	1		T25	1		T53	1
valid_sources[0x34]	747	1			T23	17		T24	5		T41	1
valid_sources[0x35]	644	1			T23	25		T24	2		T48	8
valid_sources[0x36]	1261	1			T3	18		T50	6		T23	11
valid_sources[0x37]	560	1			T5	2		T23	24		T24	6
valid_sources[0x38]	850	1			T5	3		T23	23		T24	9
valid_sources[0x39]	924	1			T10	3		T23	25		T24	8
valid_sources[0x3a]	950	1			T3	2		T8	3		T10	4
valid_sources[0x3b]	872	1			T3	33		T10	2		T5	2
valid_sources[0x3c]	631	1			T3	6		T25	2		T39	2
valid_sources[0x3d]	787	1			T5	1		T6	1		T23	24
valid_sources[0x3e]	1122	1			T3	71		T5	2		T25	1
valid_sources[0x3f]	582	1			T23	24		T7	1		T24	6
valid_sources[0x40]	841	1			T5	3		T25	1		T23	27
valid_sources[0x41]	829	1			T5	1		T25	1		T23	19
valid_sources[0x42]	1031	1			T3	3		T5	3		T23	16
valid_sources[0x43]	790	1			T23	23		T24	14		T48	15
valid_sources[0x44]	1282	1			T5	1		T12	1		T25	1
valid_sources[0x45]	864	1			T5	2		T6	1		T23	14
valid_sources[0x46]	866	1			T5	1		T6	2		T23	23
valid_sources[0x47]	1156	1			T5	1		T23	24		T24	1
valid_sources[0x48]	798	1			T6	1		T23	19		T7	3
valid_sources[0x49]	686	1			T6	1		T23	22		T24	18
valid_sources[0x4a]	616	1			T23	23		T24	20		T20	13
valid_sources[0x4b]	869	1			T10	1		T12	1		T23	15
valid_sources[0x4c]	654	1			T4	1		T23	14		T24	8
valid_sources[0x4d]	685	1			T23	23		T7	1		T24	6
valid_sources[0x4e]	605	1			T5	1		T25	1		T23	18
valid_sources[0x4f]	856	1			T10	2		T6	2		T23	15
valid_sources[0x50]	625	1			T10	3		T5	1		T23	22
valid_sources[0x51]	904	1			T12	1		T6	1		T23	16
valid_sources[0x52]	1070	1			T23	20		T7	1		T24	8
valid_sources[0x53]	682	1			T53	1		T23	25		T7	3
valid_sources[0x54]	789	1			T3	1		T5	2		T25	1
valid_sources[0x55]	606	1			T23	28		T7	1		T24	11
valid_sources[0x56]	593	1			T10	2		T23	17		T24	10
valid_sources[0x57]	610	1			T23	23		T24	7		T38	3
valid_sources[0x58]	875	1			T10	4		T5	4		T53	1
valid_sources[0x59]	660	1			T3	2		T6	1		T23	21
valid_sources[0x5a]	1003	1			T1	1		T23	21		T7	2
valid_sources[0x5b]	824	1			T10	4		T23	25		T7	1
valid_sources[0x5c]	703	1			T6	1		T23	19		T7	2
valid_sources[0x5d]	858	1			T3	118		T23	22		T26	1
valid_sources[0x5e]	853	1			T23	18		T7	4		T24	15
valid_sources[0x5f]	742	1			T10	5		T23	26		T24	12
valid_sources[0x60]	1000	1			T23	26		T7	2		T24	13
valid_sources[0x61]	693	1			T23	19		T26	2		T7	1
valid_sources[0x62]	735	1			T3	1		T10	4		T5	1
valid_sources[0x63]	637	1			T5	2		T6	1		T23	18
valid_sources[0x64]	764	1			T5	2		T23	22		T7	2
valid_sources[0x65]	796	1			T3	4		T23	23		T7	2
valid_sources[0x66]	613	1			T53	1		T23	21		T24	6
valid_sources[0x67]	830	1			T5	1		T53	1		T23	23
valid_sources[0x68]	641	1			T5	2		T23	26		T7	2
valid_sources[0x69]	1274	1			T5	2		T23	24		T7	1
valid_sources[0x6a]	982	1			T5	1		T23	20		T7	3
valid_sources[0x6b]	873	1			T3	3		T10	11		T5	1
valid_sources[0x6c]	730	1			T10	1		T5	2		T23	27
valid_sources[0x6d]	848	1			T6	1		T23	20		T26	1
valid_sources[0x6e]	660	1			T3	3		T6	1		T23	18
valid_sources[0x6f]	1105	1			T5	1		T23	25		T24	19
valid_sources[0x70]	696	1			T5	1		T53	1		T23	25
valid_sources[0x71]	600	1			T23	20		T7	1		T24	4
valid_sources[0x72]	815	1			T3	20		T5	1		T23	21
valid_sources[0x73]	856	1			T23	24		T7	1		T24	13
valid_sources[0x74]	924	1			T25	1		T23	29		T24	6
valid_sources[0x75]	878	1			T5	2		T23	26		T7	1
valid_sources[0x76]	614	1			T23	24		T24	3		T35	1
valid_sources[0x77]	637	1			T6	1		T23	26		T24	3
valid_sources[0x78]	1003	1			T23	22		T7	2		T24	14
valid_sources[0x79]	1137	1			T23	25		T7	1		T24	7
valid_sources[0x7a]	653	1			T5	5		T23	25		T24	15
valid_sources[0x7b]	849	1			T23	16		T24	9		T48	10
valid_sources[0x7c]	695	1			T23	32		T24	8		T13	1
valid_sources[0x7d]	664	1			T5	1		T25	1		T23	21
valid_sources[0x7e]	678	1			T3	1		T10	1		T5	4
valid_sources[0x7f]	1180	1			T5	1		T6	1		T23	18
valid_sources[0x80]	1022	1			T5	1		T6	2		T23	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45115

1

T3

329

T5

43

T11

1

values[0x0]

all_enables

biggest_size

62856

1

T3

435

T4

3

T9

26

values[0x1]

all_enables

biggest_size

60370

1

T3

477

T9

13

T10

13