Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15957639

1

T1

82884

T2

4747

T3

2452

full_word

145871059

1

T1

18320

T2

1029

T3

3108

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	161828418	1			T1	101204		T2	5776		T3	5560
auto[TlIntgErrCmd]	98	1			T62	5		T63	5		T64	6
auto[TlIntgErrData]	90	1			T62	1		T63	2		T64	2
auto[TlIntgErrBoth]	92	1			T62	4		T63	3		T64	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78028500

1

T1

50877

T2

2881

T3

1337

auto[1]

83800198

1

T1

50327

T2

2895

T3

4223

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7819618	1			T1	41571		T2	2363		T3	512
auto[TlIntgErrNone]	partial	auto[1]	8137771	1			T1	41313		T2	2384		T3	1940
auto[TlIntgErrNone]	full_word	auto[0]	70208759	1			T1	9306		T2	518		T3	825
auto[TlIntgErrNone]	full_word	auto[1]	75662270	1			T1	9014		T2	511		T3	2283
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T62	2		T64	3		T120	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T62	2		T63	4		T64	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T64	1		T114	1		T124	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T62	1		T63	1		T125	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T64	2		T116	3		T120	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T62	1		T116	1		T120	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T63	2		T125	1		T124	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T116	1		T125	1		T121	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T62	1		T63	1		T64	5
auto[TlIntgErrBoth]	partial	auto[1]	44	1			T62	2		T63	2		T64	7
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T62	1		T123	1		T119	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T120	1		T125	1		T119	1