Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	832538	1			T1	2172		T4	181		T5	9111
auto[1]	10714644	1			T1	6763		T4	1750		T8	14998
auto[2]	639672	1			T1	1529		T4	126		T5	5366
auto[3]	10463731	1			T1	5983		T4	1610		T8	15402

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14592595	1			T1	275		T4	2576		T8	146
auto[1]	2091064	1			T1	1720		T4	400		T8	1420
auto[2]	2126710	1			T1	2145		T4	621		T8	2570
auto[3]	3840216	1			T1	12307		T4	70		T8	26264

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8907671

1

T4

3666

T8

30398

T5

23067

auto[1]

13742914

1

T1

16447

T4

1

T8

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	238290	1			T4	150		T5	7526		T39	10
auto[0]	auto[0]	auto[1]	25425	1			T4	15		T5	761		T39	40
auto[0]	auto[0]	auto[2]	25554	1			T4	15		T5	749		T39	32
auto[0]	auto[0]	auto[3]	73674	1			T4	1		T5	75		T39	174
auto[0]	auto[1]	auto[0]	3280475	1			T4	1318		T8	13		T5	4504
auto[0]	auto[1]	auto[1]	337762	1			T4	282		T8	107		T5	794
auto[0]	auto[1]	auto[2]	346661	1			T4	121		T8	1322		T5	448
auto[0]	auto[1]	auto[3]	267423	1			T4	28		T8	13556		T5	65
auto[0]	auto[2]	auto[0]	160110	1			T5	4199		T39	6		T7	2246
auto[0]	auto[2]	auto[1]	21399	1			T5	407		T39	38		T7	205
auto[0]	auto[2]	auto[2]	22307	1			T4	113		T5	696		T39	31
auto[0]	auto[2]	auto[3]	51607	1			T4	13		T5	64		T39	141
auto[0]	auto[3]	auto[0]	3147485	1			T4	1107		T8	133		T5	1742
auto[0]	auto[3]	auto[1]	330174	1			T4	103		T8	1313		T5	177
auto[0]	auto[3]	auto[2]	343364	1			T4	372		T8	1248		T5	791
auto[0]	auto[3]	auto[3]	235961	1			T4	28		T8	12706		T5	69
auto[1]	auto[0]	auto[0]	15584	1			T1	80		T33	828		T35	726
auto[1]	auto[0]	auto[1]	69732	1			T1	314		T33	3742		T35	3064
auto[1]	auto[0]	auto[2]	69952	1			T1	325		T33	3804		T35	3119
auto[1]	auto[0]	auto[3]	314327	1			T1	1453		T33	16911		T35	14112
auto[1]	auto[1]	auto[0]	3870294	1			T1	129		T4	1		T12	1
auto[1]	auto[1]	auto[1]	651452	1			T1	1134		T50	10415		T81	7934
auto[1]	auto[1]	auto[2]	618726	1			T1	533		T50	10051		T81	8708
auto[1]	auto[1]	auto[3]	1341851	1			T1	4967		T50	1002		T81	802
auto[1]	auto[2]	auto[0]	11442	1			T33	755		T35	676		T133	742
auto[1]	auto[2]	auto[1]	51881	1			T33	3431		T35	2900		T133	3422
auto[1]	auto[2]	auto[2]	57933	1			T1	266		T33	3184		T35	1998
auto[1]	auto[2]	auto[3]	262993	1			T1	1263		T33	14349		T35	9521
auto[1]	auto[3]	auto[0]	3868915	1			T1	66		T12	1		T50	101611
auto[1]	auto[3]	auto[1]	603239	1			T1	272		T50	10334		T81	8744
auto[1]	auto[3]	auto[2]	642213	1			T1	1021		T50	10335		T81	7925
auto[1]	auto[3]	auto[3]	1292380	1			T1	4624		T8	2		T50	1044