Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1083729070	251166	0	0
ctrl_regwen_rd_A	1083729070	4915	0	0
exec_rd_A	1083729070	4572	0	0
exec_regwen_rd_A	1083729070	5139	0	0
readback_rd_A	1083729070	3176	0	0
readback_regwen_rd_A	1083729070	2739	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083729070	251166	0	0
T3	62125	1634	0	0
T4	133686	0	0	0
T5	600935	0	0	0
T8	95874	0	0	0
T9	691754	0	0	0
T10	525494	0	0	0
T11	87934	0	0	0
T12	491494	0	0	0
T23	0	8211	0	0
T24	0	3817	0	0
T25	704840	0	0	0
T44	73297	0	0	0
T48	0	5082	0	0
T54	0	9370	0	0
T55	0	7622	0	0
T56	0	7516	0	0
T68	0	1708	0	0
T69	0	793	0	0
T70	0	4602	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083729070	4915	0	0
T3	62125	63	0	0
T4	133686	0	0	0
T5	600935	0	0	0
T8	95874	0	0	0
T9	691754	0	0	0
T10	525494	0	0	0
T11	87934	0	0	0
T12	491494	0	0	0
T24	0	250	0	0
T25	704840	0	0	0
T44	73297	0	0	0
T46	0	234	0	0
T57	0	338	0	0
T69	0	103	0	0
T108	0	471	0	0
T109	0	95	0	0
T110	0	32	0	0
T111	0	193	0	0
T112	0	493	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083729070	4572	0	0
T3	62125	84	0	0
T4	133686	0	0	0
T5	600935	0	0	0
T8	95874	0	0	0
T9	691754	0	0	0
T10	525494	0	0	0
T11	87934	0	0	0
T12	491494	0	0	0
T24	0	218	0	0
T25	704840	0	0	0
T44	73297	0	0	0
T46	0	208	0	0
T57	0	209	0	0
T69	0	82	0	0
T108	0	438	0	0
T109	0	129	0	0
T110	0	78	0	0
T111	0	167	0	0
T112	0	366	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083729070	5139	0	0
T3	62125	107	0	0
T4	133686	0	0	0
T5	600935	0	0	0
T8	95874	0	0	0
T9	691754	0	0	0
T10	525494	0	0	0
T11	87934	0	0	0
T12	491494	0	0	0
T24	0	274	0	0
T25	704840	0	0	0
T44	73297	0	0	0
T46	0	305	0	0
T57	0	341	0	0
T69	0	66	0	0
T108	0	595	0	0
T109	0	98	0	0
T110	0	43	0	0
T111	0	126	0	0
T112	0	450	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083729070	3176	0	0
T3	62125	70	0	0
T4	133686	0	0	0
T5	600935	0	0	0
T8	95874	0	0	0
T9	691754	0	0	0
T10	525494	0	0	0
T11	87934	0	0	0
T12	491494	0	0	0
T24	0	178	0	0
T25	704840	0	0	0
T44	73297	0	0	0
T46	0	239	0	0
T57	0	348	0	0
T69	0	103	0	0
T108	0	535	0	0
T109	0	148	0	0
T110	0	37	0	0
T111	0	122	0	0
T112	0	554	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1083729070	2739	0	0
T3	62125	56	0	0
T4	133686	0	0	0
T5	600935	0	0	0
T8	95874	0	0	0
T9	691754	0	0	0
T10	525494	0	0	0
T11	87934	0	0	0
T12	491494	0	0	0
T24	0	212	0	0
T25	704840	0	0	0
T44	73297	0	0	0
T46	0	240	0	0
T57	0	288	0	0
T69	0	43	0	0
T108	0	497	0	0
T109	0	124	0	0
T110	0	42	0	0
T111	0	119	0	0
T112	0	400	0	0