Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16219311	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

167932530

1

T2

129651

T3

125312

T4

34434

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	90719995	1			T2	71475		T3	68894		T4	18921
values[0x0]	45098134	1			T2	34519		T3	33384		T4	9033
values[0x1]	48333712	1			T2	36680		T3	35436		T4	9905

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8249385	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

175902456

1

T2

136250

T3

131583

T4

36100

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	674789	1			T2	1		T3	478		T4	145
valid_sources[0x01]	613157	1			T2	461		T3	610		T4	157
valid_sources[0x02]	605672	1			T3	603		T4	143		T5	512
valid_sources[0x03]	837601	1			T2	844		T3	544		T4	148
valid_sources[0x04]	646897	1			T2	284		T3	531		T4	122
valid_sources[0x05]	665480	1			T2	434		T3	427		T4	125
valid_sources[0x06]	611744	1			T2	57		T3	630		T4	150
valid_sources[0x07]	795723	1			T2	476		T3	536		T4	156
valid_sources[0x08]	1596789	1			T2	53		T3	369		T4	148
valid_sources[0x09]	618131	1			T2	335		T3	791		T4	157
valid_sources[0x0a]	602244	1			T3	615		T4	162		T5	368
valid_sources[0x0b]	608882	1			T2	555		T3	490		T4	168
valid_sources[0x0c]	612868	1			T2	1		T3	462		T4	140
valid_sources[0x0d]	611153	1			T3	531		T4	174		T5	482
valid_sources[0x0e]	631732	1			T2	16918		T3	438		T4	143
valid_sources[0x0f]	599074	1			T2	488		T3	485		T4	159
valid_sources[0x10]	628668	1			T2	116		T3	547		T4	166
valid_sources[0x11]	603577	1			T2	152		T3	588		T4	136
valid_sources[0x12]	598396	1			T2	139		T3	714		T4	126
valid_sources[0x13]	599186	1			T2	393		T3	467		T4	149
valid_sources[0x14]	706548	1			T2	95		T3	535		T4	181
valid_sources[0x15]	619689	1			T2	115		T3	460		T4	152
valid_sources[0x16]	627934	1			T2	280		T3	557		T4	187
valid_sources[0x17]	601032	1			T2	222		T3	574		T4	135
valid_sources[0x18]	805592	1			T2	175		T3	533		T4	197
valid_sources[0x19]	620155	1			T2	13		T3	622		T4	163
valid_sources[0x1a]	595651	1			T3	520		T4	145		T5	459
valid_sources[0x1b]	598742	1			T3	698		T4	134		T5	413
valid_sources[0x1c]	614360	1			T3	692		T4	150		T5	535
valid_sources[0x1d]	630123	1			T2	122		T3	545		T4	164
valid_sources[0x1e]	650182	1			T2	259		T3	580		T4	151
valid_sources[0x1f]	614390	1			T2	265		T3	498		T4	82
valid_sources[0x20]	721423	1			T2	62		T3	704		T4	136
valid_sources[0x21]	609406	1			T2	258		T3	437		T4	147
valid_sources[0x22]	615364	1			T2	313		T3	460		T4	121
valid_sources[0x23]	605856	1			T3	440		T4	141		T5	512
valid_sources[0x24]	647978	1			T3	657		T4	168		T5	482
valid_sources[0x25]	629614	1			T3	456		T4	174		T5	548
valid_sources[0x26]	595121	1			T2	29		T3	463		T4	186
valid_sources[0x27]	635237	1			T2	479		T3	380		T4	136
valid_sources[0x28]	662829	1			T3	564		T4	125		T5	470
valid_sources[0x29]	606989	1			T2	185		T3	404		T4	140
valid_sources[0x2a]	840600	1			T2	163		T3	418		T4	156
valid_sources[0x2b]	596135	1			T2	34		T3	402		T4	123
valid_sources[0x2c]	625601	1			T2	43		T3	666		T4	153
valid_sources[0x2d]	606973	1			T2	167		T3	403		T4	154
valid_sources[0x2e]	612803	1			T3	458		T4	178		T5	494
valid_sources[0x2f]	2229706	1			T2	122		T3	503		T4	154
valid_sources[0x30]	640803	1			T2	239		T3	481		T4	114
valid_sources[0x31]	621158	1			T2	8		T3	436		T4	142
valid_sources[0x32]	633457	1			T2	315		T3	486		T4	118
valid_sources[0x33]	597062	1			T2	22		T3	481		T4	159
valid_sources[0x34]	1998968	1			T2	214		T3	415		T4	161
valid_sources[0x35]	644614	1			T2	47		T3	554		T4	184
valid_sources[0x36]	594444	1			T2	392		T3	429		T4	144
valid_sources[0x37]	624609	1			T2	147		T3	435		T4	136
valid_sources[0x38]	604764	1			T2	271		T3	667		T4	168
valid_sources[0x39]	614705	1			T2	677		T3	484		T4	153
valid_sources[0x3a]	643009	1			T2	45556		T3	512		T4	190
valid_sources[0x3b]	682061	1			T2	525		T3	472		T4	165
valid_sources[0x3c]	613406	1			T2	26		T3	573		T4	149
valid_sources[0x3d]	620508	1			T2	154		T3	483		T4	180
valid_sources[0x3e]	634118	1			T2	38		T3	523		T4	131
valid_sources[0x3f]	610840	1			T2	388		T3	609		T4	163
valid_sources[0x40]	640077	1			T2	12		T3	562		T4	127
valid_sources[0x41]	605098	1			T2	96		T3	638		T4	163
valid_sources[0x42]	602863	1			T2	90		T3	537		T4	125
valid_sources[0x43]	601399	1			T2	785		T3	665		T4	104
valid_sources[0x44]	634546	1			T2	47		T3	531		T4	144
valid_sources[0x45]	620790	1			T2	1		T3	613		T4	142
valid_sources[0x46]	595447	1			T2	207		T3	385		T4	152
valid_sources[0x47]	617091	1			T2	144		T3	603		T4	171
valid_sources[0x48]	647466	1			T2	603		T3	568		T4	147
valid_sources[0x49]	636414	1			T2	134		T3	498		T4	137
valid_sources[0x4a]	626095	1			T3	599		T4	138		T5	487
valid_sources[0x4b]	657827	1			T2	216		T3	556		T4	124
valid_sources[0x4c]	602642	1			T2	91		T3	430		T4	183
valid_sources[0x4d]	594499	1			T2	398		T3	574		T4	104
valid_sources[0x4e]	725904	1			T3	858		T4	141		T5	399
valid_sources[0x4f]	602501	1			T2	304		T3	638		T4	176
valid_sources[0x50]	614758	1			T3	534		T4	155		T5	572
valid_sources[0x51]	611777	1			T2	215		T3	425		T4	128
valid_sources[0x52]	604648	1			T2	666		T3	434		T4	143
valid_sources[0x53]	606235	1			T2	351		T3	621		T4	163
valid_sources[0x54]	608744	1			T2	453		T3	544		T4	177
valid_sources[0x55]	627021	1			T2	229		T3	567		T4	114
valid_sources[0x56]	631530	1			T2	413		T3	523		T4	144
valid_sources[0x57]	688319	1			T2	1314		T3	452		T4	164
valid_sources[0x58]	658760	1			T2	63		T3	551		T4	116
valid_sources[0x59]	619091	1			T2	830		T3	494		T4	143
valid_sources[0x5a]	609921	1			T3	505		T4	99		T5	502
valid_sources[0x5b]	644952	1			T3	602		T4	130		T5	491
valid_sources[0x5c]	691236	1			T2	17		T3	559		T4	133
valid_sources[0x5d]	812765	1			T3	557		T4	115		T5	465
valid_sources[0x5e]	626099	1			T2	557		T3	481		T4	182
valid_sources[0x5f]	1856171	1			T2	44		T3	582		T4	163
valid_sources[0x60]	613185	1			T2	99		T3	446		T4	143
valid_sources[0x61]	644340	1			T2	240		T3	587		T4	144
valid_sources[0x62]	600421	1			T2	194		T3	579		T4	126
valid_sources[0x63]	612801	1			T2	330		T3	438		T4	112
valid_sources[0x64]	689824	1			T2	306		T3	567		T4	143
valid_sources[0x65]	610602	1			T2	269		T3	542		T4	184
valid_sources[0x66]	649688	1			T2	525		T3	612		T4	165
valid_sources[0x67]	631210	1			T2	61		T3	611		T4	157
valid_sources[0x68]	618510	1			T3	536		T4	146		T5	432
valid_sources[0x69]	625562	1			T2	88		T3	533		T4	177
valid_sources[0x6a]	622697	1			T2	335		T3	661		T4	147
valid_sources[0x6b]	606233	1			T2	148		T3	551		T4	177
valid_sources[0x6c]	613107	1			T2	2		T3	741		T4	143
valid_sources[0x6d]	612197	1			T2	11		T3	595		T4	110
valid_sources[0x6e]	2070279	1			T2	1		T3	412		T4	141
valid_sources[0x6f]	636326	1			T2	454		T3	542		T4	170
valid_sources[0x70]	637367	1			T2	317		T3	549		T4	142
valid_sources[0x71]	644046	1			T2	7		T3	468		T4	176
valid_sources[0x72]	669548	1			T2	605		T3	440		T4	162
valid_sources[0x73]	639507	1			T2	159		T3	445		T4	146
valid_sources[0x74]	601038	1			T2	658		T3	429		T4	150
valid_sources[0x75]	604126	1			T2	581		T3	505		T4	160
valid_sources[0x76]	673679	1			T2	32		T3	505		T4	149
valid_sources[0x77]	637981	1			T3	384		T4	156		T5	395
valid_sources[0x78]	617237	1			T2	197		T3	548		T4	144
valid_sources[0x79]	601160	1			T2	115		T3	518		T4	170
valid_sources[0x7a]	616031	1			T2	50		T3	484		T4	161
valid_sources[0x7b]	668554	1			T3	435		T4	131		T5	470
valid_sources[0x7c]	654264	1			T2	343		T3	615		T4	160
valid_sources[0x7d]	609315	1			T2	327		T3	476		T4	115
valid_sources[0x7e]	805659	1			T3	548		T4	131		T5	473
valid_sources[0x7f]	686064	1			T2	357		T3	475		T4	166
valid_sources[0x80]	613457	1			T2	304		T3	671		T4	134

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

82567300

1

T2

64976

T3

62640

T4

17244

values[0x0]

all_enables

biggest_size

42677801

1

T2

32516

T3

31487

T4

8499

values[0x1]

all_enables

biggest_size

42687429

1

T2

32159

T3

31185

T4

8691

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43617	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

153264

1

T2

23

T4

2

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53733	1			T2	17		T11	10		T7	25
values[0x0]	69246	1			T1	5		T2	41		T3	1
values[0x1]	73902	1			T1	4		T2	29		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33697	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

163184

1

T1

1

T2

32

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	638	1			T27	1		T25	9		T26	1
valid_sources[0x01]	683	1			T27	2		T25	6		T26	4
valid_sources[0x02]	567	1			T25	14		T26	1		T28	2
valid_sources[0x03]	631	1			T27	1		T25	15		T26	4
valid_sources[0x04]	574	1			T27	2		T25	8		T26	7
valid_sources[0x05]	686	1			T27	1		T25	8		T26	1
valid_sources[0x06]	983	1			T27	2		T25	12		T28	2
valid_sources[0x07]	778	1			T4	1		T27	3		T25	6
valid_sources[0x08]	647	1			T29	1		T27	1		T25	10
valid_sources[0x09]	671	1			T25	10		T28	5		T57	27
valid_sources[0x0a]	998	1			T25	11		T26	10		T28	6
valid_sources[0x0b]	646	1			T25	13		T26	1		T28	1
valid_sources[0x0c]	899	1			T27	3		T25	18		T26	2
valid_sources[0x0d]	819	1			T27	2		T25	6		T26	1
valid_sources[0x0e]	660	1			T29	1		T25	11		T26	1
valid_sources[0x0f]	732	1			T29	1		T25	16		T26	2
valid_sources[0x10]	921	1			T27	3		T25	14		T26	5
valid_sources[0x11]	577	1			T27	1		T25	14		T28	3
valid_sources[0x12]	676	1			T25	12		T26	4		T28	5
valid_sources[0x13]	696	1			T7	4		T59	4		T25	13
valid_sources[0x14]	761	1			T4	1		T25	14		T26	3
valid_sources[0x15]	641	1			T27	1		T25	6		T26	5
valid_sources[0x16]	717	1			T25	23		T28	6		T55	1
valid_sources[0x17]	836	1			T27	2		T25	12		T26	3
valid_sources[0x18]	607	1			T27	1		T25	16		T26	1
valid_sources[0x19]	693	1			T27	1		T25	12		T26	3
valid_sources[0x1a]	883	1			T27	1		T25	14		T26	5
valid_sources[0x1b]	559	1			T25	23		T26	1		T28	4
valid_sources[0x1c]	837	1			T29	1		T27	3		T25	7
valid_sources[0x1d]	850	1			T29	1		T25	10		T28	3
valid_sources[0x1e]	766	1			T27	2		T25	9		T26	6
valid_sources[0x1f]	696	1			T25	13		T28	7		T47	1
valid_sources[0x20]	758	1			T25	31		T26	2		T28	4
valid_sources[0x21]	917	1			T27	1		T25	6		T26	2
valid_sources[0x22]	711	1			T27	6		T61	1		T25	11
valid_sources[0x23]	655	1			T25	19		T26	2		T28	2
valid_sources[0x24]	1072	1			T25	7		T26	4		T28	2
valid_sources[0x25]	675	1			T3	1		T25	15		T26	1
valid_sources[0x26]	619	1			T27	1		T25	13		T26	4
valid_sources[0x27]	847	1			T25	14		T26	2		T28	8
valid_sources[0x28]	716	1			T27	1		T25	11		T26	2
valid_sources[0x29]	869	1			T25	10		T26	1		T28	5
valid_sources[0x2a]	683	1			T29	1		T25	8		T26	6
valid_sources[0x2b]	591	1			T25	5		T26	2		T28	2
valid_sources[0x2c]	763	1			T27	3		T25	5		T26	4
valid_sources[0x2d]	597	1			T27	2		T25	7		T26	5
valid_sources[0x2e]	624	1			T27	1		T25	28		T26	3
valid_sources[0x2f]	745	1			T7	2		T25	12		T28	3
valid_sources[0x30]	972	1			T4	1		T27	1		T59	3
valid_sources[0x31]	599	1			T25	6		T26	2		T28	3
valid_sources[0x32]	651	1			T25	9		T28	1		T57	20
valid_sources[0x33]	673	1			T25	9		T26	7		T28	3
valid_sources[0x34]	840	1			T2	87		T27	1		T25	15
valid_sources[0x35]	628	1			T27	1		T25	6		T26	4
valid_sources[0x36]	628	1			T25	5		T26	5		T28	5
valid_sources[0x37]	676	1			T12	4		T25	11		T26	8
valid_sources[0x38]	732	1			T27	6		T25	1		T26	9
valid_sources[0x39]	737	1			T25	16		T26	6		T28	4
valid_sources[0x3a]	668	1			T25	16		T26	2		T28	3
valid_sources[0x3b]	851	1			T7	14		T25	16		T26	1
valid_sources[0x3c]	651	1			T25	23		T26	1		T28	8
valid_sources[0x3d]	664	1			T27	1		T25	11		T26	2
valid_sources[0x3e]	610	1			T27	1		T25	11		T26	11
valid_sources[0x3f]	621	1			T4	1		T27	2		T25	18
valid_sources[0x40]	672	1			T27	1		T25	17		T26	2
valid_sources[0x41]	977	1			T25	16		T26	7		T28	2
valid_sources[0x42]	588	1			T25	9		T26	4		T28	6
valid_sources[0x43]	797	1			T27	2		T25	33		T28	1
valid_sources[0x44]	702	1			T7	10		T27	1		T25	6
valid_sources[0x45]	681	1			T25	16		T26	20		T28	1
valid_sources[0x46]	741	1			T1	3		T25	5		T28	2
valid_sources[0x47]	688	1			T29	1		T25	4		T28	3
valid_sources[0x48]	801	1			T27	2		T25	18		T28	2
valid_sources[0x49]	866	1			T29	1		T25	7		T28	4
valid_sources[0x4a]	1373	1			T25	11		T26	3		T28	3
valid_sources[0x4b]	980	1			T25	13		T26	3		T28	6
valid_sources[0x4c]	674	1			T29	1		T25	12		T26	3
valid_sources[0x4d]	860	1			T27	1		T25	10		T26	12
valid_sources[0x4e]	917	1			T29	1		T25	20		T28	6
valid_sources[0x4f]	760	1			T29	1		T27	1		T25	19
valid_sources[0x50]	977	1			T25	13		T26	4		T28	3
valid_sources[0x51]	640	1			T25	4		T26	4		T28	3
valid_sources[0x52]	884	1			T29	1		T27	4		T25	10
valid_sources[0x53]	1219	1			T25	15		T28	6		T57	16
valid_sources[0x54]	619	1			T27	3		T25	14		T26	3
valid_sources[0x55]	619	1			T27	4		T25	9		T28	7
valid_sources[0x56]	994	1			T25	20		T26	13		T28	5
valid_sources[0x57]	1366	1			T27	1		T60	2		T25	14
valid_sources[0x58]	709	1			T27	1		T25	8		T26	3
valid_sources[0x59]	888	1			T27	1		T25	13		T26	5
valid_sources[0x5a]	726	1			T25	6		T26	16		T47	2
valid_sources[0x5b]	817	1			T25	12		T26	7		T28	11
valid_sources[0x5c]	780	1			T25	7		T26	3		T28	2
valid_sources[0x5d]	625	1			T27	1		T25	16		T26	1
valid_sources[0x5e]	780	1			T27	1		T25	20		T26	1
valid_sources[0x5f]	928	1			T25	20		T26	3		T28	4
valid_sources[0x60]	615	1			T12	2		T25	19		T26	15
valid_sources[0x61]	671	1			T27	8		T25	21		T26	2
valid_sources[0x62]	1010	1			T10	7		T29	1		T27	3
valid_sources[0x63]	650	1			T27	1		T25	2		T26	6
valid_sources[0x64]	915	1			T7	2		T27	4		T18	5
valid_sources[0x65]	607	1			T6	4		T25	9		T26	4
valid_sources[0x66]	565	1			T27	1		T25	12		T26	2
valid_sources[0x67]	934	1			T27	1		T25	14		T26	11
valid_sources[0x68]	869	1			T25	9		T26	4		T28	3
valid_sources[0x69]	720	1			T3	1		T27	2		T25	19
valid_sources[0x6a]	822	1			T7	4		T25	17		T26	2
valid_sources[0x6b]	912	1			T27	2		T25	10		T26	3
valid_sources[0x6c]	836	1			T18	8		T25	11		T26	3
valid_sources[0x6d]	667	1			T25	9		T26	2		T28	5
valid_sources[0x6e]	768	1			T27	4		T25	13		T26	2
valid_sources[0x6f]	596	1			T25	23		T26	3		T28	4
valid_sources[0x70]	924	1			T25	22		T26	4		T28	7
valid_sources[0x71]	746	1			T25	7		T26	10		T28	3
valid_sources[0x72]	907	1			T27	2		T25	15		T26	1
valid_sources[0x73]	834	1			T25	11		T26	4		T28	2
valid_sources[0x74]	652	1			T27	1		T25	13		T26	3
valid_sources[0x75]	999	1			T27	4		T25	14		T26	12
valid_sources[0x76]	762	1			T25	6		T26	5		T28	4
valid_sources[0x77]	632	1			T12	1		T27	2		T25	10
valid_sources[0x78]	764	1			T3	1		T27	2		T25	21
valid_sources[0x79]	674	1			T27	6		T25	17		T26	4
valid_sources[0x7a]	1171	1			T27	1		T25	2		T26	5
valid_sources[0x7b]	624	1			T5	1		T25	9		T26	6
valid_sources[0x7c]	609	1			T25	8		T26	1		T28	5
valid_sources[0x7d]	682	1			T25	3		T26	1		T28	2
valid_sources[0x7e]	1030	1			T27	1		T25	11		T28	8
valid_sources[0x7f]	765	1			T25	2		T26	5		T28	2
valid_sources[0x80]	737	1			T25	9		T26	7		T28	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41077

1

T2

9

T11

6

T7

13

values[0x0]

all_enables

biggest_size

57554

1

T2

13

T4

1

T10

2

values[0x1]

all_enables

biggest_size

54633

1

T2

1

T4

1

T6

2