Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16110789

1

T2

12204

T3

12402

T4

3425

full_word

164859200

1

T2

121365

T3

125312

T4

34434

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	180969719	1			T2	133569		T3	137714		T4	37859
auto[TlIntgErrCmd]	96	1			T71	4		T72	8		T73	3
auto[TlIntgErrData]	96	1			T71	2		T72	5		T73	2
auto[TlIntgErrBoth]	78	1			T71	4		T72	7		T73	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87472311

1

T2

62370

T3

68894

T4

18921

auto[1]

93497678

1

T2

71199

T3

68820

T4

18938

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7893589	1			T2	5680		T3	6254		T4	1677
auto[TlIntgErrNone]	partial	auto[1]	8216945	1			T2	6524		T3	6148		T4	1748
auto[TlIntgErrNone]	full_word	auto[0]	79578603	1			T2	56690		T3	62640		T4	17244
auto[TlIntgErrNone]	full_word	auto[1]	85280582	1			T2	64675		T3	62672		T4	17190
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T71	2		T72	4		T73	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T71	2		T72	4		T73	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T128	1		T133	1		T134	2
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T135	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	36	1			T72	3		T127	1		T131	1
auto[TlIntgErrData]	partial	auto[1]	52	1			T71	2		T72	2		T73	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T132	2		T134	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T127	1		T129	1		T136	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T71	3		T72	5		T73	3
auto[TlIntgErrBoth]	partial	auto[1]	40	1			T71	1		T72	2		T73	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T132	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1			T135	1		-	-		-	-