Group : dv_base_reg_pkg::mubi_cov#(8,32'h00000096,32'h00000069)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(8,32'h00000096,32'h00000069)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if 100.00 1 100 1 64 64




Group Instance : mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00


Variables for Group Instance mubi8_cov_of_mubi8_cov_of_tb.dut.u_otp_en_sram_ifetch_mubi_cov_if
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 10 0 10 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 63 1 T29 1 T23 2 T141 2
others[1] 59 1 T29 1 T70 3 T142 1
others[2] 67 1 T11 1 T68 1 T143 1
others[3] 52 1 T2 1 T68 2 T79 1
others[4] 57 1 T11 1 T29 2 T59 1
others[5] 59 1 T68 1 T70 2 T23 2
others[6] 58 1 T11 1 T29 1 T59 1
others[7] 58 1 T2 1 T139 1 T23 3
false 5874 1 T1 1 T2 5 T3 1
true 602 1 T2 3 T11 2 T29 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%