Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	780275	1			T2	38		T5	15326		T11	68
auto[1]	10584528	1			T2	464		T3	57545		T4	9483
auto[2]	586543	1			T2	38		T5	13069		T11	30
auto[3]	10331823	1			T2	281		T3	57376		T4	9454

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13407422	1			T2	568		T3	96083		T4	15561
auto[1]	2144007	1			T2	105		T3	8924		T4	1606
auto[2]	2181576	1			T2	130		T3	9078		T4	1594
auto[3]	4550164	1			T2	18		T3	836		T4	176

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8016787

1

T2

821

T3

31

T4

18936

auto[1]

14266382

1

T3

114890

T4

1

T5

52383

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	261691	1			T2	31		T11	56		T12	175
auto[0]	auto[0]	auto[1]	27268	1			T2	4		T11	9		T12	25
auto[0]	auto[0]	auto[2]	27000	1			T2	3		T11	3		T12	24
auto[0]	auto[0]	auto[3]	46191	1			T12	3		T45	213		T139	2
auto[0]	auto[1]	auto[0]	2855488	1			T2	337		T3	8		T4	7781
auto[0]	auto[1]	auto[1]	301081	1			T2	79		T3	1		T4	814
auto[0]	auto[1]	auto[2]	313938	1			T2	38		T3	4		T4	803
auto[0]	auto[1]	auto[3]	324239	1			T2	10		T4	85		T10	210
auto[0]	auto[2]	auto[0]	168273	1			T45	4		T9	16		T139	194
auto[0]	auto[2]	auto[1]	19860	1			T45	28		T9	1		T139	12
auto[0]	auto[2]	auto[2]	21743	1			T2	35		T11	29		T12	108
auto[0]	auto[2]	auto[3]	32444	1			T2	3		T11	1		T12	19
auto[0]	auto[3]	auto[0]	2713890	1			T2	200		T3	14		T4	7779
auto[0]	auto[3]	auto[1]	296401	1			T2	22		T3	2		T4	792
auto[0]	auto[3]	auto[2]	311125	1			T2	54		T3	2		T4	791
auto[0]	auto[3]	auto[3]	296155	1			T2	5		T4	91		T10	224
auto[1]	auto[0]	auto[0]	13701	1			T5	507		T117	1051		T119	1231
auto[1]	auto[0]	auto[1]	62042	1			T5	2256		T117	5073		T119	5650
auto[1]	auto[0]	auto[2]	61814	1			T5	2325		T117	5018		T119	5734
auto[1]	auto[0]	auto[3]	280568	1			T5	10238		T117	22828		T119	25778
auto[1]	auto[1]	auto[0]	3696254	1			T3	48049		T5	84		T6	1734
auto[1]	auto[1]	auto[1]	714313	1			T3	4259		T5	2342		T6	6911
auto[1]	auto[1]	auto[2]	689392	1			T3	4818		T5	377		T6	7707
auto[1]	auto[1]	auto[3]	1689823	1			T3	406		T5	10144		T6	30760
auto[1]	auto[2]	auto[0]	10589	1			T5	474		T117	1022		T119	1133
auto[1]	auto[2]	auto[1]	47923	1			T5	2136		T117	4692		T119	5197
auto[1]	auto[2]	auto[2]	51798	1			T5	1879		T117	3476		T119	4824
auto[1]	auto[2]	auto[3]	233913	1			T5	8580		T117	15211		T119	21482
auto[1]	auto[3]	auto[0]	3687536	1			T3	48012		T4	1		T5	47
auto[1]	auto[3]	auto[1]	675119	1			T3	4662		T5	163		T6	7570
auto[1]	auto[3]	auto[2]	704766	1			T3	4254		T5	1926		T6	6829
auto[1]	auto[3]	auto[3]	1646831	1			T3	430		T5	8905		T6	31346