Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1253523730	216746	0	0
ctrl_regwen_rd_A	1253523730	7012	0	0
exec_rd_A	1253523730	6375	0	0
exec_regwen_rd_A	1253523730	6774	0	0
readback_rd_A	1253523730	4235	0	0
readback_regwen_rd_A	1253523730	3816	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253523730	216746	0	0
T8	884930	0	0	0
T25	181837	5927	0	0
T26	27830	1265	0	0
T28	33102	914	0	0
T30	34494	0	0	0
T46	279235	0	0	0
T49	0	5320	0	0
T54	691594	0	0	0
T57	0	9136	0	0
T62	0	7362	0	0
T63	0	8678	0	0
T67	0	4655	0	0
T68	794778	0	0	0
T69	76519	0	0	0
T70	362371	0	0	0
T74	0	2114	0	0
T78	0	4279	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253523730	7012	0	0
T8	884930	0	0	0
T25	181837	540	0	0
T26	27830	108	0	0
T28	33102	20	0	0
T30	34494	0	0	0
T46	279235	0	0	0
T49	0	242	0	0
T50	0	314	0	0
T51	0	630	0	0
T54	691594	0	0	0
T68	794778	0	0	0
T69	76519	0	0	0
T70	362371	0	0	0
T78	0	206	0	0
T123	0	88	0	0
T124	0	280	0	0
T125	0	228	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253523730	6375	0	0
T8	884930	0	0	0
T25	181837	449	0	0
T26	27830	67	0	0
T28	33102	40	0	0
T30	34494	0	0	0
T46	279235	0	0	0
T49	0	189	0	0
T50	0	296	0	0
T51	0	457	0	0
T54	691594	0	0	0
T68	794778	0	0	0
T69	76519	0	0	0
T70	362371	0	0	0
T78	0	180	0	0
T123	0	80	0	0
T124	0	208	0	0
T125	0	240	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253523730	6774	0	0
T8	884930	0	0	0
T25	181837	392	0	0
T26	27830	127	0	0
T28	33102	31	0	0
T30	34494	0	0	0
T46	279235	0	0	0
T49	0	204	0	0
T50	0	292	0	0
T51	0	472	0	0
T54	691594	0	0	0
T68	794778	0	0	0
T69	76519	0	0	0
T70	362371	0	0	0
T78	0	152	0	0
T123	0	122	0	0
T124	0	358	0	0
T125	0	291	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253523730	4235	0	0
T8	884930	0	0	0
T25	181837	392	0	0
T26	27830	87	0	0
T28	33102	45	0	0
T30	34494	0	0	0
T46	279235	0	0	0
T49	0	127	0	0
T50	0	240	0	0
T51	0	493	0	0
T54	691594	0	0	0
T68	794778	0	0	0
T69	76519	0	0	0
T70	362371	0	0	0
T78	0	156	0	0
T123	0	67	0	0
T124	0	207	0	0
T125	0	136	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1253523730	3816	0	0
T8	884930	0	0	0
T25	181837	280	0	0
T26	27830	76	0	0
T28	33102	15	0	0
T30	34494	0	0	0
T46	279235	0	0	0
T49	0	212	0	0
T50	0	216	0	0
T51	0	428	0	0
T54	691594	0	0	0
T68	794778	0	0	0
T69	76519	0	0	0
T70	362371	0	0	0
T78	0	191	0	0
T123	0	73	0	0
T124	0	160	0	0
T125	0	153	0	0