| T796 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.3632332167 |
|
|
Jul 20 06:13:29 PM PDT 24 |
Jul 20 06:14:15 PM PDT 24 |
23700004949 ps |
| T797 |
/workspace/coverage/default/46.sram_ctrl_alert_test.1056272471 |
|
|
Jul 20 06:17:09 PM PDT 24 |
Jul 20 06:17:10 PM PDT 24 |
26138785 ps |
| T798 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.1368050112 |
|
|
Jul 20 06:15:48 PM PDT 24 |
Jul 20 06:20:58 PM PDT 24 |
12254375554 ps |
| T799 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1115109012 |
|
|
Jul 20 06:12:31 PM PDT 24 |
Jul 20 06:13:30 PM PDT 24 |
781143244 ps |
| T800 |
/workspace/coverage/default/19.sram_ctrl_regwen.375214070 |
|
|
Jul 20 06:13:26 PM PDT 24 |
Jul 20 06:25:00 PM PDT 24 |
12720346284 ps |
| T801 |
/workspace/coverage/default/35.sram_ctrl_executable.1342554020 |
|
|
Jul 20 06:15:28 PM PDT 24 |
Jul 20 06:17:48 PM PDT 24 |
1660962193 ps |
| T802 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.1566528988 |
|
|
Jul 20 06:14:20 PM PDT 24 |
Jul 20 06:15:09 PM PDT 24 |
768267139 ps |
| T803 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1565024595 |
|
|
Jul 20 06:17:24 PM PDT 24 |
Jul 20 06:25:40 PM PDT 24 |
38958395087 ps |
| T804 |
/workspace/coverage/default/13.sram_ctrl_alert_test.3771562044 |
|
|
Jul 20 06:12:57 PM PDT 24 |
Jul 20 06:12:58 PM PDT 24 |
32977832 ps |
| T805 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.3635770324 |
|
|
Jul 20 06:13:29 PM PDT 24 |
Jul 20 06:16:10 PM PDT 24 |
10513788363 ps |
| T17 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.1453397717 |
|
|
Jul 20 06:12:35 PM PDT 24 |
Jul 20 06:12:41 PM PDT 24 |
280725585 ps |
| T806 |
/workspace/coverage/default/15.sram_ctrl_partial_access.3672353185 |
|
|
Jul 20 06:13:05 PM PDT 24 |
Jul 20 06:13:37 PM PDT 24 |
969800274 ps |
| T807 |
/workspace/coverage/default/46.sram_ctrl_smoke.2586832905 |
|
|
Jul 20 06:17:01 PM PDT 24 |
Jul 20 06:17:16 PM PDT 24 |
1476155161 ps |
| T808 |
/workspace/coverage/default/41.sram_ctrl_stress_all.3341347684 |
|
|
Jul 20 06:16:27 PM PDT 24 |
Jul 20 07:59:11 PM PDT 24 |
1046013349672 ps |
| T809 |
/workspace/coverage/default/9.sram_ctrl_stress_all.3658782065 |
|
|
Jul 20 06:12:54 PM PDT 24 |
Jul 20 07:30:45 PM PDT 24 |
732922869520 ps |
| T810 |
/workspace/coverage/default/22.sram_ctrl_smoke.1047010581 |
|
|
Jul 20 06:13:38 PM PDT 24 |
Jul 20 06:14:01 PM PDT 24 |
871044601 ps |
| T811 |
/workspace/coverage/default/10.sram_ctrl_smoke.2883593763 |
|
|
Jul 20 06:12:53 PM PDT 24 |
Jul 20 06:14:36 PM PDT 24 |
6849332631 ps |
| T812 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2140644053 |
|
|
Jul 20 06:12:47 PM PDT 24 |
Jul 20 06:12:52 PM PDT 24 |
676538067 ps |
| T813 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1551807207 |
|
|
Jul 20 06:12:48 PM PDT 24 |
Jul 20 06:13:23 PM PDT 24 |
3695287430 ps |
| T814 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.69417150 |
|
|
Jul 20 06:15:34 PM PDT 24 |
Jul 20 06:22:19 PM PDT 24 |
33197629983 ps |
| T815 |
/workspace/coverage/default/43.sram_ctrl_regwen.487216715 |
|
|
Jul 20 06:17:20 PM PDT 24 |
Jul 20 06:26:31 PM PDT 24 |
5765981065 ps |
| T816 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.1151014551 |
|
|
Jul 20 06:16:26 PM PDT 24 |
Jul 20 06:22:32 PM PDT 24 |
98851385088 ps |
| T817 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.3061043339 |
|
|
Jul 20 06:17:15 PM PDT 24 |
Jul 20 06:17:55 PM PDT 24 |
750327176 ps |
| T818 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.3460171505 |
|
|
Jul 20 06:13:09 PM PDT 24 |
Jul 20 06:15:21 PM PDT 24 |
6305242068 ps |
| T819 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.2567348565 |
|
|
Jul 20 06:12:34 PM PDT 24 |
Jul 20 06:12:39 PM PDT 24 |
641016370 ps |
| T820 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.574236803 |
|
|
Jul 20 06:15:58 PM PDT 24 |
Jul 20 06:19:35 PM PDT 24 |
7842936838 ps |
| T821 |
/workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.847240695 |
|
|
Jul 20 06:13:54 PM PDT 24 |
Jul 20 06:14:03 PM PDT 24 |
296096785 ps |
| T822 |
/workspace/coverage/default/29.sram_ctrl_executable.1680255278 |
|
|
Jul 20 06:14:36 PM PDT 24 |
Jul 20 06:35:23 PM PDT 24 |
57768743593 ps |
| T823 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.1223425040 |
|
|
Jul 20 06:13:29 PM PDT 24 |
Jul 20 06:13:49 PM PDT 24 |
725627914 ps |
| T824 |
/workspace/coverage/default/13.sram_ctrl_stress_all.3485956067 |
|
|
Jul 20 06:12:56 PM PDT 24 |
Jul 20 08:10:21 PM PDT 24 |
393604884911 ps |
| T825 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.1165735417 |
|
|
Jul 20 06:15:01 PM PDT 24 |
Jul 20 06:16:28 PM PDT 24 |
5366163922 ps |
| T826 |
/workspace/coverage/default/6.sram_ctrl_smoke.2166886299 |
|
|
Jul 20 06:12:45 PM PDT 24 |
Jul 20 06:14:30 PM PDT 24 |
1213296951 ps |
| T827 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.3218457227 |
|
|
Jul 20 06:15:18 PM PDT 24 |
Jul 20 06:35:35 PM PDT 24 |
58739766979 ps |
| T828 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.28006804 |
|
|
Jul 20 06:16:36 PM PDT 24 |
Jul 20 06:20:26 PM PDT 24 |
16302095617 ps |
| T829 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3859629390 |
|
|
Jul 20 06:14:09 PM PDT 24 |
Jul 20 06:17:14 PM PDT 24 |
10516399253 ps |
| T830 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2031563211 |
|
|
Jul 20 06:12:48 PM PDT 24 |
Jul 20 06:13:22 PM PDT 24 |
20240247701 ps |
| T831 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1149661809 |
|
|
Jul 20 06:12:34 PM PDT 24 |
Jul 20 06:14:07 PM PDT 24 |
2982422950 ps |
| T832 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.4080487779 |
|
|
Jul 20 06:16:39 PM PDT 24 |
Jul 20 06:16:43 PM PDT 24 |
706984057 ps |
| T833 |
/workspace/coverage/default/45.sram_ctrl_smoke.3129366680 |
|
|
Jul 20 06:16:53 PM PDT 24 |
Jul 20 06:17:30 PM PDT 24 |
533638251 ps |
| T834 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2945456913 |
|
|
Jul 20 06:12:25 PM PDT 24 |
Jul 20 06:13:13 PM PDT 24 |
2130255036 ps |
| T835 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3088486374 |
|
|
Jul 20 06:16:44 PM PDT 24 |
Jul 20 06:22:33 PM PDT 24 |
13016759020 ps |
| T836 |
/workspace/coverage/default/7.sram_ctrl_partial_access.341134541 |
|
|
Jul 20 06:12:42 PM PDT 24 |
Jul 20 06:13:30 PM PDT 24 |
3128745799 ps |
| T837 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.2654757831 |
|
|
Jul 20 06:16:27 PM PDT 24 |
Jul 20 06:17:25 PM PDT 24 |
888121105 ps |
| T838 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.1843557876 |
|
|
Jul 20 06:13:00 PM PDT 24 |
Jul 20 06:15:11 PM PDT 24 |
1620503592 ps |
| T839 |
/workspace/coverage/default/12.sram_ctrl_stress_all.3331672340 |
|
|
Jul 20 06:12:53 PM PDT 24 |
Jul 20 07:52:04 PM PDT 24 |
39893811519 ps |
| T840 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.1722385188 |
|
|
Jul 20 06:12:31 PM PDT 24 |
Jul 20 06:12:39 PM PDT 24 |
1281017913 ps |
| T841 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.3403847303 |
|
|
Jul 20 06:16:00 PM PDT 24 |
Jul 20 06:16:04 PM PDT 24 |
1351515969 ps |
| T842 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.1673151591 |
|
|
Jul 20 06:15:16 PM PDT 24 |
Jul 20 06:15:20 PM PDT 24 |
352687438 ps |
| T843 |
/workspace/coverage/default/48.sram_ctrl_executable.2717072727 |
|
|
Jul 20 06:17:23 PM PDT 24 |
Jul 20 06:42:05 PM PDT 24 |
103614202534 ps |
| T844 |
/workspace/coverage/default/2.sram_ctrl_partial_access.2373727421 |
|
|
Jul 20 06:12:36 PM PDT 24 |
Jul 20 06:12:52 PM PDT 24 |
3811474892 ps |
| T845 |
/workspace/coverage/default/28.sram_ctrl_mem_partial_access.595868829 |
|
|
Jul 20 06:14:29 PM PDT 24 |
Jul 20 06:15:47 PM PDT 24 |
4547268087 ps |
| T846 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.4129699656 |
|
|
Jul 20 06:16:43 PM PDT 24 |
Jul 20 06:16:48 PM PDT 24 |
706887655 ps |
| T847 |
/workspace/coverage/default/26.sram_ctrl_partial_access.3339850777 |
|
|
Jul 20 06:14:10 PM PDT 24 |
Jul 20 06:14:20 PM PDT 24 |
2623168322 ps |
| T848 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.133217475 |
|
|
Jul 20 06:13:09 PM PDT 24 |
Jul 20 06:13:19 PM PDT 24 |
270332592 ps |
| T849 |
/workspace/coverage/default/13.sram_ctrl_regwen.615317213 |
|
|
Jul 20 06:13:00 PM PDT 24 |
Jul 20 06:22:37 PM PDT 24 |
15881797187 ps |
| T850 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.1255478484 |
|
|
Jul 20 06:14:42 PM PDT 24 |
Jul 20 06:22:11 PM PDT 24 |
22527573190 ps |
| T851 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.1415734411 |
|
|
Jul 20 06:12:43 PM PDT 24 |
Jul 20 06:12:49 PM PDT 24 |
709995157 ps |
| T852 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1519467856 |
|
|
Jul 20 06:12:53 PM PDT 24 |
Jul 20 06:13:42 PM PDT 24 |
1164044885 ps |
| T853 |
/workspace/coverage/default/36.sram_ctrl_smoke.3129241065 |
|
|
Jul 20 06:15:34 PM PDT 24 |
Jul 20 06:15:48 PM PDT 24 |
3411359648 ps |
| T854 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.3387127731 |
|
|
Jul 20 06:12:52 PM PDT 24 |
Jul 20 06:14:14 PM PDT 24 |
8748355908 ps |
| T855 |
/workspace/coverage/default/1.sram_ctrl_stress_all.1232024181 |
|
|
Jul 20 06:12:37 PM PDT 24 |
Jul 20 06:52:32 PM PDT 24 |
105910745815 ps |
| T856 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2216865095 |
|
|
Jul 20 06:12:26 PM PDT 24 |
Jul 20 06:16:08 PM PDT 24 |
3086021304 ps |
| T857 |
/workspace/coverage/default/14.sram_ctrl_stress_all.3431757909 |
|
|
Jul 20 06:12:59 PM PDT 24 |
Jul 20 07:38:34 PM PDT 24 |
390196270573 ps |
| T858 |
/workspace/coverage/default/4.sram_ctrl_partial_access.406913717 |
|
|
Jul 20 06:12:33 PM PDT 24 |
Jul 20 06:12:58 PM PDT 24 |
2735100021 ps |
| T859 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.139570301 |
|
|
Jul 20 06:12:52 PM PDT 24 |
Jul 20 06:13:36 PM PDT 24 |
779414319 ps |
| T860 |
/workspace/coverage/default/18.sram_ctrl_bijection.2300619752 |
|
|
Jul 20 06:13:19 PM PDT 24 |
Jul 20 06:44:12 PM PDT 24 |
150484080610 ps |
| T861 |
/workspace/coverage/default/39.sram_ctrl_regwen.863435831 |
|
|
Jul 20 06:16:01 PM PDT 24 |
Jul 20 06:32:32 PM PDT 24 |
71232780661 ps |
| T862 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.352213757 |
|
|
Jul 20 06:12:41 PM PDT 24 |
Jul 20 06:22:11 PM PDT 24 |
16970676448 ps |
| T863 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3959057587 |
|
|
Jul 20 06:12:43 PM PDT 24 |
Jul 20 06:13:30 PM PDT 24 |
6272950180 ps |
| T864 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.4146426420 |
|
|
Jul 20 06:12:52 PM PDT 24 |
Jul 20 06:15:23 PM PDT 24 |
795804806 ps |
| T865 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.4089574988 |
|
|
Jul 20 06:12:48 PM PDT 24 |
Jul 20 06:17:07 PM PDT 24 |
17130074398 ps |
| T866 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.1068045639 |
|
|
Jul 20 06:16:00 PM PDT 24 |
Jul 20 06:16:58 PM PDT 24 |
9513504033 ps |
| T867 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3885688862 |
|
|
Jul 20 06:12:27 PM PDT 24 |
Jul 20 06:17:17 PM PDT 24 |
9825401978 ps |
| T868 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.3281488470 |
|
|
Jul 20 06:12:53 PM PDT 24 |
Jul 20 06:13:04 PM PDT 24 |
689108566 ps |
| T869 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.385472740 |
|
|
Jul 20 06:14:59 PM PDT 24 |
Jul 20 06:18:35 PM PDT 24 |
10923945337 ps |
| T870 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4127768494 |
|
|
Jul 20 06:14:04 PM PDT 24 |
Jul 20 06:14:46 PM PDT 24 |
19279451586 ps |
| T101 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.2963088648 |
|
|
Jul 20 06:12:34 PM PDT 24 |
Jul 20 06:15:19 PM PDT 24 |
48219394238 ps |
| T871 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.463484231 |
|
|
Jul 20 06:16:28 PM PDT 24 |
Jul 20 06:52:12 PM PDT 24 |
74978514048 ps |
| T872 |
/workspace/coverage/default/22.sram_ctrl_executable.3528474027 |
|
|
Jul 20 06:13:45 PM PDT 24 |
Jul 20 06:32:14 PM PDT 24 |
62533107950 ps |
| T873 |
/workspace/coverage/default/48.sram_ctrl_bijection.1398827609 |
|
|
Jul 20 06:17:16 PM PDT 24 |
Jul 20 06:46:36 PM PDT 24 |
40587342909 ps |
| T874 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2987568890 |
|
|
Jul 20 06:17:40 PM PDT 24 |
Jul 20 06:17:44 PM PDT 24 |
1358114705 ps |
| T875 |
/workspace/coverage/default/25.sram_ctrl_partial_access.3153637055 |
|
|
Jul 20 06:14:05 PM PDT 24 |
Jul 20 06:14:19 PM PDT 24 |
1035473354 ps |
| T876 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.226709045 |
|
|
Jul 20 06:12:52 PM PDT 24 |
Jul 20 06:15:47 PM PDT 24 |
6107669357 ps |
| T877 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.1059341680 |
|
|
Jul 20 06:15:18 PM PDT 24 |
Jul 20 06:22:52 PM PDT 24 |
22582258260 ps |
| T878 |
/workspace/coverage/default/27.sram_ctrl_stress_all.246808483 |
|
|
Jul 20 06:14:16 PM PDT 24 |
Jul 20 06:51:03 PM PDT 24 |
117736626166 ps |
| T879 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.1369039741 |
|
|
Jul 20 06:13:21 PM PDT 24 |
Jul 20 06:19:31 PM PDT 24 |
147970806400 ps |
| T880 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1787237923 |
|
|
Jul 20 06:17:15 PM PDT 24 |
Jul 20 06:32:56 PM PDT 24 |
15603935450 ps |
| T881 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2876963305 |
|
|
Jul 20 06:12:43 PM PDT 24 |
Jul 20 06:17:40 PM PDT 24 |
4145393821 ps |
| T882 |
/workspace/coverage/default/27.sram_ctrl_alert_test.3853702081 |
|
|
Jul 20 06:14:21 PM PDT 24 |
Jul 20 06:14:22 PM PDT 24 |
16312039 ps |
| T33 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.3250105445 |
|
|
Jul 20 06:12:31 PM PDT 24 |
Jul 20 06:12:35 PM PDT 24 |
116300609 ps |
| T883 |
/workspace/coverage/default/28.sram_ctrl_executable.1144562452 |
|
|
Jul 20 06:14:30 PM PDT 24 |
Jul 20 06:32:45 PM PDT 24 |
37724864960 ps |
| T884 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3791464227 |
|
|
Jul 20 06:15:08 PM PDT 24 |
Jul 20 06:17:27 PM PDT 24 |
1511870665 ps |
| T885 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3932501424 |
|
|
Jul 20 06:13:03 PM PDT 24 |
Jul 20 06:22:36 PM PDT 24 |
202016530416 ps |
| T886 |
/workspace/coverage/default/26.sram_ctrl_alert_test.4021042628 |
|
|
Jul 20 06:14:14 PM PDT 24 |
Jul 20 06:14:15 PM PDT 24 |
40185489 ps |
| T887 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.655527667 |
|
|
Jul 20 06:13:38 PM PDT 24 |
Jul 20 06:21:59 PM PDT 24 |
23294625599 ps |
| T888 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.133428573 |
|
|
Jul 20 06:12:52 PM PDT 24 |
Jul 20 06:24:40 PM PDT 24 |
31730488406 ps |
| T889 |
/workspace/coverage/default/49.sram_ctrl_bijection.1446093813 |
|
|
Jul 20 06:17:34 PM PDT 24 |
Jul 20 06:30:59 PM PDT 24 |
190840462503 ps |
| T890 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.211888515 |
|
|
Jul 20 06:13:13 PM PDT 24 |
Jul 20 06:17:29 PM PDT 24 |
11910742950 ps |
| T891 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2216657963 |
|
|
Jul 20 06:14:04 PM PDT 24 |
Jul 20 06:26:25 PM PDT 24 |
38725601497 ps |
| T892 |
/workspace/coverage/default/40.sram_ctrl_partial_access.4873768 |
|
|
Jul 20 06:16:09 PM PDT 24 |
Jul 20 06:17:00 PM PDT 24 |
3501349863 ps |
| T893 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.77236891 |
|
|
Jul 20 06:14:38 PM PDT 24 |
Jul 20 06:15:14 PM PDT 24 |
1480992210 ps |
| T894 |
/workspace/coverage/default/47.sram_ctrl_bijection.3521098351 |
|
|
Jul 20 06:17:07 PM PDT 24 |
Jul 20 06:45:29 PM PDT 24 |
288188549834 ps |
| T895 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.2342286464 |
|
|
Jul 20 06:15:26 PM PDT 24 |
Jul 20 06:35:44 PM PDT 24 |
11069775306 ps |
| T896 |
/workspace/coverage/default/38.sram_ctrl_alert_test.77274484 |
|
|
Jul 20 06:15:56 PM PDT 24 |
Jul 20 06:15:57 PM PDT 24 |
53562788 ps |
| T897 |
/workspace/coverage/default/42.sram_ctrl_smoke.3171907210 |
|
|
Jul 20 06:16:27 PM PDT 24 |
Jul 20 06:16:42 PM PDT 24 |
2892576108 ps |
| T34 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.580173903 |
|
|
Jul 20 06:12:36 PM PDT 24 |
Jul 20 06:12:40 PM PDT 24 |
230043782 ps |
| T898 |
/workspace/coverage/default/49.sram_ctrl_alert_test.2896214256 |
|
|
Jul 20 06:17:40 PM PDT 24 |
Jul 20 06:17:41 PM PDT 24 |
21036080 ps |
| T899 |
/workspace/coverage/default/15.sram_ctrl_executable.3471068955 |
|
|
Jul 20 06:12:59 PM PDT 24 |
Jul 20 06:39:25 PM PDT 24 |
114145696287 ps |
| T900 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.803189300 |
|
|
Jul 20 06:14:14 PM PDT 24 |
Jul 20 06:14:52 PM PDT 24 |
737137999 ps |
| T901 |
/workspace/coverage/default/27.sram_ctrl_regwen.2533549762 |
|
|
Jul 20 06:14:20 PM PDT 24 |
Jul 20 06:33:04 PM PDT 24 |
27532935852 ps |
| T902 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.989529784 |
|
|
Jul 20 06:14:17 PM PDT 24 |
Jul 20 06:33:48 PM PDT 24 |
18841183743 ps |
| T903 |
/workspace/coverage/default/6.sram_ctrl_alert_test.3615073877 |
|
|
Jul 20 06:12:44 PM PDT 24 |
Jul 20 06:12:47 PM PDT 24 |
33386428 ps |
| T904 |
/workspace/coverage/default/17.sram_ctrl_stress_all.2329030033 |
|
|
Jul 20 06:13:07 PM PDT 24 |
Jul 20 06:40:37 PM PDT 24 |
77089088452 ps |
| T905 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.4026259101 |
|
|
Jul 20 06:16:33 PM PDT 24 |
Jul 20 06:19:28 PM PDT 24 |
115903166362 ps |
| T906 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1148841563 |
|
|
Jul 20 06:14:54 PM PDT 24 |
Jul 20 06:21:14 PM PDT 24 |
7426296182 ps |
| T907 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.4050653474 |
|
|
Jul 20 06:15:08 PM PDT 24 |
Jul 20 06:15:25 PM PDT 24 |
786621954 ps |
| T908 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.2177793465 |
|
|
Jul 20 06:15:50 PM PDT 24 |
Jul 20 06:15:54 PM PDT 24 |
350956430 ps |
| T909 |
/workspace/coverage/default/46.sram_ctrl_executable.272938667 |
|
|
Jul 20 06:16:59 PM PDT 24 |
Jul 20 06:29:21 PM PDT 24 |
4950732010 ps |
| T910 |
/workspace/coverage/default/45.sram_ctrl_alert_test.2578715499 |
|
|
Jul 20 06:16:59 PM PDT 24 |
Jul 20 06:17:01 PM PDT 24 |
11604051 ps |
| T911 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.4085873610 |
|
|
Jul 20 06:17:39 PM PDT 24 |
Jul 20 06:20:30 PM PDT 24 |
5003178262 ps |
| T912 |
/workspace/coverage/default/0.sram_ctrl_regwen.138784644 |
|
|
Jul 20 06:12:26 PM PDT 24 |
Jul 20 06:17:31 PM PDT 24 |
1098095837 ps |
| T913 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1661591295 |
|
|
Jul 20 06:12:47 PM PDT 24 |
Jul 20 06:21:04 PM PDT 24 |
6759731621 ps |
| T914 |
/workspace/coverage/default/19.sram_ctrl_smoke.2050237667 |
|
|
Jul 20 06:13:18 PM PDT 24 |
Jul 20 06:13:49 PM PDT 24 |
9816506654 ps |
| T915 |
/workspace/coverage/default/43.sram_ctrl_bijection.1404876840 |
|
|
Jul 20 06:16:30 PM PDT 24 |
Jul 20 06:46:24 PM PDT 24 |
207154221739 ps |
| T916 |
/workspace/coverage/default/46.sram_ctrl_partial_access.3565214795 |
|
|
Jul 20 06:16:57 PM PDT 24 |
Jul 20 06:17:20 PM PDT 24 |
1686977254 ps |
| T917 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.2484417486 |
|
|
Jul 20 06:13:04 PM PDT 24 |
Jul 20 06:14:06 PM PDT 24 |
34787951822 ps |
| T918 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.4078540858 |
|
|
Jul 20 06:15:33 PM PDT 24 |
Jul 20 06:40:09 PM PDT 24 |
19782278037 ps |
| T919 |
/workspace/coverage/default/26.sram_ctrl_ram_cfg.3451696343 |
|
|
Jul 20 06:14:12 PM PDT 24 |
Jul 20 06:14:16 PM PDT 24 |
365828574 ps |
| T920 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.637581965 |
|
|
Jul 20 06:15:18 PM PDT 24 |
Jul 20 06:18:02 PM PDT 24 |
8971996614 ps |
| T921 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3679832556 |
|
|
Jul 20 06:13:04 PM PDT 24 |
Jul 20 06:14:23 PM PDT 24 |
773463708 ps |
| T922 |
/workspace/coverage/default/42.sram_ctrl_regwen.2149893893 |
|
|
Jul 20 06:16:27 PM PDT 24 |
Jul 20 06:34:16 PM PDT 24 |
55438820312 ps |
| T923 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1816360112 |
|
|
Jul 20 06:17:42 PM PDT 24 |
Jul 20 06:27:36 PM PDT 24 |
23932275680 ps |
| T924 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1313645466 |
|
|
Jul 20 06:17:01 PM PDT 24 |
Jul 20 06:17:14 PM PDT 24 |
2873960438 ps |
| T925 |
/workspace/coverage/default/33.sram_ctrl_alert_test.725618066 |
|
|
Jul 20 06:15:11 PM PDT 24 |
Jul 20 06:15:12 PM PDT 24 |
19860699 ps |
| T926 |
/workspace/coverage/default/13.sram_ctrl_smoke.403371265 |
|
|
Jul 20 06:12:59 PM PDT 24 |
Jul 20 06:13:08 PM PDT 24 |
1038972348 ps |
| T927 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.3390143528 |
|
|
Jul 20 06:17:42 PM PDT 24 |
Jul 20 06:21:59 PM PDT 24 |
28154693650 ps |
| T928 |
/workspace/coverage/default/20.sram_ctrl_stress_all.2231877790 |
|
|
Jul 20 06:13:29 PM PDT 24 |
Jul 20 07:20:30 PM PDT 24 |
258158342010 ps |
| T929 |
/workspace/coverage/default/32.sram_ctrl_alert_test.92626465 |
|
|
Jul 20 06:14:59 PM PDT 24 |
Jul 20 06:15:00 PM PDT 24 |
80508660 ps |
| T930 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3812362515 |
|
|
Jul 20 06:14:52 PM PDT 24 |
Jul 20 06:21:27 PM PDT 24 |
63742411980 ps |
| T931 |
/workspace/coverage/default/0.sram_ctrl_smoke.2689197974 |
|
|
Jul 20 06:12:31 PM PDT 24 |
Jul 20 06:12:54 PM PDT 24 |
1987794923 ps |
| T932 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.1013562915 |
|
|
Jul 20 06:13:38 PM PDT 24 |
Jul 20 06:30:06 PM PDT 24 |
88400440192 ps |
| T933 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.2067900689 |
|
|
Jul 20 06:13:16 PM PDT 24 |
Jul 20 06:16:20 PM PDT 24 |
2705967118 ps |
| T934 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2105028307 |
|
|
Jul 20 06:16:19 PM PDT 24 |
Jul 20 06:17:24 PM PDT 24 |
3834770914 ps |
| T935 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3254903168 |
|
|
Jul 20 06:12:50 PM PDT 24 |
Jul 20 06:18:26 PM PDT 24 |
18309709030 ps |
| T936 |
/workspace/coverage/default/28.sram_ctrl_regwen.3187331453 |
|
|
Jul 20 06:14:26 PM PDT 24 |
Jul 20 06:26:36 PM PDT 24 |
11219125019 ps |
| T937 |
/workspace/coverage/default/28.sram_ctrl_smoke.3447936645 |
|
|
Jul 20 06:14:21 PM PDT 24 |
Jul 20 06:16:40 PM PDT 24 |
810768737 ps |
| T938 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.479211439 |
|
|
Jul 20 06:17:15 PM PDT 24 |
Jul 20 06:18:28 PM PDT 24 |
3013057008 ps |
| T939 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.420006541 |
|
|
Jul 20 06:12:35 PM PDT 24 |
Jul 20 06:12:40 PM PDT 24 |
1542234644 ps |
| T940 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.2335335952 |
|
|
Jul 20 06:13:03 PM PDT 24 |
Jul 20 06:15:01 PM PDT 24 |
3188345847 ps |
| T941 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.3316338961 |
|
|
Jul 20 06:13:08 PM PDT 24 |
Jul 20 06:28:24 PM PDT 24 |
71719140989 ps |
| T942 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4279013161 |
|
|
Jul 20 06:48:38 PM PDT 24 |
Jul 20 06:48:45 PM PDT 24 |
46137018 ps |
| T75 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.471169024 |
|
|
Jul 20 06:48:41 PM PDT 24 |
Jul 20 06:49:40 PM PDT 24 |
7399950494 ps |
| T943 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4255000751 |
|
|
Jul 20 06:48:40 PM PDT 24 |
Jul 20 06:48:48 PM PDT 24 |
1463194479 ps |
| T76 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2063842319 |
|
|
Jul 20 06:48:47 PM PDT 24 |
Jul 20 06:49:59 PM PDT 24 |
117569350913 ps |
| T77 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1097590126 |
|
|
Jul 20 06:48:49 PM PDT 24 |
Jul 20 06:49:17 PM PDT 24 |
14814679033 ps |
| T71 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.97153320 |
|
|
Jul 20 06:48:42 PM PDT 24 |
Jul 20 06:48:46 PM PDT 24 |
476377595 ps |
| T80 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1594031474 |
|
|
Jul 20 06:48:52 PM PDT 24 |
Jul 20 06:48:54 PM PDT 24 |
10659352 ps |
| T112 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3737215805 |
|
|
Jul 20 06:48:47 PM PDT 24 |
Jul 20 06:48:48 PM PDT 24 |
137656082 ps |
| T113 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.945792650 |
|
|
Jul 20 06:48:42 PM PDT 24 |
Jul 20 06:48:45 PM PDT 24 |
35826569 ps |
| T114 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1535031727 |
|
|
Jul 20 06:48:39 PM PDT 24 |
Jul 20 06:48:42 PM PDT 24 |
28723020 ps |
| T72 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4278883427 |
|
|
Jul 20 06:48:50 PM PDT 24 |
Jul 20 06:48:54 PM PDT 24 |
349460174 ps |
| T944 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2551666471 |
|
|
Jul 20 06:48:40 PM PDT 24 |
Jul 20 06:48:47 PM PDT 24 |
356194906 ps |
| T81 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.217328933 |
|
|
Jul 20 06:48:56 PM PDT 24 |
Jul 20 06:49:57 PM PDT 24 |
29410978055 ps |
| T73 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3440858290 |
|
|
Jul 20 06:48:43 PM PDT 24 |
Jul 20 06:48:47 PM PDT 24 |
318835675 ps |
| T127 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4112310038 |
|
|
Jul 20 06:48:50 PM PDT 24 |
Jul 20 06:48:53 PM PDT 24 |
1194452749 ps |
| T122 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3132892510 |
|
|
Jul 20 06:48:38 PM PDT 24 |
Jul 20 06:48:42 PM PDT 24 |
29081852 ps |
| T131 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3126889575 |
|
|
Jul 20 06:48:42 PM PDT 24 |
Jul 20 06:48:46 PM PDT 24 |
113663434 ps |
| T945 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1832103943 |
|
|
Jul 20 06:48:49 PM PDT 24 |
Jul 20 06:48:54 PM PDT 24 |
1352607336 ps |
| T946 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2387363652 |
|
|
Jul 20 06:48:53 PM PDT 24 |
Jul 20 06:48:57 PM PDT 24 |
1109366527 ps |
| T115 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.697470095 |
|
|
Jul 20 06:48:48 PM PDT 24 |
Jul 20 06:48:49 PM PDT 24 |
40661831 ps |
| T947 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3040806114 |
|
|
Jul 20 06:49:00 PM PDT 24 |
Jul 20 06:49:05 PM PDT 24 |
354172146 ps |
| T82 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2832296508 |
|
|
Jul 20 06:48:38 PM PDT 24 |
Jul 20 06:49:13 PM PDT 24 |
37016011508 ps |
| T948 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.666713077 |
|
|
Jul 20 06:48:57 PM PDT 24 |
Jul 20 06:49:02 PM PDT 24 |
47204729 ps |
| T949 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3166524960 |
|
|
Jul 20 06:48:56 PM PDT 24 |
Jul 20 06:49:01 PM PDT 24 |
698163751 ps |
| T950 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3792113419 |
|
|
Jul 20 06:48:42 PM PDT 24 |
Jul 20 06:48:47 PM PDT 24 |
120596714 ps |
| T83 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.866931269 |
|
|
Jul 20 06:48:51 PM PDT 24 |
Jul 20 06:49:53 PM PDT 24 |
29405944787 ps |
| T84 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3563458130 |
|
|
Jul 20 06:48:48 PM PDT 24 |
Jul 20 06:48:50 PM PDT 24 |
83526330 ps |
| T951 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1556001058 |
|
|
Jul 20 06:48:38 PM PDT 24 |
Jul 20 06:48:42 PM PDT 24 |
32051757 ps |
| T952 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.97784969 |
|
|
Jul 20 06:48:50 PM PDT 24 |
Jul 20 06:48:53 PM PDT 24 |
21440231 ps |
| T85 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2277833684 |
|
|
Jul 20 06:48:59 PM PDT 24 |
Jul 20 06:49:01 PM PDT 24 |
49202308 ps |
| T128 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2073293266 |
|
|
Jul 20 06:48:46 PM PDT 24 |
Jul 20 06:48:48 PM PDT 24 |
135988409 ps |
| T86 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3466332013 |
|
|
Jul 20 06:48:48 PM PDT 24 |
Jul 20 06:48:49 PM PDT 24 |
45133888 ps |
| T953 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.888301775 |
|
|
Jul 20 06:49:04 PM PDT 24 |
Jul 20 06:49:06 PM PDT 24 |
32703535 ps |
| T954 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2217447687 |
|
|
Jul 20 06:48:56 PM PDT 24 |
Jul 20 06:49:02 PM PDT 24 |
1377701357 ps |
| T87 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3288126663 |
|
|
Jul 20 06:48:41 PM PDT 24 |
Jul 20 06:49:10 PM PDT 24 |
3768059377 ps |
| T955 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3535264276 |
|
|
Jul 20 06:48:40 PM PDT 24 |
Jul 20 06:48:46 PM PDT 24 |
117688702 ps |
| T956 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2091887545 |
|
|
Jul 20 06:48:40 PM PDT 24 |
Jul 20 06:48:44 PM PDT 24 |
24244560 ps |
| T88 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2957700188 |
|
|
Jul 20 06:48:48 PM PDT 24 |
Jul 20 06:49:19 PM PDT 24 |
10871289642 ps |
| T957 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3533676044 |
|
|
Jul 20 06:48:39 PM PDT 24 |
Jul 20 06:48:45 PM PDT 24 |
731924769 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2937152226 |
|
|
Jul 20 06:48:38 PM PDT 24 |
Jul 20 06:48:44 PM PDT 24 |
483109696 ps |
| T959 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4127883056 |
|
|
Jul 20 06:48:38 PM PDT 24 |
Jul 20 06:48:45 PM PDT 24 |
847468919 ps |
| T960 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.504915078 |
|
|
Jul 20 06:48:51 PM PDT 24 |
Jul 20 06:48:56 PM PDT 24 |
353854877 ps |
| T89 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2949754297 |
|
|
Jul 20 06:48:43 PM PDT 24 |
Jul 20 06:48:45 PM PDT 24 |
25632610 ps |
| T961 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3493276487 |
|
|
Jul 20 06:48:58 PM PDT 24 |
Jul 20 06:49:02 PM PDT 24 |
312029280 ps |
| T962 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3518903940 |
|
|
Jul 20 06:48:40 PM PDT 24 |
Jul 20 06:49:40 PM PDT 24 |
12389711000 ps |
| T963 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1621607565 |
|
|
Jul 20 06:48:49 PM PDT 24 |
Jul 20 06:48:50 PM PDT 24 |
36053744 ps |
| T129 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1418393948 |
|
|
Jul 20 06:48:49 PM PDT 24 |
Jul 20 06:48:52 PM PDT 24 |
112936028 ps |
| T964 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3212593579 |
|
|
Jul 20 06:48:42 PM PDT 24 |
Jul 20 06:48:45 PM PDT 24 |
33666304 ps |
| T965 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.805483916 |
|
|
Jul 20 06:48:52 PM PDT 24 |
Jul 20 06:48:57 PM PDT 24 |
378129587 ps |
| T966 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3003012536 |
|
|
Jul 20 06:48:52 PM PDT 24 |
Jul 20 06:48:56 PM PDT 24 |
364145014 ps |
| T90 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2557087036 |
|
|
Jul 20 06:48:49 PM PDT 24 |
Jul 20 06:49:41 PM PDT 24 |
7259768471 ps |
| T132 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1188589026 |
|
|
Jul 20 06:48:40 PM PDT 24 |
Jul 20 06:48:45 PM PDT 24 |
982531131 ps |
| T967 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1432925791 |
|
|
Jul 20 06:48:51 PM PDT 24 |
Jul 20 06:48:56 PM PDT 24 |
683928462 ps |
| T968 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1395910319 |
|
|
Jul 20 06:49:00 PM PDT 24 |
Jul 20 06:49:02 PM PDT 24 |
23313450 ps |
| T102 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2886314985 |
|
|
Jul 20 06:48:39 PM PDT 24 |
Jul 20 06:48:42 PM PDT 24 |
51416011 ps |
| T969 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3194653515 |
|
|
Jul 20 06:48:49 PM PDT 24 |
Jul 20 06:48:55 PM PDT 24 |
132495040 ps |
| T970 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1348132517 |
|
|
Jul 20 06:48:40 PM PDT 24 |
Jul 20 06:48:48 PM PDT 24 |
732667914 ps |
| T971 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1045651029 |
|
|
Jul 20 06:48:48 PM PDT 24 |
Jul 20 06:48:53 PM PDT 24 |
1412248980 ps |
| T972 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1922107003 |
|
|
Jul 20 06:48:57 PM PDT 24 |
Jul 20 06:49:02 PM PDT 24 |
228264678 ps |
| T973 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.640183663 |
|
|
Jul 20 06:48:58 PM PDT 24 |
Jul 20 06:49:01 PM PDT 24 |
21190151 ps |
| T133 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2672748474 |
|
|
Jul 20 06:48:49 PM PDT 24 |
Jul 20 06:48:52 PM PDT 24 |
146437820 ps |
| T974 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1307136275 |
|
|
Jul 20 06:48:58 PM PDT 24 |
Jul 20 06:49:02 PM PDT 24 |
1531132502 ps |
| T975 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.652000482 |
|
|
Jul 20 06:48:38 PM PDT 24 |
Jul 20 06:48:42 PM PDT 24 |
376102765 ps |
| T976 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.892288072 |
|
|
Jul 20 06:48:53 PM PDT 24 |
Jul 20 06:48:57 PM PDT 24 |
795471674 ps |
| T977 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1309153453 |
|
|
Jul 20 06:48:59 PM PDT 24 |
Jul 20 06:49:04 PM PDT 24 |
452761245 ps |
| T978 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1345899114 |
|
|
Jul 20 06:49:02 PM PDT 24 |
Jul 20 06:49:05 PM PDT 24 |
56021230 ps |
| T108 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2925013968 |
|
|
Jul 20 06:48:50 PM PDT 24 |
Jul 20 06:48:52 PM PDT 24 |
55931545 ps |
| T979 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3351559281 |
|
|
Jul 20 06:48:37 PM PDT 24 |
Jul 20 06:48:42 PM PDT 24 |
77348189 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2605749805 |
|
|
Jul 20 06:48:38 PM PDT 24 |
Jul 20 06:48:43 PM PDT 24 |
178632343 ps |
| T981 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2031260800 |
|
|
Jul 20 06:48:41 PM PDT 24 |
Jul 20 06:48:45 PM PDT 24 |
47070782 ps |
| T91 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1319766285 |
|
|
Jul 20 06:48:42 PM PDT 24 |
Jul 20 06:48:45 PM PDT 24 |
96736154 ps |
| T982 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1893845234 |
|
|
Jul 20 06:48:40 PM PDT 24 |
Jul 20 06:48:43 PM PDT 24 |
50356362 ps |
| T983 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2922839930 |
|
|
Jul 20 06:48:57 PM PDT 24 |
Jul 20 06:49:00 PM PDT 24 |
15492848 ps |
| T984 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4198294081 |
|
|
Jul 20 06:48:50 PM PDT 24 |
Jul 20 06:48:55 PM PDT 24 |
710553824 ps |
| T92 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1955215339 |
|
|
Jul 20 06:48:37 PM PDT 24 |
Jul 20 06:49:09 PM PDT 24 |
15397613297 ps |
| T103 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.591955845 |
|
|
Jul 20 06:48:41 PM PDT 24 |
Jul 20 06:49:13 PM PDT 24 |
15364166433 ps |
| T985 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1056128947 |
|
|
Jul 20 06:48:56 PM PDT 24 |
Jul 20 06:48:58 PM PDT 24 |
14612604 ps |
| T104 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.920845046 |
|
|
Jul 20 06:48:39 PM PDT 24 |
Jul 20 06:49:11 PM PDT 24 |
3783531212 ps |
| T986 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.558739468 |
|
|
Jul 20 06:48:43 PM PDT 24 |
Jul 20 06:48:46 PM PDT 24 |
34277668 ps |
| T987 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2735341360 |
|
|
Jul 20 06:48:40 PM PDT 24 |
Jul 20 06:48:46 PM PDT 24 |
154600875 ps |
| T988 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1849315922 |
|
|
Jul 20 06:48:49 PM PDT 24 |
Jul 20 06:48:54 PM PDT 24 |
29615293 ps |
| T989 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2063202819 |
|
|
Jul 20 06:48:51 PM PDT 24 |
Jul 20 06:48:53 PM PDT 24 |
47092240 ps |
| T990 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1894502409 |
|
|
Jul 20 06:48:37 PM PDT 24 |
Jul 20 06:48:40 PM PDT 24 |
19174236 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2482719705 |
|
|
Jul 20 06:48:43 PM PDT 24 |
Jul 20 06:48:46 PM PDT 24 |
87678920 ps |
| T992 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.742667053 |
|
|
Jul 20 06:48:48 PM PDT 24 |
Jul 20 06:48:54 PM PDT 24 |
528890829 ps |
| T993 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3084043508 |
|
|
Jul 20 06:48:49 PM PDT 24 |
Jul 20 06:48:52 PM PDT 24 |
42186545 ps |
| T105 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2279107422 |
|
|
Jul 20 06:48:34 PM PDT 24 |
Jul 20 06:48:37 PM PDT 24 |
22220568 ps |
| T994 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2148083020 |
|
|
Jul 20 06:48:51 PM PDT 24 |
Jul 20 06:49:46 PM PDT 24 |
7354775737 ps |
| T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2245662218 |
|
|
Jul 20 06:48:39 PM PDT 24 |
Jul 20 06:48:43 PM PDT 24 |
45471156 ps |
| T996 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2964479106 |
|
|
Jul 20 06:48:41 PM PDT 24 |
Jul 20 06:48:48 PM PDT 24 |
764094688 ps |
| T997 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1514172613 |
|
|
Jul 20 06:48:56 PM PDT 24 |
Jul 20 06:48:59 PM PDT 24 |
1545451478 ps |
| T998 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.356496324 |
|
|
Jul 20 06:48:50 PM PDT 24 |
Jul 20 06:49:21 PM PDT 24 |
15382908534 ps |
| T999 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3998920190 |
|
|
Jul 20 06:49:02 PM PDT 24 |
Jul 20 06:49:04 PM PDT 24 |
32818561 ps |
| T1000 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.202607070 |
|
|
Jul 20 06:48:50 PM PDT 24 |
Jul 20 06:49:17 PM PDT 24 |
4506718556 ps |
| T1001 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2880949753 |
|
|
Jul 20 06:48:42 PM PDT 24 |
Jul 20 06:48:45 PM PDT 24 |
21178523 ps |
| T136 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3070262726 |
|
|
Jul 20 06:48:48 PM PDT 24 |
Jul 20 06:48:51 PM PDT 24 |
360035096 ps |
| T1002 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3151606899 |
|
|
Jul 20 06:48:57 PM PDT 24 |
Jul 20 06:49:00 PM PDT 24 |
22418950 ps |
| T1003 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3621619224 |
|
|
Jul 20 06:48:52 PM PDT 24 |
Jul 20 06:48:55 PM PDT 24 |
162697310 ps |
| T135 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3056865466 |
|
|
Jul 20 06:48:47 PM PDT 24 |
Jul 20 06:48:50 PM PDT 24 |
207172127 ps |
| T1004 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2881547673 |
|
|
Jul 20 06:48:41 PM PDT 24 |
Jul 20 06:48:45 PM PDT 24 |
15254189 ps |