SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
97.99 | 99.19 | 94.27 | 99.72 | 100.00 | 96.03 | 99.12 | 97.62 |
T1005 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1059222737 | Jul 20 06:48:58 PM PDT 24 | Jul 20 06:49:03 PM PDT 24 | 761624612 ps | ||
T1006 | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2782242263 | Jul 20 06:48:39 PM PDT 24 | Jul 20 06:48:42 PM PDT 24 | 23099974 ps | ||
T106 | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2862694770 | Jul 20 06:48:58 PM PDT 24 | Jul 20 06:49:55 PM PDT 24 | 28231706168 ps | ||
T1007 | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2697501938 | Jul 20 06:48:49 PM PDT 24 | Jul 20 06:48:53 PM PDT 24 | 31070777 ps | ||
T1008 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2547226170 | Jul 20 06:48:41 PM PDT 24 | Jul 20 06:48:45 PM PDT 24 | 11790951 ps | ||
T1009 | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.990844671 | Jul 20 06:48:57 PM PDT 24 | Jul 20 06:48:59 PM PDT 24 | 57062507 ps | ||
T1010 | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1288917993 | Jul 20 06:48:40 PM PDT 24 | Jul 20 06:48:44 PM PDT 24 | 77449414 ps | ||
T1011 | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4016437604 | Jul 20 06:48:57 PM PDT 24 | Jul 20 06:49:00 PM PDT 24 | 128106276 ps | ||
T1012 | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.36899094 | Jul 20 06:48:39 PM PDT 24 | Jul 20 06:48:47 PM PDT 24 | 930426638 ps | ||
T1013 | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1858555391 | Jul 20 06:48:57 PM PDT 24 | Jul 20 06:49:01 PM PDT 24 | 232211661 ps | ||
T1014 | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1613716896 | Jul 20 06:48:38 PM PDT 24 | Jul 20 06:48:42 PM PDT 24 | 128269291 ps | ||
T107 | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2907997685 | Jul 20 06:48:59 PM PDT 24 | Jul 20 06:49:50 PM PDT 24 | 7341421191 ps | ||
T1015 | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3279489374 | Jul 20 06:48:49 PM PDT 24 | Jul 20 06:48:51 PM PDT 24 | 13545870 ps | ||
T1016 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1924058991 | Jul 20 06:48:34 PM PDT 24 | Jul 20 06:48:39 PM PDT 24 | 620252465 ps | ||
T1017 | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.798721561 | Jul 20 06:48:40 PM PDT 24 | Jul 20 06:48:44 PM PDT 24 | 20948432 ps | ||
T1018 | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3608911075 | Jul 20 06:48:51 PM PDT 24 | Jul 20 06:48:53 PM PDT 24 | 120230817 ps | ||
T1019 | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.481239555 | Jul 20 06:48:41 PM PDT 24 | Jul 20 06:48:45 PM PDT 24 | 59752457 ps | ||
T1020 | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2669183774 | Jul 20 06:48:57 PM PDT 24 | Jul 20 06:49:00 PM PDT 24 | 448943055 ps | ||
T1021 | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.869732284 | Jul 20 06:48:50 PM PDT 24 | Jul 20 06:48:52 PM PDT 24 | 28657066 ps | ||
T1022 | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4182665679 | Jul 20 06:48:50 PM PDT 24 | Jul 20 06:48:55 PM PDT 24 | 700153212 ps | ||
T130 | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4156251201 | Jul 20 06:48:43 PM PDT 24 | Jul 20 06:48:47 PM PDT 24 | 333727189 ps | ||
T1023 | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3275301156 | Jul 20 06:48:48 PM PDT 24 | Jul 20 06:48:50 PM PDT 24 | 127104304 ps | ||
T1024 | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3181111843 | Jul 20 06:48:57 PM PDT 24 | Jul 20 06:49:00 PM PDT 24 | 12318969 ps | ||
T1025 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3313675575 | Jul 20 06:48:50 PM PDT 24 | Jul 20 06:48:55 PM PDT 24 | 355833116 ps | ||
T1026 | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.711032866 | Jul 20 06:48:49 PM PDT 24 | Jul 20 06:48:51 PM PDT 24 | 46958694 ps | ||
T1027 | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4067857554 | Jul 20 06:48:50 PM PDT 24 | Jul 20 06:48:54 PM PDT 24 | 53595510 ps | ||
T1028 | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4052517621 | Jul 20 06:48:55 PM PDT 24 | Jul 20 06:48:58 PM PDT 24 | 973375719 ps | ||
T1029 | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3376137929 | Jul 20 06:48:52 PM PDT 24 | Jul 20 06:48:57 PM PDT 24 | 134718513 ps | ||
T1030 | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2457757727 | Jul 20 06:48:55 PM PDT 24 | Jul 20 06:49:21 PM PDT 24 | 3823502602 ps | ||
T1031 | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.221637780 | Jul 20 06:48:39 PM PDT 24 | Jul 20 06:48:42 PM PDT 24 | 13167739 ps | ||
T1032 | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.246183099 | Jul 20 06:48:47 PM PDT 24 | Jul 20 06:48:48 PM PDT 24 | 15800237 ps | ||
T1033 | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2517215250 | Jul 20 06:48:57 PM PDT 24 | Jul 20 06:49:51 PM PDT 24 | 28336823595 ps | ||
T1034 | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2861856296 | Jul 20 06:48:41 PM PDT 24 | Jul 20 06:48:49 PM PDT 24 | 140495623 ps | ||
T1035 | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.328428645 | Jul 20 06:48:37 PM PDT 24 | Jul 20 06:48:40 PM PDT 24 | 27264033 ps | ||
T134 | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1492827988 | Jul 20 06:48:40 PM PDT 24 | Jul 20 06:48:46 PM PDT 24 | 183134361 ps |
Test location | /workspace/coverage/default/49.sram_ctrl_lc_escalation.3151069273 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 36824410782 ps |
CPU time | 49.26 seconds |
Started | Jul 20 06:17:42 PM PDT 24 |
Finished | Jul 20 06:18:32 PM PDT 24 |
Peak memory | 211124 kb |
Host | smart-bc06bf59-e92e-445e-8de6-835ea7e7ae89 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151069273 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_lc_es calation.3151069273 |
Directory | /workspace/49.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2004627845 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 1874573646 ps |
CPU time | 53.65 seconds |
Started | Jul 20 06:17:24 PM PDT 24 |
Finished | Jul 20 06:18:18 PM PDT 24 |
Peak memory | 212180 kb |
Host | smart-c0b2d59d-04cc-46bc-8235-285ba44482b5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2004627845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_stress_all_with_rand_reset.2004627845 |
Directory | /workspace/48.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2895449892 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 2939245941 ps |
CPU time | 93.82 seconds |
Started | Jul 20 06:15:40 PM PDT 24 |
Finished | Jul 20 06:17:15 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-781abf05-c306-4dd7-b640-30fd13948a20 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895449892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_mem_partial_access.2895449892 |
Directory | /workspace/36.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_regwen.3939504301 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 19530725111 ps |
CPU time | 753.51 seconds |
Started | Jul 20 06:17:17 PM PDT 24 |
Finished | Jul 20 06:29:51 PM PDT 24 |
Peak memory | 376676 kb |
Host | smart-cacb13af-0c1e-4ae6-9f53-f2b860ec826f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939504301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.3939504301 |
Directory | /workspace/47.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4278883427 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 349460174 ps |
CPU time | 2.38 seconds |
Started | Jul 20 06:48:50 PM PDT 24 |
Finished | Jul 20 06:48:54 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-6d08275e-ad22-4267-af70-2a221ed580bf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278883427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 8.sram_ctrl_tl_intg_err.4278883427 |
Directory | /workspace/8.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3778487318 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 25675542056 ps |
CPU time | 248.47 seconds |
Started | Jul 20 06:16:26 PM PDT 24 |
Finished | Jul 20 06:20:35 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-0de570a3-3345-470e-ae2d-4c6d4060682d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778487318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 43.sram_ctrl_partial_access_b2b.3778487318 |
Directory | /workspace/43.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_sec_cm.1624634570 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 658165479 ps |
CPU time | 3.05 seconds |
Started | Jul 20 06:12:27 PM PDT 24 |
Finished | Jul 20 06:12:31 PM PDT 24 |
Peak memory | 222008 kb |
Host | smart-df370f72-9142-40a1-99fa-014d3f9aafa2 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624634570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_sec_cm.1624634570 |
Directory | /workspace/0.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all.1461183094 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 906851547886 ps |
CPU time | 5180.82 seconds |
Started | Jul 20 06:15:20 PM PDT 24 |
Finished | Jul 20 07:41:41 PM PDT 24 |
Peak memory | 382212 kb |
Host | smart-78da7e6e-ea59-4baa-acef-a805ac3d4763 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461183094 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 34.sram_ctrl_stress_all.1461183094 |
Directory | /workspace/34.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_alert_test.181894987 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 21568319 ps |
CPU time | 0.65 seconds |
Started | Jul 20 06:16:27 PM PDT 24 |
Finished | Jul 20 06:16:29 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-f054eeec-41fd-45ab-b796-f096e1a8e75a |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181894987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_alert_test.181894987 |
Directory | /workspace/42.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.471169024 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 7399950494 ps |
CPU time | 56.25 seconds |
Started | Jul 20 06:48:41 PM PDT 24 |
Finished | Jul 20 06:49:40 PM PDT 24 |
Peak memory | 203532 kb |
Host | smart-e2210520-edad-432d-a915-5c5ba55aaecd |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471169024 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.471169024 |
Directory | /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_ram_cfg.2821239536 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 343926783 ps |
CPU time | 3.19 seconds |
Started | Jul 20 06:13:12 PM PDT 24 |
Finished | Jul 20 06:13:16 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-da63afa8-17a7-416d-aad8-d3780cfba3d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821239536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.2821239536 |
Directory | /workspace/18.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2475876490 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 2842145466 ps |
CPU time | 226.29 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:16:33 PM PDT 24 |
Peak memory | 361448 kb |
Host | smart-6034b659-6e32-477f-8630-c10b1c7a1874 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2475876490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_stress_all_with_rand_reset.2475876490 |
Directory | /workspace/4.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1188589026 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 982531131 ps |
CPU time | 2.45 seconds |
Started | Jul 20 06:48:40 PM PDT 24 |
Finished | Jul 20 06:48:45 PM PDT 24 |
Peak memory | 211472 kb |
Host | smart-f15edf13-0873-4b08-a470-ef0179e38a38 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188589026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.sram_ctrl_tl_intg_err.1188589026 |
Directory | /workspace/0.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_executable.236320970 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 25327934023 ps |
CPU time | 1790.18 seconds |
Started | Jul 20 06:13:21 PM PDT 24 |
Finished | Jul 20 06:43:12 PM PDT 24 |
Peak memory | 379804 kb |
Host | smart-65937f3b-af2a-4033-a591-4a50ce30a744 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236320970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executabl e.236320970 |
Directory | /workspace/18.sram_ctrl_executable/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3056865466 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 207172127 ps |
CPU time | 2.33 seconds |
Started | Jul 20 06:48:47 PM PDT 24 |
Finished | Jul 20 06:48:50 PM PDT 24 |
Peak memory | 203280 kb |
Host | smart-4d627935-d1e5-404c-ac9e-1a9ec68fe068 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056865466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 9.sram_ctrl_tl_intg_err.3056865466 |
Directory | /workspace/9.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all.2666929340 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 985830857795 ps |
CPU time | 5028.19 seconds |
Started | Jul 20 06:16:36 PM PDT 24 |
Finished | Jul 20 07:40:25 PM PDT 24 |
Peak memory | 382844 kb |
Host | smart-7ba40ef4-229a-4aa4-9673-09a768a1b7ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666929340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 43.sram_ctrl_stress_all.2666929340 |
Directory | /workspace/43.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1492827988 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 183134361 ps |
CPU time | 2.31 seconds |
Started | Jul 20 06:48:40 PM PDT 24 |
Finished | Jul 20 06:48:46 PM PDT 24 |
Peak memory | 211468 kb |
Host | smart-572fce4e-e3bf-49c2-938a-45ce8672c784 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492827988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.sram_ctrl_tl_intg_err.1492827988 |
Directory | /workspace/1.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2862694770 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 28231706168 ps |
CPU time | 55.61 seconds |
Started | Jul 20 06:48:58 PM PDT 24 |
Finished | Jul 20 06:49:55 PM PDT 24 |
Peak memory | 203512 kb |
Host | smart-10a6aabc-dd31-47af-8bcd-db53bc2dfbbd |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862694770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.2862694770 |
Directory | /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_multiple_keys.3885761463 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 61109295913 ps |
CPU time | 673.67 seconds |
Started | Jul 20 06:13:00 PM PDT 24 |
Finished | Jul 20 06:24:16 PM PDT 24 |
Peak memory | 382900 kb |
Host | smart-1ae67f64-f2e2-4ddb-9234-e8a94dbf0321 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885761463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multi ple_keys.3885761463 |
Directory | /workspace/15.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_regwen.3654624362 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 85261172989 ps |
CPU time | 904.79 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:27:41 PM PDT 24 |
Peak memory | 379916 kb |
Host | smart-d87b43f6-092e-4590-b267-e25ee82fa767 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654624362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.3654624362 |
Directory | /workspace/2.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_executable.1022726727 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 14345184328 ps |
CPU time | 937.87 seconds |
Started | Jul 20 06:12:24 PM PDT 24 |
Finished | Jul 20 06:28:03 PM PDT 24 |
Peak memory | 375748 kb |
Host | smart-8c4c2511-82cf-438d-bb3e-9e73c698211d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022726727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl e.1022726727 |
Directory | /workspace/0.sram_ctrl_executable/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2279107422 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 22220568 ps |
CPU time | 0.68 seconds |
Started | Jul 20 06:48:34 PM PDT 24 |
Finished | Jul 20 06:48:37 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-2f0171d6-770a-403b-b631-fe375a3eb96f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279107422 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_aliasing.2279107422 |
Directory | /workspace/0.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1924058991 |
Short name | T1016 |
Test name | |
Test status | |
Simulation time | 620252465 ps |
CPU time | 2.3 seconds |
Started | Jul 20 06:48:34 PM PDT 24 |
Finished | Jul 20 06:48:39 PM PDT 24 |
Peak memory | 203256 kb |
Host | smart-f47fd1d0-d009-4760-b2eb-581d157e4b30 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924058991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_bit_bash.1924058991 |
Directory | /workspace/0.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1894502409 |
Short name | T990 |
Test name | |
Test status | |
Simulation time | 19174236 ps |
CPU time | 0.7 seconds |
Started | Jul 20 06:48:37 PM PDT 24 |
Finished | Jul 20 06:48:40 PM PDT 24 |
Peak memory | 203020 kb |
Host | smart-9ff6dc61-e79e-40bf-9634-16b2493181ab |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894502409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 0.sram_ctrl_csr_hw_reset.1894502409 |
Directory | /workspace/0.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3533676044 |
Short name | T957 |
Test name | |
Test status | |
Simulation time | 731924769 ps |
CPU time | 3.7 seconds |
Started | Jul 20 06:48:39 PM PDT 24 |
Finished | Jul 20 06:48:45 PM PDT 24 |
Peak memory | 211472 kb |
Host | smart-f8343212-f3e2-4e6c-9d65-ff28a3225c0e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533676044 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_csr_mem_rw_with_rand_reset.3533676044 |
Directory | /workspace/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.328428645 |
Short name | T1035 |
Test name | |
Test status | |
Simulation time | 27264033 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:48:37 PM PDT 24 |
Finished | Jul 20 06:48:40 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-e51eb883-c149-4724-8b3b-89ff90af575d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328428645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.sram_ctrl_csr_rw.328428645 |
Directory | /workspace/0.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1955215339 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 15397613297 ps |
CPU time | 29.27 seconds |
Started | Jul 20 06:48:37 PM PDT 24 |
Finished | Jul 20 06:49:09 PM PDT 24 |
Peak memory | 203352 kb |
Host | smart-cdc04b5d-9b5f-48c9-b299-7a5de981ccfa |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955215339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.1955215339 |
Directory | /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.558739468 |
Short name | T986 |
Test name | |
Test status | |
Simulation time | 34277668 ps |
CPU time | 0.71 seconds |
Started | Jul 20 06:48:43 PM PDT 24 |
Finished | Jul 20 06:48:46 PM PDT 24 |
Peak memory | 203048 kb |
Host | smart-637b8d85-d4fb-46f7-b75e-1307388329b7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558739468 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.558739468 |
Directory | /workspace/0.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3351559281 |
Short name | T979 |
Test name | |
Test status | |
Simulation time | 77348189 ps |
CPU time | 3.29 seconds |
Started | Jul 20 06:48:37 PM PDT 24 |
Finished | Jul 20 06:48:42 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-e019300b-c68f-4180-ab19-13b825a11619 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351559281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 0.sram_ctrl_tl_errors.3351559281 |
Directory | /workspace/0.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1893845234 |
Short name | T982 |
Test name | |
Test status | |
Simulation time | 50356362 ps |
CPU time | 0.72 seconds |
Started | Jul 20 06:48:40 PM PDT 24 |
Finished | Jul 20 06:48:43 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-72da3f3c-86e0-43fe-9b20-8cd9f4ad87ec |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893845234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_aliasing.1893845234 |
Directory | /workspace/1.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1613716896 |
Short name | T1014 |
Test name | |
Test status | |
Simulation time | 128269291 ps |
CPU time | 1.52 seconds |
Started | Jul 20 06:48:38 PM PDT 24 |
Finished | Jul 20 06:48:42 PM PDT 24 |
Peak memory | 203216 kb |
Host | smart-468718f9-6278-44c7-8777-96ddd13493ea |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613716896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_bit_bash.1613716896 |
Directory | /workspace/1.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2547226170 |
Short name | T1008 |
Test name | |
Test status | |
Simulation time | 11790951 ps |
CPU time | 0.7 seconds |
Started | Jul 20 06:48:41 PM PDT 24 |
Finished | Jul 20 06:48:45 PM PDT 24 |
Peak memory | 202972 kb |
Host | smart-7d506a41-c4c8-4251-b572-3b84e2ea58c1 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547226170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 1.sram_ctrl_csr_hw_reset.2547226170 |
Directory | /workspace/1.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2964479106 |
Short name | T996 |
Test name | |
Test status | |
Simulation time | 764094688 ps |
CPU time | 3.98 seconds |
Started | Jul 20 06:48:41 PM PDT 24 |
Finished | Jul 20 06:48:48 PM PDT 24 |
Peak memory | 212472 kb |
Host | smart-f23ad173-ced7-4c17-9709-41711cd07861 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964479106 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_csr_mem_rw_with_rand_reset.2964479106 |
Directory | /workspace/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1319766285 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 96736154 ps |
CPU time | 0.69 seconds |
Started | Jul 20 06:48:42 PM PDT 24 |
Finished | Jul 20 06:48:45 PM PDT 24 |
Peak memory | 203032 kb |
Host | smart-ef2d884f-3d80-4f09-af20-f595bc040348 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319766285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_csr_rw.1319766285 |
Directory | /workspace/1.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3288126663 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 3768059377 ps |
CPU time | 26.37 seconds |
Started | Jul 20 06:48:41 PM PDT 24 |
Finished | Jul 20 06:49:10 PM PDT 24 |
Peak memory | 203316 kb |
Host | smart-1c8eed9c-de12-4847-babd-1752ed56141a |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288126663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.3288126663 |
Directory | /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.798721561 |
Short name | T1017 |
Test name | |
Test status | |
Simulation time | 20948432 ps |
CPU time | 0.8 seconds |
Started | Jul 20 06:48:40 PM PDT 24 |
Finished | Jul 20 06:48:44 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-2baa4ffb-3a6e-4b26-a8c5-def07a43dfcd |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798721561 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.798721561 |
Directory | /workspace/1.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2937152226 |
Short name | T958 |
Test name | |
Test status | |
Simulation time | 483109696 ps |
CPU time | 4.2 seconds |
Started | Jul 20 06:48:38 PM PDT 24 |
Finished | Jul 20 06:48:44 PM PDT 24 |
Peak memory | 212476 kb |
Host | smart-6d3b15a8-38a3-4b92-9aeb-007010cce22c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937152226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 1.sram_ctrl_tl_errors.2937152226 |
Directory | /workspace/1.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3003012536 |
Short name | T966 |
Test name | |
Test status | |
Simulation time | 364145014 ps |
CPU time | 3 seconds |
Started | Jul 20 06:48:52 PM PDT 24 |
Finished | Jul 20 06:48:56 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-58cc8c9f-40f9-4ae2-8a5c-b6f3fe0582b1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003012536 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_csr_mem_rw_with_rand_reset.3003012536 |
Directory | /workspace/10.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3279489374 |
Short name | T1015 |
Test name | |
Test status | |
Simulation time | 13545870 ps |
CPU time | 0.69 seconds |
Started | Jul 20 06:48:49 PM PDT 24 |
Finished | Jul 20 06:48:51 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-9b24c82b-dc70-4e59-a27e-840899c7e083 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279489374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_csr_rw.3279489374 |
Directory | /workspace/10.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2063842319 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 117569350913 ps |
CPU time | 71.74 seconds |
Started | Jul 20 06:48:47 PM PDT 24 |
Finished | Jul 20 06:49:59 PM PDT 24 |
Peak memory | 203624 kb |
Host | smart-b2eb9e73-1783-4f3c-8add-dcd3b66dae02 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063842319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.2063842319 |
Directory | /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3563458130 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 83526330 ps |
CPU time | 0.8 seconds |
Started | Jul 20 06:48:48 PM PDT 24 |
Finished | Jul 20 06:48:50 PM PDT 24 |
Peak memory | 203028 kb |
Host | smart-cb8a5287-2fe7-4539-9fd4-acd164e22bef |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563458130 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.3563458130 |
Directory | /workspace/10.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3194653515 |
Short name | T969 |
Test name | |
Test status | |
Simulation time | 132495040 ps |
CPU time | 4.66 seconds |
Started | Jul 20 06:48:49 PM PDT 24 |
Finished | Jul 20 06:48:55 PM PDT 24 |
Peak memory | 211504 kb |
Host | smart-f42204b7-7d73-4101-8d97-afe600806364 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194653515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 10.sram_ctrl_tl_errors.3194653515 |
Directory | /workspace/10.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3070262726 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 360035096 ps |
CPU time | 2.54 seconds |
Started | Jul 20 06:48:48 PM PDT 24 |
Finished | Jul 20 06:48:51 PM PDT 24 |
Peak memory | 211480 kb |
Host | smart-b04cf72b-1bce-4734-8eef-dd6e352681e9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070262726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 10.sram_ctrl_tl_intg_err.3070262726 |
Directory | /workspace/10.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1832103943 |
Short name | T945 |
Test name | |
Test status | |
Simulation time | 1352607336 ps |
CPU time | 3.36 seconds |
Started | Jul 20 06:48:49 PM PDT 24 |
Finished | Jul 20 06:48:54 PM PDT 24 |
Peak memory | 203024 kb |
Host | smart-ef95c97b-d39b-463b-b005-ebfe2a967879 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832103943 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_csr_mem_rw_with_rand_reset.1832103943 |
Directory | /workspace/11.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2063202819 |
Short name | T989 |
Test name | |
Test status | |
Simulation time | 47092240 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:48:51 PM PDT 24 |
Finished | Jul 20 06:48:53 PM PDT 24 |
Peak memory | 203012 kb |
Host | smart-4d1a8195-d649-41c2-82b1-fab2d91d701f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063202819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_csr_rw.2063202819 |
Directory | /workspace/11.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.202607070 |
Short name | T1000 |
Test name | |
Test status | |
Simulation time | 4506718556 ps |
CPU time | 26.13 seconds |
Started | Jul 20 06:48:50 PM PDT 24 |
Finished | Jul 20 06:49:17 PM PDT 24 |
Peak memory | 203356 kb |
Host | smart-ace09402-8e3f-4092-b97f-1ddd6a642fa0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202607070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.202607070 |
Directory | /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.97784969 |
Short name | T952 |
Test name | |
Test status | |
Simulation time | 21440231 ps |
CPU time | 0.75 seconds |
Started | Jul 20 06:48:50 PM PDT 24 |
Finished | Jul 20 06:48:53 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-a416101f-979a-4071-80ab-0ed16f4f9ae9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97784969 -assert nopostproc +UVM_TESTNAME=sram_ctr l_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.97784969 |
Directory | /workspace/11.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.892288072 |
Short name | T976 |
Test name | |
Test status | |
Simulation time | 795471674 ps |
CPU time | 2.66 seconds |
Started | Jul 20 06:48:53 PM PDT 24 |
Finished | Jul 20 06:48:57 PM PDT 24 |
Peak memory | 211504 kb |
Host | smart-746a5d0e-554c-4af9-ba43-6d1d8cdbd16d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892288072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_tl_errors.892288072 |
Directory | /workspace/11.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2073293266 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 135988409 ps |
CPU time | 1.4 seconds |
Started | Jul 20 06:48:46 PM PDT 24 |
Finished | Jul 20 06:48:48 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-d70481b5-ff85-462b-bec0-ee09d41e5818 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073293266 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 11.sram_ctrl_tl_intg_err.2073293266 |
Directory | /workspace/11.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.805483916 |
Short name | T965 |
Test name | |
Test status | |
Simulation time | 378129587 ps |
CPU time | 3.79 seconds |
Started | Jul 20 06:48:52 PM PDT 24 |
Finished | Jul 20 06:48:57 PM PDT 24 |
Peak memory | 211592 kb |
Host | smart-294339a6-0152-48e0-b5c0-2ba4ad9d49bf |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805483916 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_csr_mem_rw_with_rand_reset.805483916 |
Directory | /workspace/12.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3466332013 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 45133888 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:48:48 PM PDT 24 |
Finished | Jul 20 06:48:49 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-5f2fab3d-ef16-4c9d-8245-2ca4fc34f690 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466332013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_csr_rw.3466332013 |
Directory | /workspace/12.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.866931269 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 29405944787 ps |
CPU time | 60.96 seconds |
Started | Jul 20 06:48:51 PM PDT 24 |
Finished | Jul 20 06:49:53 PM PDT 24 |
Peak memory | 203568 kb |
Host | smart-6bf4e647-149a-4732-ad88-2a02bc26f8ff |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866931269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.866931269 |
Directory | /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3737215805 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 137656082 ps |
CPU time | 0.71 seconds |
Started | Jul 20 06:48:47 PM PDT 24 |
Finished | Jul 20 06:48:48 PM PDT 24 |
Peak memory | 203028 kb |
Host | smart-097bc55a-d7b7-4028-84e4-7a30206b1f84 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737215805 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.3737215805 |
Directory | /workspace/12.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2697501938 |
Short name | T1007 |
Test name | |
Test status | |
Simulation time | 31070777 ps |
CPU time | 2.85 seconds |
Started | Jul 20 06:48:49 PM PDT 24 |
Finished | Jul 20 06:48:53 PM PDT 24 |
Peak memory | 203252 kb |
Host | smart-9bc7f998-bd3b-44dd-9f80-6f8bb59559f5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697501938 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 12.sram_ctrl_tl_errors.2697501938 |
Directory | /workspace/12.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2672748474 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 146437820 ps |
CPU time | 1.61 seconds |
Started | Jul 20 06:48:49 PM PDT 24 |
Finished | Jul 20 06:48:52 PM PDT 24 |
Peak memory | 211564 kb |
Host | smart-2455e982-4d4c-4f67-9797-ca1b5cbff4ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672748474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 12.sram_ctrl_tl_intg_err.2672748474 |
Directory | /workspace/12.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4182665679 |
Short name | T1022 |
Test name | |
Test status | |
Simulation time | 700153212 ps |
CPU time | 3.55 seconds |
Started | Jul 20 06:48:50 PM PDT 24 |
Finished | Jul 20 06:48:55 PM PDT 24 |
Peak memory | 211280 kb |
Host | smart-3edcf05d-4a0b-482f-87cf-b0fa14508a9f |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182665679 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_csr_mem_rw_with_rand_reset.4182665679 |
Directory | /workspace/13.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.246183099 |
Short name | T1032 |
Test name | |
Test status | |
Simulation time | 15800237 ps |
CPU time | 0.69 seconds |
Started | Jul 20 06:48:47 PM PDT 24 |
Finished | Jul 20 06:48:48 PM PDT 24 |
Peak memory | 202964 kb |
Host | smart-c33e15f7-626d-4ce6-adfc-01d66d92054a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246183099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 13.sram_ctrl_csr_rw.246183099 |
Directory | /workspace/13.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2148083020 |
Short name | T994 |
Test name | |
Test status | |
Simulation time | 7354775737 ps |
CPU time | 53.54 seconds |
Started | Jul 20 06:48:51 PM PDT 24 |
Finished | Jul 20 06:49:46 PM PDT 24 |
Peak memory | 203468 kb |
Host | smart-3ce2b895-b048-4bb4-bb8d-82cb8807e88b |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148083020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.2148083020 |
Directory | /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3275301156 |
Short name | T1023 |
Test name | |
Test status | |
Simulation time | 127104304 ps |
CPU time | 0.72 seconds |
Started | Jul 20 06:48:48 PM PDT 24 |
Finished | Jul 20 06:48:50 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-edae3557-8808-477b-80cd-1c6898104372 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275301156 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.3275301156 |
Directory | /workspace/13.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.742667053 |
Short name | T992 |
Test name | |
Test status | |
Simulation time | 528890829 ps |
CPU time | 5.19 seconds |
Started | Jul 20 06:48:48 PM PDT 24 |
Finished | Jul 20 06:48:54 PM PDT 24 |
Peak memory | 211420 kb |
Host | smart-cd92850a-4274-4c59-a89d-07e7d1f4fea7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742667053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_tl_errors.742667053 |
Directory | /workspace/13.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1432925791 |
Short name | T967 |
Test name | |
Test status | |
Simulation time | 683928462 ps |
CPU time | 3.44 seconds |
Started | Jul 20 06:48:51 PM PDT 24 |
Finished | Jul 20 06:48:56 PM PDT 24 |
Peak memory | 203292 kb |
Host | smart-55759e70-8aa4-4a1b-b0da-c9065e1ce763 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432925791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 13.sram_ctrl_tl_intg_err.1432925791 |
Directory | /workspace/13.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1045651029 |
Short name | T971 |
Test name | |
Test status | |
Simulation time | 1412248980 ps |
CPU time | 4.03 seconds |
Started | Jul 20 06:48:48 PM PDT 24 |
Finished | Jul 20 06:48:53 PM PDT 24 |
Peak memory | 211216 kb |
Host | smart-b69ba88b-f790-429a-8985-dd7cf369b93a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045651029 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_csr_mem_rw_with_rand_reset.1045651029 |
Directory | /workspace/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1594031474 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 10659352 ps |
CPU time | 0.65 seconds |
Started | Jul 20 06:48:52 PM PDT 24 |
Finished | Jul 20 06:48:54 PM PDT 24 |
Peak memory | 203020 kb |
Host | smart-17aca92e-3bcc-4f23-8381-9a4f19d4d016 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594031474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_csr_rw.1594031474 |
Directory | /workspace/14.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1097590126 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 14814679033 ps |
CPU time | 27.3 seconds |
Started | Jul 20 06:48:49 PM PDT 24 |
Finished | Jul 20 06:49:17 PM PDT 24 |
Peak memory | 203348 kb |
Host | smart-c9df1060-b7d3-4ae4-b66e-44d90612e2af |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097590126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.1097590126 |
Directory | /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.697470095 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 40661831 ps |
CPU time | 0.7 seconds |
Started | Jul 20 06:48:48 PM PDT 24 |
Finished | Jul 20 06:48:49 PM PDT 24 |
Peak memory | 203172 kb |
Host | smart-8f2ec488-cc65-4b1a-a12d-2fce7adb804b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697470095 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.697470095 |
Directory | /workspace/14.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3621619224 |
Short name | T1003 |
Test name | |
Test status | |
Simulation time | 162697310 ps |
CPU time | 2.08 seconds |
Started | Jul 20 06:48:52 PM PDT 24 |
Finished | Jul 20 06:48:55 PM PDT 24 |
Peak memory | 203304 kb |
Host | smart-b192b900-c20f-4712-9d8f-e199204dacf7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621619224 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 14.sram_ctrl_tl_errors.3621619224 |
Directory | /workspace/14.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1418393948 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 112936028 ps |
CPU time | 1.54 seconds |
Started | Jul 20 06:48:49 PM PDT 24 |
Finished | Jul 20 06:48:52 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-25dd10d0-6a60-4ebc-98af-ebca4e84767b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418393948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 14.sram_ctrl_tl_intg_err.1418393948 |
Directory | /workspace/14.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1059222737 |
Short name | T1005 |
Test name | |
Test status | |
Simulation time | 761624612 ps |
CPU time | 3.94 seconds |
Started | Jul 20 06:48:58 PM PDT 24 |
Finished | Jul 20 06:49:03 PM PDT 24 |
Peak memory | 211632 kb |
Host | smart-be52700e-5298-4e08-9f4f-7d4cf730821e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059222737 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_csr_mem_rw_with_rand_reset.1059222737 |
Directory | /workspace/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3181111843 |
Short name | T1024 |
Test name | |
Test status | |
Simulation time | 12318969 ps |
CPU time | 0.64 seconds |
Started | Jul 20 06:48:57 PM PDT 24 |
Finished | Jul 20 06:49:00 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-ad8724e8-9678-4437-8159-bb03e9652f8d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181111843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_csr_rw.3181111843 |
Directory | /workspace/15.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2517215250 |
Short name | T1033 |
Test name | |
Test status | |
Simulation time | 28336823595 ps |
CPU time | 52.83 seconds |
Started | Jul 20 06:48:57 PM PDT 24 |
Finished | Jul 20 06:49:51 PM PDT 24 |
Peak memory | 203568 kb |
Host | smart-79a243a4-5079-496f-bd52-021e509e19d5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517215250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.2517215250 |
Directory | /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2277833684 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 49202308 ps |
CPU time | 0.71 seconds |
Started | Jul 20 06:48:59 PM PDT 24 |
Finished | Jul 20 06:49:01 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-ea02c06a-3576-44c8-bd1a-f92656999350 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277833684 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.2277833684 |
Directory | /workspace/15.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.666713077 |
Short name | T948 |
Test name | |
Test status | |
Simulation time | 47204729 ps |
CPU time | 3.7 seconds |
Started | Jul 20 06:48:57 PM PDT 24 |
Finished | Jul 20 06:49:02 PM PDT 24 |
Peak memory | 212888 kb |
Host | smart-58c47849-3979-4b7d-94dd-e99e2170899a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666713077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_tl_errors.666713077 |
Directory | /workspace/15.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4052517621 |
Short name | T1028 |
Test name | |
Test status | |
Simulation time | 973375719 ps |
CPU time | 1.58 seconds |
Started | Jul 20 06:48:55 PM PDT 24 |
Finished | Jul 20 06:48:58 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-2d9ff583-f492-4ae2-a800-ee46e926c358 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052517621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 15.sram_ctrl_tl_intg_err.4052517621 |
Directory | /workspace/15.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3166524960 |
Short name | T949 |
Test name | |
Test status | |
Simulation time | 698163751 ps |
CPU time | 3.13 seconds |
Started | Jul 20 06:48:56 PM PDT 24 |
Finished | Jul 20 06:49:01 PM PDT 24 |
Peak memory | 203024 kb |
Host | smart-8afed76f-49b4-4f89-9aad-d4ec1f09f910 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166524960 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_csr_mem_rw_with_rand_reset.3166524960 |
Directory | /workspace/16.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1056128947 |
Short name | T985 |
Test name | |
Test status | |
Simulation time | 14612604 ps |
CPU time | 0.69 seconds |
Started | Jul 20 06:48:56 PM PDT 24 |
Finished | Jul 20 06:48:58 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-a67bc40a-10a5-46c5-b97c-fc232ebe7390 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056128947 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.sram_ctrl_csr_rw.1056128947 |
Directory | /workspace/16.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.217328933 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 29410978055 ps |
CPU time | 60.63 seconds |
Started | Jul 20 06:48:56 PM PDT 24 |
Finished | Jul 20 06:49:57 PM PDT 24 |
Peak memory | 203520 kb |
Host | smart-1ece577c-0e61-4603-9165-9a7fbaa118eb |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217328933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.217328933 |
Directory | /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.888301775 |
Short name | T953 |
Test name | |
Test status | |
Simulation time | 32703535 ps |
CPU time | 0.71 seconds |
Started | Jul 20 06:49:04 PM PDT 24 |
Finished | Jul 20 06:49:06 PM PDT 24 |
Peak memory | 203060 kb |
Host | smart-c44dbcd0-5bb1-4309-a7f0-849915670640 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888301775 -assert nopostproc +UVM_TESTNAME=sram_ct rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.888301775 |
Directory | /workspace/16.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1922107003 |
Short name | T972 |
Test name | |
Test status | |
Simulation time | 228264678 ps |
CPU time | 2.52 seconds |
Started | Jul 20 06:48:57 PM PDT 24 |
Finished | Jul 20 06:49:02 PM PDT 24 |
Peak memory | 211532 kb |
Host | smart-233f21ce-64eb-4e62-a124-e8cd7cc9eb0b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922107003 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 16.sram_ctrl_tl_errors.1922107003 |
Directory | /workspace/16.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2669183774 |
Short name | T1020 |
Test name | |
Test status | |
Simulation time | 448943055 ps |
CPU time | 1.5 seconds |
Started | Jul 20 06:48:57 PM PDT 24 |
Finished | Jul 20 06:49:00 PM PDT 24 |
Peak memory | 211476 kb |
Host | smart-84665f35-45f5-4369-9992-efc28cb1183e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669183774 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 16.sram_ctrl_tl_intg_err.2669183774 |
Directory | /workspace/16.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3040806114 |
Short name | T947 |
Test name | |
Test status | |
Simulation time | 354172146 ps |
CPU time | 3.34 seconds |
Started | Jul 20 06:49:00 PM PDT 24 |
Finished | Jul 20 06:49:05 PM PDT 24 |
Peak memory | 211260 kb |
Host | smart-6e48148a-d1d5-4fe9-b255-613f439ec023 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040806114 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_csr_mem_rw_with_rand_reset.3040806114 |
Directory | /workspace/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.640183663 |
Short name | T973 |
Test name | |
Test status | |
Simulation time | 21190151 ps |
CPU time | 0.7 seconds |
Started | Jul 20 06:48:58 PM PDT 24 |
Finished | Jul 20 06:49:01 PM PDT 24 |
Peak memory | 203048 kb |
Host | smart-4bb7b398-ae47-4528-8146-a0b94033b970 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640183663 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 17.sram_ctrl_csr_rw.640183663 |
Directory | /workspace/17.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2457757727 |
Short name | T1030 |
Test name | |
Test status | |
Simulation time | 3823502602 ps |
CPU time | 25.5 seconds |
Started | Jul 20 06:48:55 PM PDT 24 |
Finished | Jul 20 06:49:21 PM PDT 24 |
Peak memory | 203380 kb |
Host | smart-c23afbc0-89b8-45a0-9e3b-d58d47b1f2de |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457757727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.2457757727 |
Directory | /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1395910319 |
Short name | T968 |
Test name | |
Test status | |
Simulation time | 23313450 ps |
CPU time | 0.71 seconds |
Started | Jul 20 06:49:00 PM PDT 24 |
Finished | Jul 20 06:49:02 PM PDT 24 |
Peak memory | 203068 kb |
Host | smart-1e070ce2-77c3-41ad-bca8-513c1fcb80c0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395910319 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.1395910319 |
Directory | /workspace/17.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1345899114 |
Short name | T978 |
Test name | |
Test status | |
Simulation time | 56021230 ps |
CPU time | 2.22 seconds |
Started | Jul 20 06:49:02 PM PDT 24 |
Finished | Jul 20 06:49:05 PM PDT 24 |
Peak memory | 203276 kb |
Host | smart-85b1ad30-9163-4492-9470-6effb020cee7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345899114 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 17.sram_ctrl_tl_errors.1345899114 |
Directory | /workspace/17.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4016437604 |
Short name | T1011 |
Test name | |
Test status | |
Simulation time | 128106276 ps |
CPU time | 1.61 seconds |
Started | Jul 20 06:48:57 PM PDT 24 |
Finished | Jul 20 06:49:00 PM PDT 24 |
Peak memory | 203304 kb |
Host | smart-325cba2c-e07b-4b7c-95f5-c4b6e4beafdb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016437604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 17.sram_ctrl_tl_intg_err.4016437604 |
Directory | /workspace/17.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1514172613 |
Short name | T997 |
Test name | |
Test status | |
Simulation time | 1545451478 ps |
CPU time | 3.25 seconds |
Started | Jul 20 06:48:56 PM PDT 24 |
Finished | Jul 20 06:48:59 PM PDT 24 |
Peak memory | 203036 kb |
Host | smart-99862110-9337-49b6-867a-3e6892d77d39 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514172613 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_csr_mem_rw_with_rand_reset.1514172613 |
Directory | /workspace/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.990844671 |
Short name | T1009 |
Test name | |
Test status | |
Simulation time | 57062507 ps |
CPU time | 0.7 seconds |
Started | Jul 20 06:48:57 PM PDT 24 |
Finished | Jul 20 06:48:59 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-37d29db1-e8af-48f1-82ff-58eea49a5201 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990844671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 18.sram_ctrl_csr_rw.990844671 |
Directory | /workspace/18.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3998920190 |
Short name | T999 |
Test name | |
Test status | |
Simulation time | 32818561 ps |
CPU time | 0.73 seconds |
Started | Jul 20 06:49:02 PM PDT 24 |
Finished | Jul 20 06:49:04 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-9736d227-491a-4389-a50b-6ab70d50306a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998920190 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.3998920190 |
Directory | /workspace/18.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3493276487 |
Short name | T961 |
Test name | |
Test status | |
Simulation time | 312029280 ps |
CPU time | 2.81 seconds |
Started | Jul 20 06:48:58 PM PDT 24 |
Finished | Jul 20 06:49:02 PM PDT 24 |
Peak memory | 211424 kb |
Host | smart-9e8505e0-e53c-47ef-9926-9beacb32adcf |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493276487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 18.sram_ctrl_tl_errors.3493276487 |
Directory | /workspace/18.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1858555391 |
Short name | T1013 |
Test name | |
Test status | |
Simulation time | 232211661 ps |
CPU time | 2.54 seconds |
Started | Jul 20 06:48:57 PM PDT 24 |
Finished | Jul 20 06:49:01 PM PDT 24 |
Peak memory | 211476 kb |
Host | smart-671e6fe0-4d4f-49b3-a947-f1f614ae58dd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858555391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 18.sram_ctrl_tl_intg_err.1858555391 |
Directory | /workspace/18.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2217447687 |
Short name | T954 |
Test name | |
Test status | |
Simulation time | 1377701357 ps |
CPU time | 4.21 seconds |
Started | Jul 20 06:48:56 PM PDT 24 |
Finished | Jul 20 06:49:02 PM PDT 24 |
Peak memory | 211416 kb |
Host | smart-cc35c425-ebd8-475d-a5d2-a6f253c81c04 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217447687 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_csr_mem_rw_with_rand_reset.2217447687 |
Directory | /workspace/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2922839930 |
Short name | T983 |
Test name | |
Test status | |
Simulation time | 15492848 ps |
CPU time | 0.67 seconds |
Started | Jul 20 06:48:57 PM PDT 24 |
Finished | Jul 20 06:49:00 PM PDT 24 |
Peak memory | 203096 kb |
Host | smart-4c26e435-c106-4dd4-a509-de6ed1f603be |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922839930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_csr_rw.2922839930 |
Directory | /workspace/19.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2907997685 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 7341421191 ps |
CPU time | 49.57 seconds |
Started | Jul 20 06:48:59 PM PDT 24 |
Finished | Jul 20 06:49:50 PM PDT 24 |
Peak memory | 203600 kb |
Host | smart-7446aa7e-5c44-4730-88ac-765ab22f082e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907997685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.2907997685 |
Directory | /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3151606899 |
Short name | T1002 |
Test name | |
Test status | |
Simulation time | 22418950 ps |
CPU time | 0.82 seconds |
Started | Jul 20 06:48:57 PM PDT 24 |
Finished | Jul 20 06:49:00 PM PDT 24 |
Peak memory | 203036 kb |
Host | smart-0e3c522a-dcad-48da-a733-18d7d90d3124 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151606899 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.3151606899 |
Directory | /workspace/19.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1309153453 |
Short name | T977 |
Test name | |
Test status | |
Simulation time | 452761245 ps |
CPU time | 4.02 seconds |
Started | Jul 20 06:48:59 PM PDT 24 |
Finished | Jul 20 06:49:04 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-d124c15c-2280-4db0-bd79-ebbf50b60f2c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309153453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 19.sram_ctrl_tl_errors.1309153453 |
Directory | /workspace/19.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1307136275 |
Short name | T974 |
Test name | |
Test status | |
Simulation time | 1531132502 ps |
CPU time | 2 seconds |
Started | Jul 20 06:48:58 PM PDT 24 |
Finished | Jul 20 06:49:02 PM PDT 24 |
Peak memory | 203268 kb |
Host | smart-1bf6b897-5d11-454c-a957-28141228713a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307136275 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 19.sram_ctrl_tl_intg_err.1307136275 |
Directory | /workspace/19.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.221637780 |
Short name | T1031 |
Test name | |
Test status | |
Simulation time | 13167739 ps |
CPU time | 0.75 seconds |
Started | Jul 20 06:48:39 PM PDT 24 |
Finished | Jul 20 06:48:42 PM PDT 24 |
Peak memory | 203040 kb |
Host | smart-a818af6d-0d18-4d6c-b839-7be02914a35a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221637780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_aliasing.221637780 |
Directory | /workspace/2.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3132892510 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 29081852 ps |
CPU time | 1.29 seconds |
Started | Jul 20 06:48:38 PM PDT 24 |
Finished | Jul 20 06:48:42 PM PDT 24 |
Peak memory | 203260 kb |
Host | smart-7de7c57d-1a78-4220-867f-77c840603014 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132892510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_bit_bash.3132892510 |
Directory | /workspace/2.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2245662218 |
Short name | T995 |
Test name | |
Test status | |
Simulation time | 45471156 ps |
CPU time | 0.71 seconds |
Started | Jul 20 06:48:39 PM PDT 24 |
Finished | Jul 20 06:48:43 PM PDT 24 |
Peak memory | 203056 kb |
Host | smart-d9884edb-1ae0-46be-a943-f654e924c6df |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245662218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 2.sram_ctrl_csr_hw_reset.2245662218 |
Directory | /workspace/2.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.4127883056 |
Short name | T959 |
Test name | |
Test status | |
Simulation time | 847468919 ps |
CPU time | 4.62 seconds |
Started | Jul 20 06:48:38 PM PDT 24 |
Finished | Jul 20 06:48:45 PM PDT 24 |
Peak memory | 211468 kb |
Host | smart-1eb73ded-beeb-47d4-8d93-574150908a04 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127883056 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_csr_mem_rw_with_rand_reset.4127883056 |
Directory | /workspace/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2091887545 |
Short name | T956 |
Test name | |
Test status | |
Simulation time | 24244560 ps |
CPU time | 0.69 seconds |
Started | Jul 20 06:48:40 PM PDT 24 |
Finished | Jul 20 06:48:44 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-514654c5-90b2-4e8b-bd5a-8d7dd3a2abb5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091887545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_csr_rw.2091887545 |
Directory | /workspace/2.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.591955845 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 15364166433 ps |
CPU time | 28.95 seconds |
Started | Jul 20 06:48:41 PM PDT 24 |
Finished | Jul 20 06:49:13 PM PDT 24 |
Peak memory | 203372 kb |
Host | smart-54d80d1a-6cd5-41af-b520-9a6f0da8f096 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591955845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.591955845 |
Directory | /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2880949753 |
Short name | T1001 |
Test name | |
Test status | |
Simulation time | 21178523 ps |
CPU time | 0.82 seconds |
Started | Jul 20 06:48:42 PM PDT 24 |
Finished | Jul 20 06:48:45 PM PDT 24 |
Peak memory | 203024 kb |
Host | smart-6a41ea02-fdcd-4746-bbaa-58561a7b4497 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880949753 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.2880949753 |
Directory | /workspace/2.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2861856296 |
Short name | T1034 |
Test name | |
Test status | |
Simulation time | 140495623 ps |
CPU time | 4.69 seconds |
Started | Jul 20 06:48:41 PM PDT 24 |
Finished | Jul 20 06:48:49 PM PDT 24 |
Peak memory | 212472 kb |
Host | smart-26fc9502-1cc8-4831-9a8c-a551c3ea34cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861856296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 2.sram_ctrl_tl_errors.2861856296 |
Directory | /workspace/2.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3126889575 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 113663434 ps |
CPU time | 1.55 seconds |
Started | Jul 20 06:48:42 PM PDT 24 |
Finished | Jul 20 06:48:46 PM PDT 24 |
Peak memory | 211472 kb |
Host | smart-244a1db2-c18e-4832-808a-c0084e9a8733 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126889575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.sram_ctrl_tl_intg_err.3126889575 |
Directory | /workspace/2.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.481239555 |
Short name | T1019 |
Test name | |
Test status | |
Simulation time | 59752457 ps |
CPU time | 0.76 seconds |
Started | Jul 20 06:48:41 PM PDT 24 |
Finished | Jul 20 06:48:45 PM PDT 24 |
Peak memory | 203000 kb |
Host | smart-1ca8b60e-3faa-4968-a8a8-f4e32e92d052 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481239555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_aliasing.481239555 |
Directory | /workspace/3.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3792113419 |
Short name | T950 |
Test name | |
Test status | |
Simulation time | 120596714 ps |
CPU time | 2.21 seconds |
Started | Jul 20 06:48:42 PM PDT 24 |
Finished | Jul 20 06:48:47 PM PDT 24 |
Peak memory | 203224 kb |
Host | smart-fcf7407d-ddb6-40c2-ab25-a851f6c69925 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792113419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_bit_bash.3792113419 |
Directory | /workspace/3.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1556001058 |
Short name | T951 |
Test name | |
Test status | |
Simulation time | 32051757 ps |
CPU time | 0.69 seconds |
Started | Jul 20 06:48:38 PM PDT 24 |
Finished | Jul 20 06:48:42 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-f85d0f8a-9505-42f0-a4d6-07a3dc533436 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556001058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 3.sram_ctrl_csr_hw_reset.1556001058 |
Directory | /workspace/3.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2551666471 |
Short name | T944 |
Test name | |
Test status | |
Simulation time | 356194906 ps |
CPU time | 3.71 seconds |
Started | Jul 20 06:48:40 PM PDT 24 |
Finished | Jul 20 06:48:47 PM PDT 24 |
Peak memory | 211288 kb |
Host | smart-0f1ade07-8bb9-4619-a295-35eaf8e99c8b |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551666471 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_csr_mem_rw_with_rand_reset.2551666471 |
Directory | /workspace/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2886314985 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 51416011 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:48:39 PM PDT 24 |
Finished | Jul 20 06:48:42 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-d10ec3b3-62d5-4679-a049-0105c95a7a32 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886314985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_csr_rw.2886314985 |
Directory | /workspace/3.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2881547673 |
Short name | T1004 |
Test name | |
Test status | |
Simulation time | 15254189 ps |
CPU time | 0.71 seconds |
Started | Jul 20 06:48:41 PM PDT 24 |
Finished | Jul 20 06:48:45 PM PDT 24 |
Peak memory | 203036 kb |
Host | smart-38b2ad19-ff5c-44ed-bdb4-96da45a92722 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881547673 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.2881547673 |
Directory | /workspace/3.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2735341360 |
Short name | T987 |
Test name | |
Test status | |
Simulation time | 154600875 ps |
CPU time | 3.31 seconds |
Started | Jul 20 06:48:40 PM PDT 24 |
Finished | Jul 20 06:48:46 PM PDT 24 |
Peak memory | 211508 kb |
Host | smart-59c6d10a-ca85-4f5e-aa06-e5b5389732ea |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735341360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 3.sram_ctrl_tl_errors.2735341360 |
Directory | /workspace/3.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.97153320 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 476377595 ps |
CPU time | 1.66 seconds |
Started | Jul 20 06:48:42 PM PDT 24 |
Finished | Jul 20 06:48:46 PM PDT 24 |
Peak memory | 211432 kb |
Host | smart-7164e78c-12cc-4e38-9471-fd4a3a69cc61 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97153320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_te st +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.sram_ctrl_tl_intg_err.97153320 |
Directory | /workspace/3.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2949754297 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 25632610 ps |
CPU time | 0.71 seconds |
Started | Jul 20 06:48:43 PM PDT 24 |
Finished | Jul 20 06:48:45 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-38b173d2-1c23-40e3-8af3-f661747ec943 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949754297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_aliasing.2949754297 |
Directory | /workspace/4.sram_ctrl_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2605749805 |
Short name | T980 |
Test name | |
Test status | |
Simulation time | 178632343 ps |
CPU time | 2.45 seconds |
Started | Jul 20 06:48:38 PM PDT 24 |
Finished | Jul 20 06:48:43 PM PDT 24 |
Peak memory | 203236 kb |
Host | smart-31de1630-857f-4b81-81fc-16cb8f07c5e6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605749805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_bit_bash.2605749805 |
Directory | /workspace/4.sram_ctrl_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2782242263 |
Short name | T1006 |
Test name | |
Test status | |
Simulation time | 23099974 ps |
CPU time | 0.71 seconds |
Started | Jul 20 06:48:39 PM PDT 24 |
Finished | Jul 20 06:48:42 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-08c58eb8-b2d9-4afa-be2d-2bc31a0dac29 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782242263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul l -cm_name 4.sram_ctrl_csr_hw_reset.2782242263 |
Directory | /workspace/4.sram_ctrl_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4255000751 |
Short name | T943 |
Test name | |
Test status | |
Simulation time | 1463194479 ps |
CPU time | 4.69 seconds |
Started | Jul 20 06:48:40 PM PDT 24 |
Finished | Jul 20 06:48:48 PM PDT 24 |
Peak memory | 217108 kb |
Host | smart-b1fe840b-468b-461c-a0c4-c6618ecfc2fc |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255000751 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_csr_mem_rw_with_rand_reset.4255000751 |
Directory | /workspace/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2482719705 |
Short name | T991 |
Test name | |
Test status | |
Simulation time | 87678920 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:48:43 PM PDT 24 |
Finished | Jul 20 06:48:46 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-a14133d7-12d3-46a1-81de-2fa5ec6065a9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482719705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_csr_rw.2482719705 |
Directory | /workspace/4.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2832296508 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 37016011508 ps |
CPU time | 32.11 seconds |
Started | Jul 20 06:48:38 PM PDT 24 |
Finished | Jul 20 06:49:13 PM PDT 24 |
Peak memory | 203564 kb |
Host | smart-86d2c8ce-e6fb-4191-b619-c114a8acc013 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832296508 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.2832296508 |
Directory | /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1288917993 |
Short name | T1010 |
Test name | |
Test status | |
Simulation time | 77449414 ps |
CPU time | 0.77 seconds |
Started | Jul 20 06:48:40 PM PDT 24 |
Finished | Jul 20 06:48:44 PM PDT 24 |
Peak memory | 203020 kb |
Host | smart-b680f9d1-80ab-4c73-9725-a00d1999e587 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288917993 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.1288917993 |
Directory | /workspace/4.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3535264276 |
Short name | T955 |
Test name | |
Test status | |
Simulation time | 117688702 ps |
CPU time | 2.47 seconds |
Started | Jul 20 06:48:40 PM PDT 24 |
Finished | Jul 20 06:48:46 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-c19aeaf9-a87e-4e0a-b23f-bad20d5c77e1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535264276 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 4.sram_ctrl_tl_errors.3535264276 |
Directory | /workspace/4.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3440858290 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 318835675 ps |
CPU time | 1.65 seconds |
Started | Jul 20 06:48:43 PM PDT 24 |
Finished | Jul 20 06:48:47 PM PDT 24 |
Peak memory | 211440 kb |
Host | smart-f8c8109a-1e8b-439d-b672-522bd8311640 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440858290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.sram_ctrl_tl_intg_err.3440858290 |
Directory | /workspace/4.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.36899094 |
Short name | T1012 |
Test name | |
Test status | |
Simulation time | 930426638 ps |
CPU time | 5.46 seconds |
Started | Jul 20 06:48:39 PM PDT 24 |
Finished | Jul 20 06:48:47 PM PDT 24 |
Peak memory | 213936 kb |
Host | smart-9464d2f1-6b30-4403-af91-066e7bbcb376 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36899094 -asser t nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_csr_mem_rw_with_rand_reset.36899094 |
Directory | /workspace/5.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.945792650 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 35826569 ps |
CPU time | 0.67 seconds |
Started | Jul 20 06:48:42 PM PDT 24 |
Finished | Jul 20 06:48:45 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-e59fc620-f85a-4e07-b805-4b723641dae8 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945792650 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 5.sram_ctrl_csr_rw.945792650 |
Directory | /workspace/5.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.920845046 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 3783531212 ps |
CPU time | 28.85 seconds |
Started | Jul 20 06:48:39 PM PDT 24 |
Finished | Jul 20 06:49:11 PM PDT 24 |
Peak memory | 203296 kb |
Host | smart-378f65db-e46c-482f-9d79-82474350a56e |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920845046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.920845046 |
Directory | /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1535031727 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 28723020 ps |
CPU time | 0.71 seconds |
Started | Jul 20 06:48:39 PM PDT 24 |
Finished | Jul 20 06:48:42 PM PDT 24 |
Peak memory | 203084 kb |
Host | smart-cdb53901-d419-4565-950c-6b75336475c9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535031727 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.1535031727 |
Directory | /workspace/5.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1348132517 |
Short name | T970 |
Test name | |
Test status | |
Simulation time | 732667914 ps |
CPU time | 5.06 seconds |
Started | Jul 20 06:48:40 PM PDT 24 |
Finished | Jul 20 06:48:48 PM PDT 24 |
Peak memory | 211448 kb |
Host | smart-f2e4cc96-1560-4d57-b593-6e29010da712 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348132517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 5.sram_ctrl_tl_errors.1348132517 |
Directory | /workspace/5.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.652000482 |
Short name | T975 |
Test name | |
Test status | |
Simulation time | 376102765 ps |
CPU time | 1.63 seconds |
Started | Jul 20 06:48:38 PM PDT 24 |
Finished | Jul 20 06:48:42 PM PDT 24 |
Peak memory | 211376 kb |
Host | smart-f913e50f-ef3e-4db2-b405-02598112580e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652000482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 5.sram_ctrl_tl_intg_err.652000482 |
Directory | /workspace/5.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4198294081 |
Short name | T984 |
Test name | |
Test status | |
Simulation time | 710553824 ps |
CPU time | 3.32 seconds |
Started | Jul 20 06:48:50 PM PDT 24 |
Finished | Jul 20 06:48:55 PM PDT 24 |
Peak memory | 211320 kb |
Host | smart-81329b0f-4d01-4aef-a612-d019d6be95ef |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198294081 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_csr_mem_rw_with_rand_reset.4198294081 |
Directory | /workspace/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2031260800 |
Short name | T981 |
Test name | |
Test status | |
Simulation time | 47070782 ps |
CPU time | 0.69 seconds |
Started | Jul 20 06:48:41 PM PDT 24 |
Finished | Jul 20 06:48:45 PM PDT 24 |
Peak memory | 203048 kb |
Host | smart-e98abf41-862d-4be5-8195-cbb88cbf31c5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031260800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.sram_ctrl_csr_rw.2031260800 |
Directory | /workspace/6.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3518903940 |
Short name | T962 |
Test name | |
Test status | |
Simulation time | 12389711000 ps |
CPU time | 57.21 seconds |
Started | Jul 20 06:48:40 PM PDT 24 |
Finished | Jul 20 06:49:40 PM PDT 24 |
Peak memory | 203620 kb |
Host | smart-977f1aa1-b87b-4d96-80c2-dcbb9a3d752a |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518903940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.3518903940 |
Directory | /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3212593579 |
Short name | T964 |
Test name | |
Test status | |
Simulation time | 33666304 ps |
CPU time | 0.7 seconds |
Started | Jul 20 06:48:42 PM PDT 24 |
Finished | Jul 20 06:48:45 PM PDT 24 |
Peak memory | 203048 kb |
Host | smart-17ee77ea-eff9-4596-abe3-e5ba15054009 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212593579 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.3212593579 |
Directory | /workspace/6.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4279013161 |
Short name | T942 |
Test name | |
Test status | |
Simulation time | 46137018 ps |
CPU time | 4.13 seconds |
Started | Jul 20 06:48:38 PM PDT 24 |
Finished | Jul 20 06:48:45 PM PDT 24 |
Peak memory | 211460 kb |
Host | smart-87138edf-8f45-43ff-a22f-48ba918176b0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279013161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 6.sram_ctrl_tl_errors.4279013161 |
Directory | /workspace/6.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4156251201 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 333727189 ps |
CPU time | 1.73 seconds |
Started | Jul 20 06:48:43 PM PDT 24 |
Finished | Jul 20 06:48:47 PM PDT 24 |
Peak memory | 203240 kb |
Host | smart-30b0a79c-f7c3-476a-a5b7-dfc8ced1de4f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156251201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 6.sram_ctrl_tl_intg_err.4156251201 |
Directory | /workspace/6.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.504915078 |
Short name | T960 |
Test name | |
Test status | |
Simulation time | 353854877 ps |
CPU time | 3.83 seconds |
Started | Jul 20 06:48:51 PM PDT 24 |
Finished | Jul 20 06:48:56 PM PDT 24 |
Peak memory | 211324 kb |
Host | smart-8409b917-ec5f-4244-a981-154148cc8c8d |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504915078 -asse rt nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_csr_mem_rw_with_rand_reset.504915078 |
Directory | /workspace/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.869732284 |
Short name | T1021 |
Test name | |
Test status | |
Simulation time | 28657066 ps |
CPU time | 0.67 seconds |
Started | Jul 20 06:48:50 PM PDT 24 |
Finished | Jul 20 06:48:52 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-f241fcdc-c6ec-43ed-b6a0-ffa54bdfb188 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869732284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 7.sram_ctrl_csr_rw.869732284 |
Directory | /workspace/7.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2557087036 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 7259768471 ps |
CPU time | 50.78 seconds |
Started | Jul 20 06:48:49 PM PDT 24 |
Finished | Jul 20 06:49:41 PM PDT 24 |
Peak memory | 203520 kb |
Host | smart-beae6072-8c83-41ee-8502-726a03440845 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557087036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.2557087036 |
Directory | /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3084043508 |
Short name | T993 |
Test name | |
Test status | |
Simulation time | 42186545 ps |
CPU time | 0.8 seconds |
Started | Jul 20 06:48:49 PM PDT 24 |
Finished | Jul 20 06:48:52 PM PDT 24 |
Peak memory | 203044 kb |
Host | smart-f643d423-79c5-4c59-b1ed-a27ac4a44aa1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084043508 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.3084043508 |
Directory | /workspace/7.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1849315922 |
Short name | T988 |
Test name | |
Test status | |
Simulation time | 29615293 ps |
CPU time | 2.71 seconds |
Started | Jul 20 06:48:49 PM PDT 24 |
Finished | Jul 20 06:48:54 PM PDT 24 |
Peak memory | 211584 kb |
Host | smart-8e540ec6-6539-4136-ad4f-e61df1f51618 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849315922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 7.sram_ctrl_tl_errors.1849315922 |
Directory | /workspace/7.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4112310038 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 1194452749 ps |
CPU time | 1.69 seconds |
Started | Jul 20 06:48:50 PM PDT 24 |
Finished | Jul 20 06:48:53 PM PDT 24 |
Peak memory | 211472 kb |
Host | smart-560bedf3-905f-4715-8cbd-b854477b1bb4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112310038 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_ test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 7.sram_ctrl_tl_intg_err.4112310038 |
Directory | /workspace/7.sram_ctrl_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2387363652 |
Short name | T946 |
Test name | |
Test status | |
Simulation time | 1109366527 ps |
CPU time | 3.67 seconds |
Started | Jul 20 06:48:53 PM PDT 24 |
Finished | Jul 20 06:48:57 PM PDT 24 |
Peak memory | 211260 kb |
Host | smart-11e42739-cd83-4929-9df2-b9b057db5239 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387363652 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_csr_mem_rw_with_rand_reset.2387363652 |
Directory | /workspace/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.2925013968 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 55931545 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:48:50 PM PDT 24 |
Finished | Jul 20 06:48:52 PM PDT 24 |
Peak memory | 203032 kb |
Host | smart-1f0285a8-6b34-431b-9eba-d074f8e3e15e |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925013968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_csr_rw.2925013968 |
Directory | /workspace/8.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.356496324 |
Short name | T998 |
Test name | |
Test status | |
Simulation time | 15382908534 ps |
CPU time | 29.45 seconds |
Started | Jul 20 06:48:50 PM PDT 24 |
Finished | Jul 20 06:49:21 PM PDT 24 |
Peak memory | 203376 kb |
Host | smart-799df1c6-100b-4b66-a983-1834f73df050 |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356496324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.356496324 |
Directory | /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1621607565 |
Short name | T963 |
Test name | |
Test status | |
Simulation time | 36053744 ps |
CPU time | 0.71 seconds |
Started | Jul 20 06:48:49 PM PDT 24 |
Finished | Jul 20 06:48:50 PM PDT 24 |
Peak memory | 202984 kb |
Host | smart-bea71ad3-77b0-4c40-8344-b60247e6e8b6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621607565 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.1621607565 |
Directory | /workspace/8.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4067857554 |
Short name | T1027 |
Test name | |
Test status | |
Simulation time | 53595510 ps |
CPU time | 2.21 seconds |
Started | Jul 20 06:48:50 PM PDT 24 |
Finished | Jul 20 06:48:54 PM PDT 24 |
Peak memory | 203288 kb |
Host | smart-4941f893-322a-4c51-8042-52d132bc2e39 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067857554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 8.sram_ctrl_tl_errors.4067857554 |
Directory | /workspace/8.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3313675575 |
Short name | T1025 |
Test name | |
Test status | |
Simulation time | 355833116 ps |
CPU time | 3.51 seconds |
Started | Jul 20 06:48:50 PM PDT 24 |
Finished | Jul 20 06:48:55 PM PDT 24 |
Peak memory | 211224 kb |
Host | smart-c035c2c7-8dce-4982-bd0b-57ad2ce1fa0e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313675575 -ass ert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_csr_mem_rw_with_rand_reset.3313675575 |
Directory | /workspace/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.711032866 |
Short name | T1026 |
Test name | |
Test status | |
Simulation time | 46958694 ps |
CPU time | 0.65 seconds |
Started | Jul 20 06:48:49 PM PDT 24 |
Finished | Jul 20 06:48:51 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-151ac66c-5871-4186-a672-1f5f0e71a904 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711032866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 9.sram_ctrl_csr_rw.711032866 |
Directory | /workspace/9.sram_ctrl_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2957700188 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 10871289642 ps |
CPU time | 29.48 seconds |
Started | Jul 20 06:48:48 PM PDT 24 |
Finished | Jul 20 06:49:19 PM PDT 24 |
Peak memory | 203392 kb |
Host | smart-cc09d34f-a51c-404d-a583-9d414a7b57ed |
User | root |
Command | /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957700188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.2957700188 |
Directory | /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3608911075 |
Short name | T1018 |
Test name | |
Test status | |
Simulation time | 120230817 ps |
CPU time | 0.84 seconds |
Started | Jul 20 06:48:51 PM PDT 24 |
Finished | Jul 20 06:48:53 PM PDT 24 |
Peak memory | 203060 kb |
Host | smart-9612866b-f270-4238-bb66-d6e4cf3be0b2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608911075 -assert nopostproc +UVM_TESTNAME=sram_c trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.3608911075 |
Directory | /workspace/9.sram_ctrl_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3376137929 |
Short name | T1029 |
Test name | |
Test status | |
Simulation time | 134718513 ps |
CPU time | 4.66 seconds |
Started | Jul 20 06:48:52 PM PDT 24 |
Finished | Jul 20 06:48:57 PM PDT 24 |
Peak memory | 203272 kb |
Host | smart-76fe2999-fb5f-4cf8-ae9d-b73377707659 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376137929 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam e 9.sram_ctrl_tl_errors.3376137929 |
Directory | /workspace/9.sram_ctrl_tl_errors/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_access_during_key_req.2573189807 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 75338229138 ps |
CPU time | 1149.89 seconds |
Started | Jul 20 06:12:23 PM PDT 24 |
Finished | Jul 20 06:31:33 PM PDT 24 |
Peak memory | 376764 kb |
Host | smart-5a3be76f-d941-4f8f-bae9-c91bbd2ac07b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573189807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.sram_ctrl_access_during_key_req.2573189807 |
Directory | /workspace/0.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_alert_test.857988870 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 30881675 ps |
CPU time | 0.65 seconds |
Started | Jul 20 06:12:22 PM PDT 24 |
Finished | Jul 20 06:12:23 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-dddf9154-3180-4c96-a855-513e7f204dd3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857988870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_alert_test.857988870 |
Directory | /workspace/0.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_bijection.2913101467 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 108592805529 ps |
CPU time | 1267.65 seconds |
Started | Jul 20 06:12:25 PM PDT 24 |
Finished | Jul 20 06:33:34 PM PDT 24 |
Peak memory | 203344 kb |
Host | smart-9d69d635-8533-4e84-9a83-c1a2ee99feb8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913101467 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection. 2913101467 |
Directory | /workspace/0.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_lc_escalation.1718751470 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 9230064064 ps |
CPU time | 58.36 seconds |
Started | Jul 20 06:12:27 PM PDT 24 |
Finished | Jul 20 06:13:27 PM PDT 24 |
Peak memory | 215852 kb |
Host | smart-28aa840a-4612-4135-80dd-7a62ca0f5fee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718751470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc alation.1718751470 |
Directory | /workspace/0.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_max_throughput.1722385188 |
Short name | T840 |
Test name | |
Test status | |
Simulation time | 1281017913 ps |
CPU time | 6.09 seconds |
Started | Jul 20 06:12:31 PM PDT 24 |
Finished | Jul 20 06:12:39 PM PDT 24 |
Peak memory | 202768 kb |
Host | smart-8d30556f-ca7e-4eb2-93c1-f43a11da5490 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722385188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.sram_ctrl_max_throughput.1722385188 |
Directory | /workspace/0.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1928590483 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 9796939841 ps |
CPU time | 79.63 seconds |
Started | Jul 20 06:12:27 PM PDT 24 |
Finished | Jul 20 06:13:48 PM PDT 24 |
Peak memory | 211068 kb |
Host | smart-0c64c5bb-9aca-4d57-adc4-4960122e5ae3 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928590483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_mem_partial_access.1928590483 |
Directory | /workspace/0.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_mem_walk.79625575 |
Short name | T624 |
Test name | |
Test status | |
Simulation time | 2634352618 ps |
CPU time | 163.72 seconds |
Started | Jul 20 06:12:28 PM PDT 24 |
Finished | Jul 20 06:15:14 PM PDT 24 |
Peak memory | 211888 kb |
Host | smart-81d4e600-08ee-4dc5-bea9-80a959df1b43 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79625575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_m em_walk.79625575 |
Directory | /workspace/0.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_multiple_keys.366371122 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 59326711454 ps |
CPU time | 1038.63 seconds |
Started | Jul 20 06:12:23 PM PDT 24 |
Finished | Jul 20 06:29:43 PM PDT 24 |
Peak memory | 375732 kb |
Host | smart-d695ccc2-aa90-42de-b4cb-f26b0d6b2f1a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366371122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multipl e_keys.366371122 |
Directory | /workspace/0.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access.3318241585 |
Short name | T618 |
Test name | |
Test status | |
Simulation time | 1264319494 ps |
CPU time | 20.4 seconds |
Started | Jul 20 06:12:22 PM PDT 24 |
Finished | Jul 20 06:12:43 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-8634da21-9981-421e-a735-a3d2a524867c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318241585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s ram_ctrl_partial_access.3318241585 |
Directory | /workspace/0.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3885688862 |
Short name | T867 |
Test name | |
Test status | |
Simulation time | 9825401978 ps |
CPU time | 288.77 seconds |
Started | Jul 20 06:12:27 PM PDT 24 |
Finished | Jul 20 06:17:17 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-0c5a4806-0dcb-42da-bb5a-cc93f93a6038 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885688862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_partial_access_b2b.3885688862 |
Directory | /workspace/0.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_ram_cfg.1129407156 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 2249894531 ps |
CPU time | 4.2 seconds |
Started | Jul 20 06:12:29 PM PDT 24 |
Finished | Jul 20 06:12:34 PM PDT 24 |
Peak memory | 202992 kb |
Host | smart-62c3470b-a492-470d-a172-ab0094e9da6d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129407156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.1129407156 |
Directory | /workspace/0.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_regwen.138784644 |
Short name | T912 |
Test name | |
Test status | |
Simulation time | 1098095837 ps |
CPU time | 303.25 seconds |
Started | Jul 20 06:12:26 PM PDT 24 |
Finished | Jul 20 06:17:31 PM PDT 24 |
Peak memory | 375684 kb |
Host | smart-638c25b6-372d-4c6e-8945-107cea97cc16 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138784644 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.138784644 |
Directory | /workspace/0.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_smoke.2689197974 |
Short name | T931 |
Test name | |
Test status | |
Simulation time | 1987794923 ps |
CPU time | 21.35 seconds |
Started | Jul 20 06:12:31 PM PDT 24 |
Finished | Jul 20 06:12:54 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-16d585ca-bce5-4fc1-9b88-f9d0a8cb8956 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689197974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.2689197974 |
Directory | /workspace/0.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_all.810094035 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 25015048847 ps |
CPU time | 2514.85 seconds |
Started | Jul 20 06:12:25 PM PDT 24 |
Finished | Jul 20 06:54:21 PM PDT 24 |
Peak memory | 362356 kb |
Host | smart-02cc3dd6-cfa4-460e-b197-ee537dc67425 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810094035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.sram_ctrl_stress_all.810094035 |
Directory | /workspace/0.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2216865095 |
Short name | T856 |
Test name | |
Test status | |
Simulation time | 3086021304 ps |
CPU time | 219.81 seconds |
Started | Jul 20 06:12:26 PM PDT 24 |
Finished | Jul 20 06:16:08 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-7dcadd39-0d72-4242-8af4-ac43918a1c17 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216865095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .sram_ctrl_stress_pipeline.2216865095 |
Directory | /workspace/0.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2945456913 |
Short name | T834 |
Test name | |
Test status | |
Simulation time | 2130255036 ps |
CPU time | 46.74 seconds |
Started | Jul 20 06:12:25 PM PDT 24 |
Finished | Jul 20 06:13:13 PM PDT 24 |
Peak memory | 315336 kb |
Host | smart-a4865d1e-89c6-4135-90ef-1ee55939fcca |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945456913 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.2945456913 |
Directory | /workspace/0.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_access_during_key_req.3657839506 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 41817116219 ps |
CPU time | 1442.9 seconds |
Started | Jul 20 06:12:35 PM PDT 24 |
Finished | Jul 20 06:36:40 PM PDT 24 |
Peak memory | 375388 kb |
Host | smart-d163c851-9de6-46fc-a7fb-40b53fbcee23 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657839506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.sram_ctrl_access_during_key_req.3657839506 |
Directory | /workspace/1.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_alert_test.3139613410 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 14586262 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:12:39 PM PDT 24 |
Peak memory | 202644 kb |
Host | smart-e6021eba-e915-4550-805d-7512bd1d699f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139613410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_alert_test.3139613410 |
Directory | /workspace/1.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_bijection.461136885 |
Short name | T761 |
Test name | |
Test status | |
Simulation time | 96253721861 ps |
CPU time | 1629.81 seconds |
Started | Jul 20 06:12:26 PM PDT 24 |
Finished | Jul 20 06:39:38 PM PDT 24 |
Peak memory | 203652 kb |
Host | smart-5cafb66a-27fd-4082-a891-864b692ddbda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461136885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.461136885 |
Directory | /workspace/1.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_executable.1946900326 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 13703430023 ps |
CPU time | 773.41 seconds |
Started | Jul 20 06:12:35 PM PDT 24 |
Finished | Jul 20 06:25:30 PM PDT 24 |
Peak memory | 377768 kb |
Host | smart-44d83eac-1ba6-4c0d-b438-dbb1c05b40b2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946900326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl e.1946900326 |
Directory | /workspace/1.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_lc_escalation.1005253604 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 14432694281 ps |
CPU time | 21.1 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:12:57 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-054c717a-b207-4613-a987-6a282f92515e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005253604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc alation.1005253604 |
Directory | /workspace/1.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_max_throughput.1908517670 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 1387001221 ps |
CPU time | 15.66 seconds |
Started | Jul 20 06:12:33 PM PDT 24 |
Finished | Jul 20 06:12:50 PM PDT 24 |
Peak memory | 244460 kb |
Host | smart-a76cdf9a-b95a-4315-bc3d-1057425cf009 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908517670 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_max_throughput.1908517670 |
Directory | /workspace/1.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1149661809 |
Short name | T831 |
Test name | |
Test status | |
Simulation time | 2982422950 ps |
CPU time | 90.76 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:14:07 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-61592c16-2a0c-4847-a1ae-151331a349ee |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149661809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_mem_partial_access.1149661809 |
Directory | /workspace/1.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_mem_walk.3760111500 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 13806800113 ps |
CPU time | 168.53 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:15:24 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-fc0000ce-da7c-4792-beb2-733a707675ac |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760111500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl _mem_walk.3760111500 |
Directory | /workspace/1.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_multiple_keys.4234680310 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 4156664028 ps |
CPU time | 645.21 seconds |
Started | Jul 20 06:12:23 PM PDT 24 |
Finished | Jul 20 06:23:09 PM PDT 24 |
Peak memory | 373676 kb |
Host | smart-0792571d-61cd-4d3d-8178-4495325bb155 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234680310 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip le_keys.4234680310 |
Directory | /workspace/1.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access.403363473 |
Short name | T668 |
Test name | |
Test status | |
Simulation time | 3903712840 ps |
CPU time | 136.89 seconds |
Started | Jul 20 06:12:37 PM PDT 24 |
Finished | Jul 20 06:14:55 PM PDT 24 |
Peak memory | 366432 kb |
Host | smart-b866598e-9486-466c-8d63-73fe56100fc4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403363473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sr am_ctrl_partial_access.403363473 |
Directory | /workspace/1.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1666554462 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 16141043432 ps |
CPU time | 241.49 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:16:37 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-0c5acf52-f2c3-4c34-aed1-e83660b0afb6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666554462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.sram_ctrl_partial_access_b2b.1666554462 |
Directory | /workspace/1.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_ram_cfg.420006541 |
Short name | T939 |
Test name | |
Test status | |
Simulation time | 1542234644 ps |
CPU time | 3.39 seconds |
Started | Jul 20 06:12:35 PM PDT 24 |
Finished | Jul 20 06:12:40 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-9ca55c96-9b69-4fe6-ae01-48c7b82e3b75 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420006541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.420006541 |
Directory | /workspace/1.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_regwen.2148109166 |
Short name | T783 |
Test name | |
Test status | |
Simulation time | 2196252094 ps |
CPU time | 235.28 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:16:31 PM PDT 24 |
Peak memory | 361412 kb |
Host | smart-9b120635-e933-43f7-8a0d-f39dece3a6ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148109166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.2148109166 |
Directory | /workspace/1.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_sec_cm.3250105445 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 116300609 ps |
CPU time | 1.84 seconds |
Started | Jul 20 06:12:31 PM PDT 24 |
Finished | Jul 20 06:12:35 PM PDT 24 |
Peak memory | 222080 kb |
Host | smart-812e6917-8ff2-4f65-9890-b1d41c35cf50 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250105445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_sec_cm.3250105445 |
Directory | /workspace/1.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_smoke.1591377507 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 1053803771 ps |
CPU time | 15.86 seconds |
Started | Jul 20 06:12:28 PM PDT 24 |
Finished | Jul 20 06:12:46 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-8a6ca529-02cb-4235-ab64-7ec48f561050 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591377507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.1591377507 |
Directory | /workspace/1.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all.1232024181 |
Short name | T855 |
Test name | |
Test status | |
Simulation time | 105910745815 ps |
CPU time | 2392.93 seconds |
Started | Jul 20 06:12:37 PM PDT 24 |
Finished | Jul 20 06:52:32 PM PDT 24 |
Peak memory | 381844 kb |
Host | smart-84878791-c03d-4a26-9c5a-7312f382ebec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232024181 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.sram_ctrl_stress_all.1232024181 |
Directory | /workspace/1.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.68090798 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 1502699663 ps |
CPU time | 21.4 seconds |
Started | Jul 20 06:12:33 PM PDT 24 |
Finished | Jul 20 06:12:56 PM PDT 24 |
Peak memory | 211164 kb |
Host | smart-dcdcbf80-ef83-4bb0-aa1e-9a0ce6368c49 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=68090798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_stress_all_with_rand_reset.68090798 |
Directory | /workspace/1.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1928302462 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 9924814266 ps |
CPU time | 390.11 seconds |
Started | Jul 20 06:12:25 PM PDT 24 |
Finished | Jul 20 06:18:56 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-2d386a87-ebd3-4e16-ab2e-4bee042f207e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928302462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .sram_ctrl_stress_pipeline.1928302462 |
Directory | /workspace/1.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.905080067 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 926259306 ps |
CPU time | 19.45 seconds |
Started | Jul 20 06:12:33 PM PDT 24 |
Finished | Jul 20 06:12:54 PM PDT 24 |
Peak memory | 268268 kb |
Host | smart-6cf6caeb-ff78-44d2-9fcf-1ac99fee692e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905080067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.905080067 |
Directory | /workspace/1.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_access_during_key_req.3157375652 |
Short name | T696 |
Test name | |
Test status | |
Simulation time | 3337892654 ps |
CPU time | 185.52 seconds |
Started | Jul 20 06:12:49 PM PDT 24 |
Finished | Jul 20 06:15:56 PM PDT 24 |
Peak memory | 347072 kb |
Host | smart-66b08cdb-7b37-4a33-9d0f-04e359cca016 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157375652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 10.sram_ctrl_access_during_key_req.3157375652 |
Directory | /workspace/10.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_alert_test.1989750163 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 33500500 ps |
CPU time | 0.65 seconds |
Started | Jul 20 06:12:49 PM PDT 24 |
Finished | Jul 20 06:12:51 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-864d7107-f0e4-4748-8588-9e5e5a60f83d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989750163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_alert_test.1989750163 |
Directory | /workspace/10.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_bijection.4051851135 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 260441762522 ps |
CPU time | 1008.84 seconds |
Started | Jul 20 06:12:51 PM PDT 24 |
Finished | Jul 20 06:29:41 PM PDT 24 |
Peak memory | 203492 kb |
Host | smart-47cf1a4a-9057-4c00-b358-22f8c70cb6f0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051851135 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection .4051851135 |
Directory | /workspace/10.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_executable.2570451499 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 33116076209 ps |
CPU time | 1177.54 seconds |
Started | Jul 20 06:12:53 PM PDT 24 |
Finished | Jul 20 06:32:33 PM PDT 24 |
Peak memory | 380840 kb |
Host | smart-544563b7-b13d-4b61-86dd-8e1bff596164 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570451499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab le.2570451499 |
Directory | /workspace/10.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_lc_escalation.1863873543 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 192447411986 ps |
CPU time | 124.88 seconds |
Started | Jul 20 06:12:53 PM PDT 24 |
Finished | Jul 20 06:15:00 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-2f8984b8-c9c5-4e64-9e12-cdd06ac8c2eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863873543 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es calation.1863873543 |
Directory | /workspace/10.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_max_throughput.3417366762 |
Short name | T771 |
Test name | |
Test status | |
Simulation time | 2182460620 ps |
CPU time | 44.26 seconds |
Started | Jul 20 06:12:48 PM PDT 24 |
Finished | Jul 20 06:13:34 PM PDT 24 |
Peak memory | 289908 kb |
Host | smart-eb71f502-ff08-494d-8cce-6dcc7110a0d0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417366762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_max_throughput.3417366762 |
Directory | /workspace/10.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_partial_access.226709045 |
Short name | T876 |
Test name | |
Test status | |
Simulation time | 6107669357 ps |
CPU time | 173.41 seconds |
Started | Jul 20 06:12:52 PM PDT 24 |
Finished | Jul 20 06:15:47 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-b19cb426-0d61-4037-ac0c-f28b92aa441b |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226709045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10 .sram_ctrl_mem_partial_access.226709045 |
Directory | /workspace/10.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_mem_walk.2555468269 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 41423998211 ps |
CPU time | 172.16 seconds |
Started | Jul 20 06:12:55 PM PDT 24 |
Finished | Jul 20 06:15:48 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-141fbebd-789b-49c9-8764-62f51b1ca49d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555468269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr l_mem_walk.2555468269 |
Directory | /workspace/10.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_multiple_keys.3541038110 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 6517524248 ps |
CPU time | 206.51 seconds |
Started | Jul 20 06:12:54 PM PDT 24 |
Finished | Jul 20 06:16:23 PM PDT 24 |
Peak memory | 359248 kb |
Host | smart-4d397504-b922-41a8-a808-7546ca54b47d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541038110 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi ple_keys.3541038110 |
Directory | /workspace/10.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access.2923581878 |
Short name | T789 |
Test name | |
Test status | |
Simulation time | 691410576 ps |
CPU time | 29.99 seconds |
Started | Jul 20 06:12:54 PM PDT 24 |
Finished | Jul 20 06:13:26 PM PDT 24 |
Peak memory | 280356 kb |
Host | smart-818c0143-023a-417f-a6b4-60ba30beac11 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923581878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10. sram_ctrl_partial_access.2923581878 |
Directory | /workspace/10.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1773151057 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 14859878289 ps |
CPU time | 483.62 seconds |
Started | Jul 20 06:12:53 PM PDT 24 |
Finished | Jul 20 06:20:58 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-eac56691-6121-4151-aa3a-4c878fa9b1bf |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773151057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 10.sram_ctrl_partial_access_b2b.1773151057 |
Directory | /workspace/10.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_ram_cfg.2527736000 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 696686954 ps |
CPU time | 3.08 seconds |
Started | Jul 20 06:12:52 PM PDT 24 |
Finished | Jul 20 06:12:57 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-8cba9c18-4c90-4d61-8293-4f668b89ec4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527736000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.2527736000 |
Directory | /workspace/10.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_regwen.277992183 |
Short name | T590 |
Test name | |
Test status | |
Simulation time | 98960461768 ps |
CPU time | 919.92 seconds |
Started | Jul 20 06:12:54 PM PDT 24 |
Finished | Jul 20 06:28:16 PM PDT 24 |
Peak memory | 378724 kb |
Host | smart-eeb65b29-9c5b-415d-b8c1-1dcb3c6515d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277992183 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.277992183 |
Directory | /workspace/10.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_smoke.2883593763 |
Short name | T811 |
Test name | |
Test status | |
Simulation time | 6849332631 ps |
CPU time | 101.25 seconds |
Started | Jul 20 06:12:53 PM PDT 24 |
Finished | Jul 20 06:14:36 PM PDT 24 |
Peak memory | 340908 kb |
Host | smart-d4d2d394-5581-4a9b-8aea-e5bc5a193011 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883593763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.2883593763 |
Directory | /workspace/10.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all.4077026213 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 43301957759 ps |
CPU time | 1760.62 seconds |
Started | Jul 20 06:13:04 PM PDT 24 |
Finished | Jul 20 06:42:26 PM PDT 24 |
Peak memory | 380276 kb |
Host | smart-31cf650a-2d35-49dc-9ba3-4ae13c6b24a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077026213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.sram_ctrl_stress_all.4077026213 |
Directory | /workspace/10.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2496802199 |
Short name | T682 |
Test name | |
Test status | |
Simulation time | 1450306870 ps |
CPU time | 113.42 seconds |
Started | Jul 20 06:12:51 PM PDT 24 |
Finished | Jul 20 06:14:46 PM PDT 24 |
Peak memory | 374420 kb |
Host | smart-d8c8ecf4-5d66-47a0-8d98-41618ebd90fb |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2496802199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_stress_all_with_rand_reset.2496802199 |
Directory | /workspace/10.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2259838653 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 5143157282 ps |
CPU time | 308.96 seconds |
Started | Jul 20 06:12:52 PM PDT 24 |
Finished | Jul 20 06:18:02 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-a0bb5cd6-85d5-442d-ae5e-1707e9456f39 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259838653 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.sram_ctrl_stress_pipeline.2259838653 |
Directory | /workspace/10.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.139570301 |
Short name | T859 |
Test name | |
Test status | |
Simulation time | 779414319 ps |
CPU time | 41.7 seconds |
Started | Jul 20 06:12:52 PM PDT 24 |
Finished | Jul 20 06:13:36 PM PDT 24 |
Peak memory | 310080 kb |
Host | smart-ee0aa845-92b8-4361-ab9a-e5cf7485deba |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139570301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 10.sram_ctrl_throughput_w_partial_write.139570301 |
Directory | /workspace/10.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3790510718 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 73191965441 ps |
CPU time | 1224.23 seconds |
Started | Jul 20 06:12:51 PM PDT 24 |
Finished | Jul 20 06:33:16 PM PDT 24 |
Peak memory | 377704 kb |
Host | smart-cf81dff3-0760-4e00-a4f5-576b82e2c700 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790510718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 11.sram_ctrl_access_during_key_req.3790510718 |
Directory | /workspace/11.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_alert_test.290456088 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 29187473 ps |
CPU time | 0.61 seconds |
Started | Jul 20 06:12:53 PM PDT 24 |
Finished | Jul 20 06:12:55 PM PDT 24 |
Peak memory | 202492 kb |
Host | smart-ec1c4707-19a0-4a69-8301-a64f4ef65c0b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290456088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_alert_test.290456088 |
Directory | /workspace/11.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_bijection.3103388870 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 195928124489 ps |
CPU time | 2945.39 seconds |
Started | Jul 20 06:12:54 PM PDT 24 |
Finished | Jul 20 07:02:01 PM PDT 24 |
Peak memory | 203556 kb |
Host | smart-acb1f822-892e-4f4c-8026-73c198cf9434 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103388870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection .3103388870 |
Directory | /workspace/11.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_executable.2894222201 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 15487026042 ps |
CPU time | 346.68 seconds |
Started | Jul 20 06:12:53 PM PDT 24 |
Finished | Jul 20 06:18:42 PM PDT 24 |
Peak memory | 376704 kb |
Host | smart-7dd0736a-7f31-429a-9e8f-59f1e5e55668 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894222201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab le.2894222201 |
Directory | /workspace/11.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_lc_escalation.205905066 |
Short name | T723 |
Test name | |
Test status | |
Simulation time | 48322193166 ps |
CPU time | 47.29 seconds |
Started | Jul 20 06:12:52 PM PDT 24 |
Finished | Jul 20 06:13:41 PM PDT 24 |
Peak memory | 211232 kb |
Host | smart-6239a5f7-2d94-4044-8824-16b29ac5a0d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205905066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_esc alation.205905066 |
Directory | /workspace/11.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_max_throughput.3281488470 |
Short name | T868 |
Test name | |
Test status | |
Simulation time | 689108566 ps |
CPU time | 9.81 seconds |
Started | Jul 20 06:12:53 PM PDT 24 |
Finished | Jul 20 06:13:04 PM PDT 24 |
Peak memory | 225504 kb |
Host | smart-8560c587-e3bc-4810-8781-21dd3c535f2a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281488470 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_max_throughput.3281488470 |
Directory | /workspace/11.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3903235397 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 9771749581 ps |
CPU time | 145.44 seconds |
Started | Jul 20 06:12:50 PM PDT 24 |
Finished | Jul 20 06:15:17 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-23ebccbf-2dc8-4bea-a8e0-de7e87285119 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903235397 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_mem_partial_access.3903235397 |
Directory | /workspace/11.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_mem_walk.3478891065 |
Short name | T589 |
Test name | |
Test status | |
Simulation time | 18704253102 ps |
CPU time | 342.02 seconds |
Started | Jul 20 06:12:53 PM PDT 24 |
Finished | Jul 20 06:18:37 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-a3899804-9d85-47b0-8302-57f01ce05249 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478891065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr l_mem_walk.3478891065 |
Directory | /workspace/11.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_multiple_keys.1605238831 |
Short name | T751 |
Test name | |
Test status | |
Simulation time | 22050886087 ps |
CPU time | 1720.57 seconds |
Started | Jul 20 06:12:53 PM PDT 24 |
Finished | Jul 20 06:41:36 PM PDT 24 |
Peak memory | 380796 kb |
Host | smart-89f6b032-b06a-4eff-9b5a-b70310cdd5e0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605238831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi ple_keys.1605238831 |
Directory | /workspace/11.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access.3693229991 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 3575760255 ps |
CPU time | 8.19 seconds |
Started | Jul 20 06:12:49 PM PDT 24 |
Finished | Jul 20 06:12:59 PM PDT 24 |
Peak memory | 225128 kb |
Host | smart-76a5cefa-c4ec-4050-8c4d-93d664f747d3 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693229991 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11. sram_ctrl_partial_access.3693229991 |
Directory | /workspace/11.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3932501424 |
Short name | T885 |
Test name | |
Test status | |
Simulation time | 202016530416 ps |
CPU time | 571.84 seconds |
Started | Jul 20 06:13:03 PM PDT 24 |
Finished | Jul 20 06:22:36 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-d5d82933-c184-4536-b9e9-6460ef9a95cc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932501424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 11.sram_ctrl_partial_access_b2b.3932501424 |
Directory | /workspace/11.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_ram_cfg.4259503667 |
Short name | T586 |
Test name | |
Test status | |
Simulation time | 1357581133 ps |
CPU time | 3.66 seconds |
Started | Jul 20 06:12:53 PM PDT 24 |
Finished | Jul 20 06:12:59 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-9fb4a017-f02e-4f1b-97ea-f53732b15285 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259503667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.4259503667 |
Directory | /workspace/11.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_regwen.2166605515 |
Short name | T587 |
Test name | |
Test status | |
Simulation time | 47818265235 ps |
CPU time | 1134.69 seconds |
Started | Jul 20 06:12:55 PM PDT 24 |
Finished | Jul 20 06:31:51 PM PDT 24 |
Peak memory | 377712 kb |
Host | smart-b67b3440-17e0-44c4-8e83-54fa659f3a73 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166605515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.2166605515 |
Directory | /workspace/11.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_smoke.3295614037 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 1574590155 ps |
CPU time | 19.06 seconds |
Started | Jul 20 06:12:56 PM PDT 24 |
Finished | Jul 20 06:13:16 PM PDT 24 |
Peak memory | 256712 kb |
Host | smart-e20782f7-248f-437e-88e7-f0be6eea7f8a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295614037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.3295614037 |
Directory | /workspace/11.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all.2146479166 |
Short name | T635 |
Test name | |
Test status | |
Simulation time | 148148673610 ps |
CPU time | 4022.57 seconds |
Started | Jul 20 06:12:55 PM PDT 24 |
Finished | Jul 20 07:20:00 PM PDT 24 |
Peak memory | 381908 kb |
Host | smart-5b088061-6cc5-4055-a5fc-f5ac45c66f36 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146479166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.sram_ctrl_stress_all.2146479166 |
Directory | /workspace/11.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1519467856 |
Short name | T852 |
Test name | |
Test status | |
Simulation time | 1164044885 ps |
CPU time | 46.44 seconds |
Started | Jul 20 06:12:53 PM PDT 24 |
Finished | Jul 20 06:13:42 PM PDT 24 |
Peak memory | 287708 kb |
Host | smart-2c0a7072-e8f7-4f9d-90dc-7050eaa9e9b8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1519467856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_stress_all_with_rand_reset.1519467856 |
Directory | /workspace/11.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1259357490 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 21628234293 ps |
CPU time | 296.66 seconds |
Started | Jul 20 06:12:54 PM PDT 24 |
Finished | Jul 20 06:17:53 PM PDT 24 |
Peak memory | 202848 kb |
Host | smart-0d78e508-6ecd-49ca-bc96-6369bdc49bdf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259357490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.sram_ctrl_stress_pipeline.1259357490 |
Directory | /workspace/11.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.597373536 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 1396217255 ps |
CPU time | 8.62 seconds |
Started | Jul 20 06:12:52 PM PDT 24 |
Finished | Jul 20 06:13:02 PM PDT 24 |
Peak memory | 220708 kb |
Host | smart-b6e75d1b-33b7-4718-ae37-8d5e1d83f2b2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597373536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 11.sram_ctrl_throughput_w_partial_write.597373536 |
Directory | /workspace/11.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_access_during_key_req.1850497013 |
Short name | T754 |
Test name | |
Test status | |
Simulation time | 14590983975 ps |
CPU time | 388.32 seconds |
Started | Jul 20 06:12:54 PM PDT 24 |
Finished | Jul 20 06:19:25 PM PDT 24 |
Peak memory | 352356 kb |
Host | smart-791ef420-c9bc-4932-8370-d7b6aa905280 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850497013 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 12.sram_ctrl_access_during_key_req.1850497013 |
Directory | /workspace/12.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_alert_test.339552140 |
Short name | T698 |
Test name | |
Test status | |
Simulation time | 83811697 ps |
CPU time | 0.7 seconds |
Started | Jul 20 06:12:53 PM PDT 24 |
Finished | Jul 20 06:12:56 PM PDT 24 |
Peak memory | 202440 kb |
Host | smart-150040fd-e2fb-400e-8e6b-5b07d1ae4738 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339552140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_alert_test.339552140 |
Directory | /workspace/12.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_bijection.327105359 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 84367864176 ps |
CPU time | 1163.93 seconds |
Started | Jul 20 06:13:00 PM PDT 24 |
Finished | Jul 20 06:32:26 PM PDT 24 |
Peak memory | 203532 kb |
Host | smart-ddc8c66c-4e0d-47aa-9f74-c74a3d1a6aa0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327105359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection. 327105359 |
Directory | /workspace/12.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_executable.1789499262 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 15867832410 ps |
CPU time | 405.67 seconds |
Started | Jul 20 06:13:00 PM PDT 24 |
Finished | Jul 20 06:19:48 PM PDT 24 |
Peak memory | 356300 kb |
Host | smart-5983bb5f-61a2-48e1-ba4b-74df714bf082 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789499262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab le.1789499262 |
Directory | /workspace/12.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_lc_escalation.1036602271 |
Short name | T601 |
Test name | |
Test status | |
Simulation time | 49227985607 ps |
CPU time | 75.31 seconds |
Started | Jul 20 06:12:55 PM PDT 24 |
Finished | Jul 20 06:14:12 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-8b90fa7d-6cd2-46af-96f0-0966a849833e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036602271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_es calation.1036602271 |
Directory | /workspace/12.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_max_throughput.4026197471 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 736870663 ps |
CPU time | 40.48 seconds |
Started | Jul 20 06:12:54 PM PDT 24 |
Finished | Jul 20 06:13:37 PM PDT 24 |
Peak memory | 300988 kb |
Host | smart-59d7865b-519f-4c4b-8ca4-033bf3fe7a19 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026197471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 12.sram_ctrl_max_throughput.4026197471 |
Directory | /workspace/12.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3387127731 |
Short name | T854 |
Test name | |
Test status | |
Simulation time | 8748355908 ps |
CPU time | 79.95 seconds |
Started | Jul 20 06:12:52 PM PDT 24 |
Finished | Jul 20 06:14:14 PM PDT 24 |
Peak memory | 219424 kb |
Host | smart-2ccd8414-8875-4f52-b95c-d437ed9410b8 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387127731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_mem_partial_access.3387127731 |
Directory | /workspace/12.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_mem_walk.3254903168 |
Short name | T935 |
Test name | |
Test status | |
Simulation time | 18309709030 ps |
CPU time | 334.51 seconds |
Started | Jul 20 06:12:50 PM PDT 24 |
Finished | Jul 20 06:18:26 PM PDT 24 |
Peak memory | 211204 kb |
Host | smart-99ed937d-0f91-4848-b936-7c5dffc8f782 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254903168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctr l_mem_walk.3254903168 |
Directory | /workspace/12.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_multiple_keys.133428573 |
Short name | T888 |
Test name | |
Test status | |
Simulation time | 31730488406 ps |
CPU time | 707.03 seconds |
Started | Jul 20 06:12:52 PM PDT 24 |
Finished | Jul 20 06:24:40 PM PDT 24 |
Peak memory | 365464 kb |
Host | smart-9c07c09c-d0a7-4208-94cf-6b77dd92cc0c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133428573 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multip le_keys.133428573 |
Directory | /workspace/12.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access.2350027329 |
Short name | T758 |
Test name | |
Test status | |
Simulation time | 2126644191 ps |
CPU time | 13.26 seconds |
Started | Jul 20 06:12:50 PM PDT 24 |
Finished | Jul 20 06:13:05 PM PDT 24 |
Peak memory | 202796 kb |
Host | smart-de8979d0-a8b4-458c-9335-7926dd2629ba |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350027329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12. sram_ctrl_partial_access.2350027329 |
Directory | /workspace/12.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3258871912 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 55363054770 ps |
CPU time | 354.76 seconds |
Started | Jul 20 06:12:50 PM PDT 24 |
Finished | Jul 20 06:18:46 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-4e54c131-aafa-440d-9f4a-1b9d04a625b2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258871912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 12.sram_ctrl_partial_access_b2b.3258871912 |
Directory | /workspace/12.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_ram_cfg.4151926843 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 353925566 ps |
CPU time | 3.37 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 06:13:04 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-97d54a78-233c-494f-ae33-3fd958e737a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151926843 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.4151926843 |
Directory | /workspace/12.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_regwen.1193150157 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 6942528825 ps |
CPU time | 1101.66 seconds |
Started | Jul 20 06:12:52 PM PDT 24 |
Finished | Jul 20 06:31:15 PM PDT 24 |
Peak memory | 378944 kb |
Host | smart-3b0bc4f2-7dcd-4ea3-ad37-4e8d92d1cbdf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193150157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.1193150157 |
Directory | /workspace/12.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_smoke.3700853159 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 5291832238 ps |
CPU time | 145.53 seconds |
Started | Jul 20 06:13:00 PM PDT 24 |
Finished | Jul 20 06:15:28 PM PDT 24 |
Peak memory | 367516 kb |
Host | smart-0cdc6273-380e-4ee9-a658-4795940bd3fc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700853159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.3700853159 |
Directory | /workspace/12.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all.3331672340 |
Short name | T839 |
Test name | |
Test status | |
Simulation time | 39893811519 ps |
CPU time | 5948.21 seconds |
Started | Jul 20 06:12:53 PM PDT 24 |
Finished | Jul 20 07:52:04 PM PDT 24 |
Peak memory | 380912 kb |
Host | smart-f901586d-c5ed-43b2-8fe1-fd2069098475 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331672340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.sram_ctrl_stress_all.3331672340 |
Directory | /workspace/12.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2409682166 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 1289559790 ps |
CPU time | 25.67 seconds |
Started | Jul 20 06:12:54 PM PDT 24 |
Finished | Jul 20 06:13:21 PM PDT 24 |
Peak memory | 211532 kb |
Host | smart-3d40c175-38f9-43a2-8d39-f123065714e4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2409682166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_stress_all_with_rand_reset.2409682166 |
Directory | /workspace/12.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2627597437 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 3291017314 ps |
CPU time | 179.26 seconds |
Started | Jul 20 06:12:55 PM PDT 24 |
Finished | Jul 20 06:15:56 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-0c47ad5f-f153-432c-924f-2212f9a2e6e6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627597437 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.sram_ctrl_stress_pipeline.2627597437 |
Directory | /workspace/12.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.4146426420 |
Short name | T864 |
Test name | |
Test status | |
Simulation time | 795804806 ps |
CPU time | 148.93 seconds |
Started | Jul 20 06:12:52 PM PDT 24 |
Finished | Jul 20 06:15:23 PM PDT 24 |
Peak memory | 370464 kb |
Host | smart-9f383a59-387b-4ad1-ba92-25c55ddbde7c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146426420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.4146426420 |
Directory | /workspace/12.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_access_during_key_req.671673453 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 12585047714 ps |
CPU time | 696.56 seconds |
Started | Jul 20 06:12:58 PM PDT 24 |
Finished | Jul 20 06:24:36 PM PDT 24 |
Peak memory | 380808 kb |
Host | smart-e74ce48a-6c92-41f2-8faa-fc73221a87a9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671673453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 13.sram_ctrl_access_during_key_req.671673453 |
Directory | /workspace/13.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_alert_test.3771562044 |
Short name | T804 |
Test name | |
Test status | |
Simulation time | 32977832 ps |
CPU time | 0.65 seconds |
Started | Jul 20 06:12:57 PM PDT 24 |
Finished | Jul 20 06:12:58 PM PDT 24 |
Peak memory | 202456 kb |
Host | smart-c877e54b-9ca7-47ca-a9a1-e81b28112aa8 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771562044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_alert_test.3771562044 |
Directory | /workspace/13.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_bijection.1171300615 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 96199481602 ps |
CPU time | 2041.52 seconds |
Started | Jul 20 06:13:03 PM PDT 24 |
Finished | Jul 20 06:47:06 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-65dfde91-a5a8-4b80-8725-b0bd8b5a143b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171300615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection .1171300615 |
Directory | /workspace/13.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_executable.1785087701 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 16719983397 ps |
CPU time | 495.76 seconds |
Started | Jul 20 06:13:00 PM PDT 24 |
Finished | Jul 20 06:21:18 PM PDT 24 |
Peak memory | 367600 kb |
Host | smart-336540b3-72d4-4fbb-9ab3-286d19ae7054 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785087701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab le.1785087701 |
Directory | /workspace/13.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_lc_escalation.1591223850 |
Short name | T765 |
Test name | |
Test status | |
Simulation time | 10687288836 ps |
CPU time | 20.11 seconds |
Started | Jul 20 06:13:07 PM PDT 24 |
Finished | Jul 20 06:13:28 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-0e8c2bd0-6139-47ba-86ce-c0f451f8de40 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591223850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_lc_es calation.1591223850 |
Directory | /workspace/13.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_max_throughput.858755778 |
Short name | T649 |
Test name | |
Test status | |
Simulation time | 1398693659 ps |
CPU time | 6.54 seconds |
Started | Jul 20 06:13:04 PM PDT 24 |
Finished | Jul 20 06:13:12 PM PDT 24 |
Peak memory | 211032 kb |
Host | smart-ef6b5ada-0638-4d95-a6ca-ed08dee7ec9b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858755778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.sram_ctrl_max_throughput.858755778 |
Directory | /workspace/13.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1843557876 |
Short name | T838 |
Test name | |
Test status | |
Simulation time | 1620503592 ps |
CPU time | 129.22 seconds |
Started | Jul 20 06:13:00 PM PDT 24 |
Finished | Jul 20 06:15:11 PM PDT 24 |
Peak memory | 219148 kb |
Host | smart-2f8a89bd-9b84-4ca2-8337-7e73de096093 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843557876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_mem_partial_access.1843557876 |
Directory | /workspace/13.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_mem_walk.764588992 |
Short name | T619 |
Test name | |
Test status | |
Simulation time | 49378802984 ps |
CPU time | 168.8 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 06:15:49 PM PDT 24 |
Peak memory | 211824 kb |
Host | smart-9f649cb3-91c5-4c2d-991c-ad6a5c5214fc |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764588992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl _mem_walk.764588992 |
Directory | /workspace/13.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_multiple_keys.850259830 |
Short name | T795 |
Test name | |
Test status | |
Simulation time | 14591920905 ps |
CPU time | 1064.46 seconds |
Started | Jul 20 06:13:04 PM PDT 24 |
Finished | Jul 20 06:30:50 PM PDT 24 |
Peak memory | 380856 kb |
Host | smart-e90abe15-32f0-457c-96d2-f0fa81778181 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850259830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multip le_keys.850259830 |
Directory | /workspace/13.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access.2973605926 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 6586474001 ps |
CPU time | 90.58 seconds |
Started | Jul 20 06:13:04 PM PDT 24 |
Finished | Jul 20 06:14:36 PM PDT 24 |
Peak memory | 336740 kb |
Host | smart-1abf2b7c-3fe8-47b4-b36e-9dd96a0cac8d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973605926 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13. sram_ctrl_partial_access.2973605926 |
Directory | /workspace/13.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1922384141 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 3896312962 ps |
CPU time | 234.71 seconds |
Started | Jul 20 06:13:04 PM PDT 24 |
Finished | Jul 20 06:17:00 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-b07e9b53-5b7e-4fe5-9b4c-358057dcdf06 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922384141 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 13.sram_ctrl_partial_access_b2b.1922384141 |
Directory | /workspace/13.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_ram_cfg.3602037751 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 1300293860 ps |
CPU time | 3.42 seconds |
Started | Jul 20 06:13:03 PM PDT 24 |
Finished | Jul 20 06:13:08 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-8fe98616-1d4d-49b6-bd14-fa1228931317 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602037751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.3602037751 |
Directory | /workspace/13.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_regwen.615317213 |
Short name | T849 |
Test name | |
Test status | |
Simulation time | 15881797187 ps |
CPU time | 574.92 seconds |
Started | Jul 20 06:13:00 PM PDT 24 |
Finished | Jul 20 06:22:37 PM PDT 24 |
Peak memory | 375880 kb |
Host | smart-0a983d95-4c18-4b7d-b613-b7bde817bdd3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615317213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.615317213 |
Directory | /workspace/13.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_smoke.403371265 |
Short name | T926 |
Test name | |
Test status | |
Simulation time | 1038972348 ps |
CPU time | 7.44 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 06:13:08 PM PDT 24 |
Peak memory | 208708 kb |
Host | smart-4793fc7a-597f-4acc-8e07-17327e4d301d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403371265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.403371265 |
Directory | /workspace/13.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all.3485956067 |
Short name | T824 |
Test name | |
Test status | |
Simulation time | 393604884911 ps |
CPU time | 7043.25 seconds |
Started | Jul 20 06:12:56 PM PDT 24 |
Finished | Jul 20 08:10:21 PM PDT 24 |
Peak memory | 380832 kb |
Host | smart-1f849cef-d23b-4029-b8d7-239a0a3bac57 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485956067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.sram_ctrl_stress_all.3485956067 |
Directory | /workspace/13.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3971772559 |
Short name | T642 |
Test name | |
Test status | |
Simulation time | 6833515370 ps |
CPU time | 26.05 seconds |
Started | Jul 20 06:13:01 PM PDT 24 |
Finished | Jul 20 06:13:29 PM PDT 24 |
Peak memory | 211176 kb |
Host | smart-68dffcc5-a51a-4b43-9f89-687d63c30695 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3971772559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_stress_all_with_rand_reset.3971772559 |
Directory | /workspace/13.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1309302630 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 36127413256 ps |
CPU time | 230.85 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 06:16:52 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-6eeb4862-3379-4535-b355-e0b4581b3037 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309302630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 3.sram_ctrl_stress_pipeline.1309302630 |
Directory | /workspace/13.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3679832556 |
Short name | T921 |
Test name | |
Test status | |
Simulation time | 773463708 ps |
CPU time | 78.02 seconds |
Started | Jul 20 06:13:04 PM PDT 24 |
Finished | Jul 20 06:14:23 PM PDT 24 |
Peak memory | 332884 kb |
Host | smart-2c4c678f-2575-4c67-948c-b5e1ee614164 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679832556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.3679832556 |
Directory | /workspace/13.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1651407546 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 2482269235 ps |
CPU time | 318.57 seconds |
Started | Jul 20 06:12:58 PM PDT 24 |
Finished | Jul 20 06:18:17 PM PDT 24 |
Peak memory | 362052 kb |
Host | smart-68807de5-e237-477e-b56e-e6a15e341bc0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651407546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 14.sram_ctrl_access_during_key_req.1651407546 |
Directory | /workspace/14.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_alert_test.723812099 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 23239107 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:13:01 PM PDT 24 |
Finished | Jul 20 06:13:04 PM PDT 24 |
Peak memory | 202480 kb |
Host | smart-0425f822-a456-4c0a-b415-289948085181 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723812099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_alert_test.723812099 |
Directory | /workspace/14.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_bijection.2636356306 |
Short name | T671 |
Test name | |
Test status | |
Simulation time | 24496687429 ps |
CPU time | 540.79 seconds |
Started | Jul 20 06:13:00 PM PDT 24 |
Finished | Jul 20 06:22:03 PM PDT 24 |
Peak memory | 203672 kb |
Host | smart-f6c59a10-a3bd-42f5-8bcc-81c050cac56a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636356306 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection .2636356306 |
Directory | /workspace/14.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_executable.3377649020 |
Short name | T675 |
Test name | |
Test status | |
Simulation time | 286916813972 ps |
CPU time | 1376.54 seconds |
Started | Jul 20 06:13:01 PM PDT 24 |
Finished | Jul 20 06:36:00 PM PDT 24 |
Peak memory | 378748 kb |
Host | smart-52054181-ed9c-4709-8755-ec93cff25e76 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377649020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab le.3377649020 |
Directory | /workspace/14.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_lc_escalation.2577962355 |
Short name | T633 |
Test name | |
Test status | |
Simulation time | 4923998828 ps |
CPU time | 7.41 seconds |
Started | Jul 20 06:13:01 PM PDT 24 |
Finished | Jul 20 06:13:10 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-e259c791-e1ee-475d-9f2c-04178a9f95b8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577962355 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es calation.2577962355 |
Directory | /workspace/14.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_max_throughput.548432520 |
Short name | T780 |
Test name | |
Test status | |
Simulation time | 2896787089 ps |
CPU time | 18.11 seconds |
Started | Jul 20 06:13:01 PM PDT 24 |
Finished | Jul 20 06:13:21 PM PDT 24 |
Peak memory | 252020 kb |
Host | smart-7f15fab0-d320-4c9a-96d2-50905b122adf |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548432520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.sram_ctrl_max_throughput.548432520 |
Directory | /workspace/14.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_partial_access.3245222239 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 12753649633 ps |
CPU time | 91.97 seconds |
Started | Jul 20 06:12:56 PM PDT 24 |
Finished | Jul 20 06:14:29 PM PDT 24 |
Peak memory | 211088 kb |
Host | smart-f770f1e7-7c13-4ab7-ace5-7f97968c08ae |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245222239 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_mem_partial_access.3245222239 |
Directory | /workspace/14.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_mem_walk.1781512127 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 37498405050 ps |
CPU time | 295.98 seconds |
Started | Jul 20 06:12:57 PM PDT 24 |
Finished | Jul 20 06:17:54 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-7f9ccea8-61f0-4f38-b738-2c11194b0fa6 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781512127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr l_mem_walk.1781512127 |
Directory | /workspace/14.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_multiple_keys.3246514506 |
Short name | T652 |
Test name | |
Test status | |
Simulation time | 8478813049 ps |
CPU time | 681.1 seconds |
Started | Jul 20 06:13:01 PM PDT 24 |
Finished | Jul 20 06:24:24 PM PDT 24 |
Peak memory | 377652 kb |
Host | smart-1ffa6765-27cc-4cf9-8c5e-2f5af786ae4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246514506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi ple_keys.3246514506 |
Directory | /workspace/14.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access.45547064 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 5343345468 ps |
CPU time | 8.72 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 06:13:10 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-ea521b33-9134-4b9a-88f3-8a2344e855ba |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45547064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sr am_ctrl_partial_access.45547064 |
Directory | /workspace/14.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2682627703 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 29005944370 ps |
CPU time | 328.16 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 06:18:30 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-8ce8fc66-ad9b-4194-90c8-04d6dd7e61b6 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682627703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 14.sram_ctrl_partial_access_b2b.2682627703 |
Directory | /workspace/14.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_ram_cfg.1017151547 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 1768767320 ps |
CPU time | 3.87 seconds |
Started | Jul 20 06:13:02 PM PDT 24 |
Finished | Jul 20 06:13:07 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-28034373-f990-4d92-93ee-0b32d77d1db7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017151547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.1017151547 |
Directory | /workspace/14.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_regwen.3514382835 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 3774845221 ps |
CPU time | 1554.33 seconds |
Started | Jul 20 06:13:01 PM PDT 24 |
Finished | Jul 20 06:38:58 PM PDT 24 |
Peak memory | 382832 kb |
Host | smart-08c8d928-6ddd-4fd3-ae9c-0826d4f6e173 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514382835 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.3514382835 |
Directory | /workspace/14.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_smoke.1086633610 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 1228468175 ps |
CPU time | 28.7 seconds |
Started | Jul 20 06:13:05 PM PDT 24 |
Finished | Jul 20 06:13:35 PM PDT 24 |
Peak memory | 273368 kb |
Host | smart-6da5b62d-1e8d-41d3-8e6a-056d25af7718 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086633610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.1086633610 |
Directory | /workspace/14.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all.3431757909 |
Short name | T857 |
Test name | |
Test status | |
Simulation time | 390196270573 ps |
CPU time | 5131.24 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 07:38:34 PM PDT 24 |
Peak memory | 381844 kb |
Host | smart-11e5da17-336a-4961-9af9-92cbb14ff81c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431757909 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.sram_ctrl_stress_all.3431757909 |
Directory | /workspace/14.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.542155327 |
Short name | T763 |
Test name | |
Test status | |
Simulation time | 6223471462 ps |
CPU time | 75.64 seconds |
Started | Jul 20 06:13:07 PM PDT 24 |
Finished | Jul 20 06:14:23 PM PDT 24 |
Peak memory | 298444 kb |
Host | smart-adda7ea9-f5dc-4e6c-ab8f-0353592dbd0c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=542155327 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_stress_all_with_rand_reset.542155327 |
Directory | /workspace/14.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2306146340 |
Short name | T661 |
Test name | |
Test status | |
Simulation time | 18420435250 ps |
CPU time | 284.51 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 06:17:46 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-d4a4bc8c-2d89-40f9-8cda-3f5f3c7b7086 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306146340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.sram_ctrl_stress_pipeline.2306146340 |
Directory | /workspace/14.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3203920638 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 4050397886 ps |
CPU time | 128.33 seconds |
Started | Jul 20 06:13:00 PM PDT 24 |
Finished | Jul 20 06:15:11 PM PDT 24 |
Peak memory | 358296 kb |
Host | smart-65158779-9018-4028-bbed-e2569169dc91 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203920638 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3203920638 |
Directory | /workspace/14.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_access_during_key_req.1732772674 |
Short name | T687 |
Test name | |
Test status | |
Simulation time | 13554613464 ps |
CPU time | 844.83 seconds |
Started | Jul 20 06:13:01 PM PDT 24 |
Finished | Jul 20 06:27:08 PM PDT 24 |
Peak memory | 378616 kb |
Host | smart-2efb8faa-8bd9-4d44-b682-9b3cdbcb6a27 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732772674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 15.sram_ctrl_access_during_key_req.1732772674 |
Directory | /workspace/15.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_alert_test.208239353 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 94154967 ps |
CPU time | 0.67 seconds |
Started | Jul 20 06:12:57 PM PDT 24 |
Finished | Jul 20 06:12:59 PM PDT 24 |
Peak memory | 202548 kb |
Host | smart-63599b75-a9db-407b-a676-f20c5f1032f7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208239353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_alert_test.208239353 |
Directory | /workspace/15.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_bijection.3120042771 |
Short name | T593 |
Test name | |
Test status | |
Simulation time | 130715126554 ps |
CPU time | 2158.07 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 06:49:00 PM PDT 24 |
Peak memory | 203744 kb |
Host | smart-726cf750-f1c0-497c-a24c-b648bebfdf8b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120042771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection .3120042771 |
Directory | /workspace/15.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_executable.3471068955 |
Short name | T899 |
Test name | |
Test status | |
Simulation time | 114145696287 ps |
CPU time | 1584.65 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 06:39:25 PM PDT 24 |
Peak memory | 379768 kb |
Host | smart-a2d4a2a4-d04b-4f62-8fa3-b595bcab33a7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471068955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab le.3471068955 |
Directory | /workspace/15.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_lc_escalation.1098193298 |
Short name | T617 |
Test name | |
Test status | |
Simulation time | 44593637624 ps |
CPU time | 71.67 seconds |
Started | Jul 20 06:13:07 PM PDT 24 |
Finished | Jul 20 06:14:20 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-37e839a8-0bb2-495f-a71f-8fdff971b1a5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098193298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es calation.1098193298 |
Directory | /workspace/15.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_max_throughput.474326113 |
Short name | T717 |
Test name | |
Test status | |
Simulation time | 3093430307 ps |
CPU time | 87.36 seconds |
Started | Jul 20 06:13:01 PM PDT 24 |
Finished | Jul 20 06:14:31 PM PDT 24 |
Peak memory | 334524 kb |
Host | smart-55639748-76b8-4326-9433-171ca7c8eaba |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474326113 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.sram_ctrl_max_throughput.474326113 |
Directory | /workspace/15.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1077717621 |
Short name | T654 |
Test name | |
Test status | |
Simulation time | 15763839767 ps |
CPU time | 139.04 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 06:15:20 PM PDT 24 |
Peak memory | 211584 kb |
Host | smart-8a21025d-b79b-4b53-bb8a-d3343bc36e71 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077717621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_mem_partial_access.1077717621 |
Directory | /workspace/15.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_mem_walk.2457051607 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 3953623832 ps |
CPU time | 246.96 seconds |
Started | Jul 20 06:13:04 PM PDT 24 |
Finished | Jul 20 06:17:12 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-4486355a-2657-4eff-a8b8-753d47f435e7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457051607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr l_mem_walk.2457051607 |
Directory | /workspace/15.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access.3672353185 |
Short name | T806 |
Test name | |
Test status | |
Simulation time | 969800274 ps |
CPU time | 30.73 seconds |
Started | Jul 20 06:13:05 PM PDT 24 |
Finished | Jul 20 06:13:37 PM PDT 24 |
Peak memory | 269556 kb |
Host | smart-0d3326ff-56bd-479a-86fa-71e3c5eef766 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672353185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15. sram_ctrl_partial_access.3672353185 |
Directory | /workspace/15.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2010529692 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 60030699423 ps |
CPU time | 546.75 seconds |
Started | Jul 20 06:13:08 PM PDT 24 |
Finished | Jul 20 06:22:15 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-74a16cc1-9cff-49fb-b1dd-f01b68c99af8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010529692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.sram_ctrl_partial_access_b2b.2010529692 |
Directory | /workspace/15.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_ram_cfg.1866841179 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 345924395 ps |
CPU time | 3.07 seconds |
Started | Jul 20 06:12:58 PM PDT 24 |
Finished | Jul 20 06:13:02 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-1eec29a4-51c3-414b-900e-d7c1054c81e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866841179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.1866841179 |
Directory | /workspace/15.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_regwen.3285226121 |
Short name | T660 |
Test name | |
Test status | |
Simulation time | 5605787677 ps |
CPU time | 1138.57 seconds |
Started | Jul 20 06:13:05 PM PDT 24 |
Finished | Jul 20 06:32:05 PM PDT 24 |
Peak memory | 380784 kb |
Host | smart-a80ae612-e7e8-4cae-9d52-52b468a5debb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285226121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.3285226121 |
Directory | /workspace/15.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_smoke.2110128992 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 2581999628 ps |
CPU time | 20.5 seconds |
Started | Jul 20 06:13:04 PM PDT 24 |
Finished | Jul 20 06:13:26 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-c5cffc24-586d-4ad4-93b2-ba4a59db6049 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110128992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2110128992 |
Directory | /workspace/15.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all.2078005624 |
Short name | T750 |
Test name | |
Test status | |
Simulation time | 28172987737 ps |
CPU time | 3848.25 seconds |
Started | Jul 20 06:13:06 PM PDT 24 |
Finished | Jul 20 07:17:15 PM PDT 24 |
Peak memory | 388992 kb |
Host | smart-cdccc1f1-21f2-4638-a694-75d40b524d02 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078005624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 15.sram_ctrl_stress_all.2078005624 |
Directory | /workspace/15.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.3713521149 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 894309013 ps |
CPU time | 23.57 seconds |
Started | Jul 20 06:13:05 PM PDT 24 |
Finished | Jul 20 06:13:29 PM PDT 24 |
Peak memory | 211164 kb |
Host | smart-a9618a3d-1634-406d-8014-7c61f77d5ff5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3713521149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_stress_all_with_rand_reset.3713521149 |
Directory | /workspace/15.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_stress_pipeline.2112155963 |
Short name | T739 |
Test name | |
Test status | |
Simulation time | 7901107806 ps |
CPU time | 314.28 seconds |
Started | Jul 20 06:13:00 PM PDT 24 |
Finished | Jul 20 06:18:17 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-4c1a5524-5688-4cb7-bad8-68fc18226820 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112155963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 5.sram_ctrl_stress_pipeline.2112155963 |
Directory | /workspace/15.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.4191011563 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 3004240288 ps |
CPU time | 25.3 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 06:13:26 PM PDT 24 |
Peak memory | 277516 kb |
Host | smart-d8cb288d-bf53-46db-96c4-2f6f03097b9f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191011563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.4191011563 |
Directory | /workspace/15.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_access_during_key_req.273176593 |
Short name | T626 |
Test name | |
Test status | |
Simulation time | 315948074355 ps |
CPU time | 2071.6 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 06:47:32 PM PDT 24 |
Peak memory | 378856 kb |
Host | smart-e9b17428-0606-400a-8c6c-a7af176a70e4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273176593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 16.sram_ctrl_access_during_key_req.273176593 |
Directory | /workspace/16.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_alert_test.2293737862 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 36768347 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:13:10 PM PDT 24 |
Finished | Jul 20 06:13:11 PM PDT 24 |
Peak memory | 202476 kb |
Host | smart-92ca2e70-415c-4acf-b615-aa3e56644e05 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293737862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_alert_test.2293737862 |
Directory | /workspace/16.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_bijection.1263569171 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 689375859579 ps |
CPU time | 3039 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 07:03:40 PM PDT 24 |
Peak memory | 203444 kb |
Host | smart-8c1a964e-0359-4b53-bfb4-411bc0a1c9e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263569171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection .1263569171 |
Directory | /workspace/16.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_executable.2833140771 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 17311269089 ps |
CPU time | 1181.13 seconds |
Started | Jul 20 06:13:06 PM PDT 24 |
Finished | Jul 20 06:32:48 PM PDT 24 |
Peak memory | 379856 kb |
Host | smart-712cc55b-94b6-444a-bd3b-bab10a9a308a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833140771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executab le.2833140771 |
Directory | /workspace/16.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_lc_escalation.3559686377 |
Short name | T637 |
Test name | |
Test status | |
Simulation time | 88640031008 ps |
CPU time | 80.78 seconds |
Started | Jul 20 06:13:00 PM PDT 24 |
Finished | Jul 20 06:14:23 PM PDT 24 |
Peak memory | 215864 kb |
Host | smart-bc28d129-fa3a-4c2f-b0e6-484ea709b6bf |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559686377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es calation.3559686377 |
Directory | /workspace/16.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_max_throughput.4272576194 |
Short name | T658 |
Test name | |
Test status | |
Simulation time | 729874011 ps |
CPU time | 11.18 seconds |
Started | Jul 20 06:13:01 PM PDT 24 |
Finished | Jul 20 06:13:14 PM PDT 24 |
Peak memory | 235608 kb |
Host | smart-82599319-6946-4065-b4f4-88d310b15659 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272576194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_max_throughput.4272576194 |
Directory | /workspace/16.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3460171505 |
Short name | T818 |
Test name | |
Test status | |
Simulation time | 6305242068 ps |
CPU time | 132.13 seconds |
Started | Jul 20 06:13:09 PM PDT 24 |
Finished | Jul 20 06:15:21 PM PDT 24 |
Peak memory | 211084 kb |
Host | smart-fbcc1c0f-e3ef-4850-b3e4-69307b07e24d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460171505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 6.sram_ctrl_mem_partial_access.3460171505 |
Directory | /workspace/16.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_mem_walk.4188529818 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 34582047509 ps |
CPU time | 183.17 seconds |
Started | Jul 20 06:13:08 PM PDT 24 |
Finished | Jul 20 06:16:12 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-397407ec-f5f2-4459-b1ce-9c3819859a25 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188529818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr l_mem_walk.4188529818 |
Directory | /workspace/16.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_multiple_keys.2335335952 |
Short name | T940 |
Test name | |
Test status | |
Simulation time | 3188345847 ps |
CPU time | 116.33 seconds |
Started | Jul 20 06:13:03 PM PDT 24 |
Finished | Jul 20 06:15:01 PM PDT 24 |
Peak memory | 303076 kb |
Host | smart-7f86d253-1290-426d-ad5d-8c8fd27e7f28 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335335952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi ple_keys.2335335952 |
Directory | /workspace/16.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access.3779116482 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 364998631 ps |
CPU time | 4.15 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 06:13:05 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-242baf3d-bc59-483a-b15e-014aebcf9c53 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779116482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16. sram_ctrl_partial_access.3779116482 |
Directory | /workspace/16.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.3721316100 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 29140017558 ps |
CPU time | 477.1 seconds |
Started | Jul 20 06:13:02 PM PDT 24 |
Finished | Jul 20 06:21:01 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-6d2c6f88-a32d-4cfc-b8db-858f684e92ed |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721316100 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.sram_ctrl_partial_access_b2b.3721316100 |
Directory | /workspace/16.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_ram_cfg.1122713093 |
Short name | T644 |
Test name | |
Test status | |
Simulation time | 1399179693 ps |
CPU time | 3.82 seconds |
Started | Jul 20 06:12:59 PM PDT 24 |
Finished | Jul 20 06:13:05 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-05caeed7-d221-4973-98be-6ed2a5df869e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122713093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1122713093 |
Directory | /workspace/16.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_regwen.2606135648 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 17211675071 ps |
CPU time | 1374.16 seconds |
Started | Jul 20 06:12:58 PM PDT 24 |
Finished | Jul 20 06:35:54 PM PDT 24 |
Peak memory | 380852 kb |
Host | smart-7214fe33-8b16-4e82-a1bf-36ef7effd0c8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606135648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.2606135648 |
Directory | /workspace/16.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_smoke.1234860665 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 1517130596 ps |
CPU time | 4.19 seconds |
Started | Jul 20 06:13:00 PM PDT 24 |
Finished | Jul 20 06:13:07 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-15cb5180-df52-4c61-a99f-a5d68a5e509f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234860665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.1234860665 |
Directory | /workspace/16.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all.3933829447 |
Short name | T664 |
Test name | |
Test status | |
Simulation time | 751679660516 ps |
CPU time | 4187.66 seconds |
Started | Jul 20 06:13:09 PM PDT 24 |
Finished | Jul 20 07:22:57 PM PDT 24 |
Peak memory | 376700 kb |
Host | smart-7f137ca7-64f4-470d-ab2b-1f42bf95c0f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933829447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 16.sram_ctrl_stress_all.3933829447 |
Directory | /workspace/16.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.133217475 |
Short name | T848 |
Test name | |
Test status | |
Simulation time | 270332592 ps |
CPU time | 8.81 seconds |
Started | Jul 20 06:13:09 PM PDT 24 |
Finished | Jul 20 06:13:19 PM PDT 24 |
Peak memory | 211164 kb |
Host | smart-947c28ee-b68f-4755-b886-bb901fcc3fb5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=133217475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_stress_all_with_rand_reset.133217475 |
Directory | /workspace/16.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_stress_pipeline.676859291 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 37953308486 ps |
CPU time | 282.12 seconds |
Started | Jul 20 06:13:08 PM PDT 24 |
Finished | Jul 20 06:17:51 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-94097626-074b-4479-bf44-4a1dea8af0ff |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676859291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16 .sram_ctrl_stress_pipeline.676859291 |
Directory | /workspace/16.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.948508577 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 3909933325 ps |
CPU time | 20.65 seconds |
Started | Jul 20 06:13:02 PM PDT 24 |
Finished | Jul 20 06:13:24 PM PDT 24 |
Peak memory | 257996 kb |
Host | smart-8bd1da28-a67c-425e-ae36-f1d24bb89229 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948508577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 16.sram_ctrl_throughput_w_partial_write.948508577 |
Directory | /workspace/16.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_access_during_key_req.2982006350 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 22089183714 ps |
CPU time | 553.14 seconds |
Started | Jul 20 06:13:08 PM PDT 24 |
Finished | Jul 20 06:22:22 PM PDT 24 |
Peak memory | 376684 kb |
Host | smart-5505ed68-769a-4350-8b43-ff44f66433b6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982006350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 17.sram_ctrl_access_during_key_req.2982006350 |
Directory | /workspace/17.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_alert_test.1345149092 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 35912554 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:13:08 PM PDT 24 |
Finished | Jul 20 06:13:09 PM PDT 24 |
Peak memory | 202688 kb |
Host | smart-e36fac3d-5a7d-490a-9c64-1f1be46a354b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345149092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_alert_test.1345149092 |
Directory | /workspace/17.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_bijection.2741101601 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 19492637627 ps |
CPU time | 1473.98 seconds |
Started | Jul 20 06:13:07 PM PDT 24 |
Finished | Jul 20 06:37:42 PM PDT 24 |
Peak memory | 203552 kb |
Host | smart-7d4ce816-c8f0-489a-a3dd-a35c2dbec180 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741101601 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection .2741101601 |
Directory | /workspace/17.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_executable.700424961 |
Short name | T611 |
Test name | |
Test status | |
Simulation time | 27177493469 ps |
CPU time | 1769.48 seconds |
Started | Jul 20 06:13:06 PM PDT 24 |
Finished | Jul 20 06:42:37 PM PDT 24 |
Peak memory | 380848 kb |
Host | smart-486a056a-1222-41b6-a53b-ac2e1b8d10f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700424961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executabl e.700424961 |
Directory | /workspace/17.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_lc_escalation.2484417486 |
Short name | T917 |
Test name | |
Test status | |
Simulation time | 34787951822 ps |
CPU time | 61.03 seconds |
Started | Jul 20 06:13:04 PM PDT 24 |
Finished | Jul 20 06:14:06 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-29bf7ae1-013b-4f0b-8a19-c6ccfbd738e0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484417486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_lc_es calation.2484417486 |
Directory | /workspace/17.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_max_throughput.4280998864 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 3314082846 ps |
CPU time | 110.02 seconds |
Started | Jul 20 06:13:04 PM PDT 24 |
Finished | Jul 20 06:14:56 PM PDT 24 |
Peak memory | 370532 kb |
Host | smart-38a017a4-73e1-4875-b653-8954b24c6f3c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280998864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 17.sram_ctrl_max_throughput.4280998864 |
Directory | /workspace/17.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1535218369 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 1120668074 ps |
CPU time | 66.59 seconds |
Started | Jul 20 06:13:05 PM PDT 24 |
Finished | Jul 20 06:14:12 PM PDT 24 |
Peak memory | 219328 kb |
Host | smart-7ab65d98-fb35-49d8-9f26-f4532d6d0a99 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535218369 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 7.sram_ctrl_mem_partial_access.1535218369 |
Directory | /workspace/17.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_mem_walk.3684397845 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 8990873225 ps |
CPU time | 171.57 seconds |
Started | Jul 20 06:13:03 PM PDT 24 |
Finished | Jul 20 06:15:56 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-70f6a8a2-f058-45d8-9133-78b6bc600d2a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684397845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctr l_mem_walk.3684397845 |
Directory | /workspace/17.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_multiple_keys.3316338961 |
Short name | T941 |
Test name | |
Test status | |
Simulation time | 71719140989 ps |
CPU time | 914.78 seconds |
Started | Jul 20 06:13:08 PM PDT 24 |
Finished | Jul 20 06:28:24 PM PDT 24 |
Peak memory | 379788 kb |
Host | smart-321f17c8-e268-4b33-aa70-a0ee5b186732 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316338961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multi ple_keys.3316338961 |
Directory | /workspace/17.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access.39847292 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 937676346 ps |
CPU time | 160.34 seconds |
Started | Jul 20 06:13:05 PM PDT 24 |
Finished | Jul 20 06:15:46 PM PDT 24 |
Peak memory | 358208 kb |
Host | smart-74ccc3c4-7148-4253-910d-d8ac58df0da5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39847292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sr am_ctrl_partial_access.39847292 |
Directory | /workspace/17.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.571998579 |
Short name | T648 |
Test name | |
Test status | |
Simulation time | 11449020052 ps |
CPU time | 315.81 seconds |
Started | Jul 20 06:13:07 PM PDT 24 |
Finished | Jul 20 06:18:23 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-90729140-14a6-45e5-b7cb-33308ac1a066 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571998579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 17.sram_ctrl_partial_access_b2b.571998579 |
Directory | /workspace/17.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_ram_cfg.3239291979 |
Short name | T667 |
Test name | |
Test status | |
Simulation time | 354682801 ps |
CPU time | 3.35 seconds |
Started | Jul 20 06:13:06 PM PDT 24 |
Finished | Jul 20 06:13:11 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-55dc4ef5-74db-4e32-9678-802981053743 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239291979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.3239291979 |
Directory | /workspace/17.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_regwen.2738966967 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 25962657704 ps |
CPU time | 589.28 seconds |
Started | Jul 20 06:13:09 PM PDT 24 |
Finished | Jul 20 06:22:59 PM PDT 24 |
Peak memory | 358276 kb |
Host | smart-fdc0d8af-a579-4d94-a9c1-e6dc3bbf81d4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738966967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.2738966967 |
Directory | /workspace/17.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_smoke.1386565699 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 1055328493 ps |
CPU time | 15.31 seconds |
Started | Jul 20 06:13:06 PM PDT 24 |
Finished | Jul 20 06:13:22 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-d69664a0-1bed-4fd6-bd7f-baed89759eaa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386565699 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.1386565699 |
Directory | /workspace/17.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all.2329030033 |
Short name | T904 |
Test name | |
Test status | |
Simulation time | 77089088452 ps |
CPU time | 1648.6 seconds |
Started | Jul 20 06:13:07 PM PDT 24 |
Finished | Jul 20 06:40:37 PM PDT 24 |
Peak memory | 379704 kb |
Host | smart-ef821f50-fcab-4b92-a48c-f11141511cfe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329030033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.sram_ctrl_stress_all.2329030033 |
Directory | /workspace/17.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3910613701 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 6173812076 ps |
CPU time | 54.48 seconds |
Started | Jul 20 06:13:07 PM PDT 24 |
Finished | Jul 20 06:14:03 PM PDT 24 |
Peak memory | 211176 kb |
Host | smart-6e119ac4-f8a6-4e0f-a198-2f5590a4b25b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3910613701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_stress_all_with_rand_reset.3910613701 |
Directory | /workspace/17.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_stress_pipeline.46526600 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 6063612255 ps |
CPU time | 360.89 seconds |
Started | Jul 20 06:13:09 PM PDT 24 |
Finished | Jul 20 06:19:10 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-051769f8-094e-4928-81f0-dba3a3c698ad |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46526600 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17. sram_ctrl_stress_pipeline.46526600 |
Directory | /workspace/17.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.1553385971 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 1562694115 ps |
CPU time | 114.86 seconds |
Started | Jul 20 06:13:07 PM PDT 24 |
Finished | Jul 20 06:15:03 PM PDT 24 |
Peak memory | 370504 kb |
Host | smart-25fb77a8-a051-4816-ab9b-42e5b2c6ea64 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553385971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sram_ctrl_throughput_w_partial_write.1553385971 |
Directory | /workspace/17.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2557013547 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 14897333530 ps |
CPU time | 981.15 seconds |
Started | Jul 20 06:13:15 PM PDT 24 |
Finished | Jul 20 06:29:37 PM PDT 24 |
Peak memory | 377720 kb |
Host | smart-e33b06a0-4d52-4e64-b470-8a79253c1998 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557013547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 18.sram_ctrl_access_during_key_req.2557013547 |
Directory | /workspace/18.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_alert_test.2530140009 |
Short name | T719 |
Test name | |
Test status | |
Simulation time | 33690504 ps |
CPU time | 0.61 seconds |
Started | Jul 20 06:13:19 PM PDT 24 |
Finished | Jul 20 06:13:20 PM PDT 24 |
Peak memory | 202480 kb |
Host | smart-f508ecc6-e031-4e0a-9b7e-8caa60a300ba |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530140009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_alert_test.2530140009 |
Directory | /workspace/18.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_bijection.2300619752 |
Short name | T860 |
Test name | |
Test status | |
Simulation time | 150484080610 ps |
CPU time | 1851.92 seconds |
Started | Jul 20 06:13:19 PM PDT 24 |
Finished | Jul 20 06:44:12 PM PDT 24 |
Peak memory | 203572 kb |
Host | smart-0f9a6d09-f669-4025-9e44-4203ef948c4b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300619752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection .2300619752 |
Directory | /workspace/18.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_lc_escalation.864828892 |
Short name | T680 |
Test name | |
Test status | |
Simulation time | 19308810852 ps |
CPU time | 58.88 seconds |
Started | Jul 20 06:13:11 PM PDT 24 |
Finished | Jul 20 06:14:10 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-4371845a-92c7-4418-afca-2c3bd50d2e79 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864828892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_lc_esc alation.864828892 |
Directory | /workspace/18.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_max_throughput.1115017665 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 1046502338 ps |
CPU time | 8.54 seconds |
Started | Jul 20 06:13:11 PM PDT 24 |
Finished | Jul 20 06:13:20 PM PDT 24 |
Peak memory | 220732 kb |
Host | smart-6f1c42e4-c02c-4df7-9435-10021cc6c2ff |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115017665 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_max_throughput.1115017665 |
Directory | /workspace/18.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_partial_access.1264330545 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 994008373 ps |
CPU time | 66.97 seconds |
Started | Jul 20 06:13:24 PM PDT 24 |
Finished | Jul 20 06:14:31 PM PDT 24 |
Peak memory | 211052 kb |
Host | smart-b61a2459-8e8b-4bd6-a6a9-c65cbd2984f5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264330545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_mem_partial_access.1264330545 |
Directory | /workspace/18.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_mem_walk.1369039741 |
Short name | T879 |
Test name | |
Test status | |
Simulation time | 147970806400 ps |
CPU time | 369.71 seconds |
Started | Jul 20 06:13:21 PM PDT 24 |
Finished | Jul 20 06:19:31 PM PDT 24 |
Peak memory | 211068 kb |
Host | smart-28df7923-386a-4252-805b-10affcac9e8f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369039741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr l_mem_walk.1369039741 |
Directory | /workspace/18.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_multiple_keys.3840183175 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 9472046805 ps |
CPU time | 740.11 seconds |
Started | Jul 20 06:13:05 PM PDT 24 |
Finished | Jul 20 06:25:26 PM PDT 24 |
Peak memory | 377720 kb |
Host | smart-bec859fa-4b61-49f3-bfac-78e3cd0e45e8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840183175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi ple_keys.3840183175 |
Directory | /workspace/18.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access.2357023168 |
Short name | T713 |
Test name | |
Test status | |
Simulation time | 1185896728 ps |
CPU time | 70.48 seconds |
Started | Jul 20 06:13:18 PM PDT 24 |
Finished | Jul 20 06:14:29 PM PDT 24 |
Peak memory | 338796 kb |
Host | smart-dc3c70a8-1e98-4d7e-99ab-3d959d6ead83 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357023168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18. sram_ctrl_partial_access.2357023168 |
Directory | /workspace/18.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.211888515 |
Short name | T890 |
Test name | |
Test status | |
Simulation time | 11910742950 ps |
CPU time | 255.54 seconds |
Started | Jul 20 06:13:13 PM PDT 24 |
Finished | Jul 20 06:17:29 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-dea4f4e3-a346-407a-a7d1-de16bd9ff8ea |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211888515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 18.sram_ctrl_partial_access_b2b.211888515 |
Directory | /workspace/18.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_regwen.4291762496 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 18572893544 ps |
CPU time | 1178.78 seconds |
Started | Jul 20 06:13:17 PM PDT 24 |
Finished | Jul 20 06:32:56 PM PDT 24 |
Peak memory | 378952 kb |
Host | smart-be799923-d6d9-4326-92e4-96544cb41350 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291762496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.4291762496 |
Directory | /workspace/18.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_smoke.2553919010 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 11383162743 ps |
CPU time | 22.71 seconds |
Started | Jul 20 06:13:10 PM PDT 24 |
Finished | Jul 20 06:13:33 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-0145acc2-1972-4187-ac26-484b271e79a8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553919010 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.2553919010 |
Directory | /workspace/18.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all.1188271330 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 108364476769 ps |
CPU time | 6907.81 seconds |
Started | Jul 20 06:13:11 PM PDT 24 |
Finished | Jul 20 08:08:20 PM PDT 24 |
Peak memory | 380016 kb |
Host | smart-ca9c7973-270c-48e5-bff1-4139a539e831 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188271330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.sram_ctrl_stress_all.1188271330 |
Directory | /workspace/18.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.4028681816 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 696495690 ps |
CPU time | 15.29 seconds |
Started | Jul 20 06:13:18 PM PDT 24 |
Finished | Jul 20 06:13:33 PM PDT 24 |
Peak memory | 211152 kb |
Host | smart-869fd00c-7f5b-426c-bafe-9172e20c155c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4028681816 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_stress_all_with_rand_reset.4028681816 |
Directory | /workspace/18.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_stress_pipeline.2067900689 |
Short name | T933 |
Test name | |
Test status | |
Simulation time | 2705967118 ps |
CPU time | 183.1 seconds |
Started | Jul 20 06:13:16 PM PDT 24 |
Finished | Jul 20 06:16:20 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-a47375b9-e776-4fcf-b964-e47840823d74 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067900689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 8.sram_ctrl_stress_pipeline.2067900689 |
Directory | /workspace/18.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.443764654 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 3071970410 ps |
CPU time | 42.44 seconds |
Started | Jul 20 06:13:17 PM PDT 24 |
Finished | Jul 20 06:14:00 PM PDT 24 |
Peak memory | 301028 kb |
Host | smart-b562d350-770b-4e3a-a67f-75f7def8e065 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443764654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 18.sram_ctrl_throughput_w_partial_write.443764654 |
Directory | /workspace/18.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_access_during_key_req.1735427240 |
Short name | T625 |
Test name | |
Test status | |
Simulation time | 7763544409 ps |
CPU time | 46.12 seconds |
Started | Jul 20 06:13:24 PM PDT 24 |
Finished | Jul 20 06:14:10 PM PDT 24 |
Peak memory | 259616 kb |
Host | smart-8c734112-7424-49bc-8aec-1e64065d5098 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735427240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 19.sram_ctrl_access_during_key_req.1735427240 |
Directory | /workspace/19.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_alert_test.2825619716 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 32727347 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:13:27 PM PDT 24 |
Finished | Jul 20 06:13:28 PM PDT 24 |
Peak memory | 202644 kb |
Host | smart-bbcdd1d8-ce73-4a50-ab64-cece7c8ffef0 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825619716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_alert_test.2825619716 |
Directory | /workspace/19.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_bijection.3147569357 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 183197814284 ps |
CPU time | 1534.78 seconds |
Started | Jul 20 06:13:19 PM PDT 24 |
Finished | Jul 20 06:38:54 PM PDT 24 |
Peak memory | 203636 kb |
Host | smart-9af197bf-b837-4b56-9ec1-33a374057a61 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147569357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection .3147569357 |
Directory | /workspace/19.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_executable.4217863689 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 24501561991 ps |
CPU time | 479.14 seconds |
Started | Jul 20 06:13:23 PM PDT 24 |
Finished | Jul 20 06:21:22 PM PDT 24 |
Peak memory | 367480 kb |
Host | smart-ebaaf86a-4aba-4e7e-881c-5aad545e4c07 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217863689 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executab le.4217863689 |
Directory | /workspace/19.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_lc_escalation.2827305134 |
Short name | T670 |
Test name | |
Test status | |
Simulation time | 68043766008 ps |
CPU time | 32 seconds |
Started | Jul 20 06:13:22 PM PDT 24 |
Finished | Jul 20 06:13:55 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-a009c078-c5ae-4878-97bd-d5647694b040 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827305134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es calation.2827305134 |
Directory | /workspace/19.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_max_throughput.2448997077 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 7875200592 ps |
CPU time | 35.4 seconds |
Started | Jul 20 06:13:20 PM PDT 24 |
Finished | Jul 20 06:13:56 PM PDT 24 |
Peak memory | 277944 kb |
Host | smart-ea2e6a25-29cb-4263-bab6-3d8420196431 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448997077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 19.sram_ctrl_max_throughput.2448997077 |
Directory | /workspace/19.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_partial_access.1790941205 |
Short name | T600 |
Test name | |
Test status | |
Simulation time | 5453311346 ps |
CPU time | 161.52 seconds |
Started | Jul 20 06:13:26 PM PDT 24 |
Finished | Jul 20 06:16:08 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-036186dd-758a-4e73-abc0-9327e2ce053d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790941205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_mem_partial_access.1790941205 |
Directory | /workspace/19.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_mem_walk.3240650848 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 13829434900 ps |
CPU time | 324.63 seconds |
Started | Jul 20 06:13:29 PM PDT 24 |
Finished | Jul 20 06:18:55 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-42cba7b8-d751-45d5-9840-69cef97ebefe |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240650848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctr l_mem_walk.3240650848 |
Directory | /workspace/19.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_multiple_keys.3465528237 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 8611696895 ps |
CPU time | 252.72 seconds |
Started | Jul 20 06:13:16 PM PDT 24 |
Finished | Jul 20 06:17:29 PM PDT 24 |
Peak memory | 360640 kb |
Host | smart-ebb418c3-b80b-465f-99b6-1216c26039f2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465528237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multi ple_keys.3465528237 |
Directory | /workspace/19.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access.3632238684 |
Short name | T704 |
Test name | |
Test status | |
Simulation time | 613648544 ps |
CPU time | 20.12 seconds |
Started | Jul 20 06:13:22 PM PDT 24 |
Finished | Jul 20 06:13:42 PM PDT 24 |
Peak memory | 269280 kb |
Host | smart-5a85e506-99e6-466d-bbf7-1706fef74a91 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632238684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19. sram_ctrl_partial_access.3632238684 |
Directory | /workspace/19.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1064917933 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 151358732682 ps |
CPU time | 350.8 seconds |
Started | Jul 20 06:13:24 PM PDT 24 |
Finished | Jul 20 06:19:15 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-7c328c37-b957-4329-9edd-f29357bc5d9f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064917933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 19.sram_ctrl_partial_access_b2b.1064917933 |
Directory | /workspace/19.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_ram_cfg.438210688 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 1412794414 ps |
CPU time | 3.6 seconds |
Started | Jul 20 06:13:24 PM PDT 24 |
Finished | Jul 20 06:13:28 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-ef6ef5a0-2585-4f79-82f7-ab39e7b9d5ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438210688 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.438210688 |
Directory | /workspace/19.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_regwen.375214070 |
Short name | T800 |
Test name | |
Test status | |
Simulation time | 12720346284 ps |
CPU time | 693.36 seconds |
Started | Jul 20 06:13:26 PM PDT 24 |
Finished | Jul 20 06:25:00 PM PDT 24 |
Peak memory | 364456 kb |
Host | smart-a60efab8-eeaa-4c9c-ba7b-8b666ed81d47 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375214070 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.375214070 |
Directory | /workspace/19.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_smoke.2050237667 |
Short name | T914 |
Test name | |
Test status | |
Simulation time | 9816506654 ps |
CPU time | 30.82 seconds |
Started | Jul 20 06:13:18 PM PDT 24 |
Finished | Jul 20 06:13:49 PM PDT 24 |
Peak memory | 276944 kb |
Host | smart-ff4de0dd-6c57-47be-b3ea-f6f5a0c1650f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050237667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.2050237667 |
Directory | /workspace/19.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all.1654806762 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 618032922102 ps |
CPU time | 5062 seconds |
Started | Jul 20 06:13:22 PM PDT 24 |
Finished | Jul 20 07:37:45 PM PDT 24 |
Peak memory | 389052 kb |
Host | smart-bbbe7d81-73c0-439e-948f-4f45efe9add2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654806762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.sram_ctrl_stress_all.1654806762 |
Directory | /workspace/19.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.3182825996 |
Short name | T738 |
Test name | |
Test status | |
Simulation time | 2295672500 ps |
CPU time | 15.55 seconds |
Started | Jul 20 06:13:29 PM PDT 24 |
Finished | Jul 20 06:13:45 PM PDT 24 |
Peak memory | 211572 kb |
Host | smart-3d9c6665-a2bc-42e9-935c-c58354fe32aa |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3182825996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_stress_all_with_rand_reset.3182825996 |
Directory | /workspace/19.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3762164154 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 25766904207 ps |
CPU time | 424.24 seconds |
Started | Jul 20 06:13:14 PM PDT 24 |
Finished | Jul 20 06:20:18 PM PDT 24 |
Peak memory | 203048 kb |
Host | smart-92cd0e0c-de6d-438e-aaae-4f3518acd6b5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762164154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.sram_ctrl_stress_pipeline.3762164154 |
Directory | /workspace/19.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1462230462 |
Short name | T582 |
Test name | |
Test status | |
Simulation time | 1530925730 ps |
CPU time | 35.51 seconds |
Started | Jul 20 06:13:23 PM PDT 24 |
Finished | Jul 20 06:13:59 PM PDT 24 |
Peak memory | 292664 kb |
Host | smart-e00ec4b2-1b5d-4ed3-b60a-3c9690311b26 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462230462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.1462230462 |
Directory | /workspace/19.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2930166219 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 7119414415 ps |
CPU time | 75.33 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:13:54 PM PDT 24 |
Peak memory | 319684 kb |
Host | smart-f04115a5-3d43-40e9-9f23-8fb4dec98234 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930166219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.sram_ctrl_access_during_key_req.2930166219 |
Directory | /workspace/2.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_alert_test.4293108986 |
Short name | T777 |
Test name | |
Test status | |
Simulation time | 17396692 ps |
CPU time | 0.67 seconds |
Started | Jul 20 06:12:32 PM PDT 24 |
Finished | Jul 20 06:12:35 PM PDT 24 |
Peak memory | 201956 kb |
Host | smart-db20021c-ebe9-4480-8dbe-99ff29a76cfd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293108986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_alert_test.4293108986 |
Directory | /workspace/2.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_bijection.3234250057 |
Short name | T753 |
Test name | |
Test status | |
Simulation time | 93579522195 ps |
CPU time | 1551.08 seconds |
Started | Jul 20 06:12:37 PM PDT 24 |
Finished | Jul 20 06:38:30 PM PDT 24 |
Peak memory | 203788 kb |
Host | smart-a5a6f2b6-6a2d-40dc-b2bf-43549f15c251 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234250057 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection. 3234250057 |
Directory | /workspace/2.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_executable.2780415908 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 41306350677 ps |
CPU time | 1024.44 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:29:42 PM PDT 24 |
Peak memory | 369568 kb |
Host | smart-4e16b815-8eed-4199-a480-6a848b0d4e7c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780415908 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl e.2780415908 |
Directory | /workspace/2.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_lc_escalation.2464049505 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 15951203078 ps |
CPU time | 52.63 seconds |
Started | Jul 20 06:12:35 PM PDT 24 |
Finished | Jul 20 06:13:29 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-f30b2643-014a-4306-adab-aa181322b75e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464049505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc alation.2464049505 |
Directory | /workspace/2.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_max_throughput.3166386850 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 2739295641 ps |
CPU time | 11.71 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:12:47 PM PDT 24 |
Peak memory | 235640 kb |
Host | smart-ad471f3a-a3da-4bb4-84fe-5997c0dc5b65 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166386850 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.sram_ctrl_max_throughput.3166386850 |
Directory | /workspace/2.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2963088648 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 48219394238 ps |
CPU time | 162.96 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:15:19 PM PDT 24 |
Peak memory | 215144 kb |
Host | smart-90815561-1bd5-4b34-a37e-1f8bf11c1f28 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963088648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_mem_partial_access.2963088648 |
Directory | /workspace/2.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_mem_walk.3655380088 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 21640676574 ps |
CPU time | 328.51 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:18:04 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-115db4ca-bf08-4ae8-bdf9-159def9ea6f1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655380088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl _mem_walk.3655380088 |
Directory | /workspace/2.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_multiple_keys.1471451679 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 8379373256 ps |
CPU time | 204.76 seconds |
Started | Jul 20 06:12:31 PM PDT 24 |
Finished | Jul 20 06:15:58 PM PDT 24 |
Peak memory | 378624 kb |
Host | smart-9c668af1-b211-4c0e-af77-31f61a924143 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471451679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip le_keys.1471451679 |
Directory | /workspace/2.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access.2373727421 |
Short name | T844 |
Test name | |
Test status | |
Simulation time | 3811474892 ps |
CPU time | 14.15 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:12:52 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-b0176cf7-8982-448a-90d8-4767c2e01645 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373727421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s ram_ctrl_partial_access.2373727421 |
Directory | /workspace/2.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2721643050 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 75530401088 ps |
CPU time | 453.83 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:20:10 PM PDT 24 |
Peak memory | 202852 kb |
Host | smart-ed200030-7b8d-458b-af17-15a85a692ea0 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721643050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_partial_access_b2b.2721643050 |
Directory | /workspace/2.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_ram_cfg.2567348565 |
Short name | T819 |
Test name | |
Test status | |
Simulation time | 641016370 ps |
CPU time | 3.09 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:12:39 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-075d0d33-5473-4958-94f1-511c8204328f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567348565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.2567348565 |
Directory | /workspace/2.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_sec_cm.4106496580 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 912221152 ps |
CPU time | 2.84 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:12:41 PM PDT 24 |
Peak memory | 221980 kb |
Host | smart-2141f2b9-afbf-4242-bf9a-ad342bec88a7 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106496580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_sec_cm.4106496580 |
Directory | /workspace/2.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_smoke.1002706642 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 6123972994 ps |
CPU time | 22.74 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:13:01 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-b0bdfeb3-0fee-47f4-816c-491b35d58c43 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002706642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1002706642 |
Directory | /workspace/2.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all.995111664 |
Short name | T591 |
Test name | |
Test status | |
Simulation time | 20262776418 ps |
CPU time | 2925.16 seconds |
Started | Jul 20 06:12:38 PM PDT 24 |
Finished | Jul 20 07:01:25 PM PDT 24 |
Peak memory | 382896 kb |
Host | smart-c779561e-1bb0-42dd-a54f-815804099cb5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995111664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.sram_ctrl_stress_all.995111664 |
Directory | /workspace/2.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3956372412 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 978471710 ps |
CPU time | 25.97 seconds |
Started | Jul 20 06:12:31 PM PDT 24 |
Finished | Jul 20 06:12:59 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-0d3d1854-8b80-4b2d-af1c-7399ee74144c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3956372412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_stress_all_with_rand_reset.3956372412 |
Directory | /workspace/2.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_stress_pipeline.1729867455 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 13086408690 ps |
CPU time | 244.13 seconds |
Started | Jul 20 06:12:32 PM PDT 24 |
Finished | Jul 20 06:16:38 PM PDT 24 |
Peak memory | 202632 kb |
Host | smart-21df342d-0578-4b5c-b786-3235e227678e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729867455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .sram_ctrl_stress_pipeline.1729867455 |
Directory | /workspace/2.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.1115109012 |
Short name | T799 |
Test name | |
Test status | |
Simulation time | 781143244 ps |
CPU time | 56.72 seconds |
Started | Jul 20 06:12:31 PM PDT 24 |
Finished | Jul 20 06:13:30 PM PDT 24 |
Peak memory | 319384 kb |
Host | smart-e7468a0d-4e2a-4e30-b9dd-f428d6e46056 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115109012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.1115109012 |
Directory | /workspace/2.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_access_during_key_req.3197521027 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 15955097384 ps |
CPU time | 840.34 seconds |
Started | Jul 20 06:13:28 PM PDT 24 |
Finished | Jul 20 06:27:29 PM PDT 24 |
Peak memory | 367980 kb |
Host | smart-35d1b25f-538e-4fe1-a235-d1ed2d7fb045 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197521027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_access_during_key_req.3197521027 |
Directory | /workspace/20.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_alert_test.844006146 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 15358665 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:13:28 PM PDT 24 |
Finished | Jul 20 06:13:30 PM PDT 24 |
Peak memory | 202480 kb |
Host | smart-378ef95a-4141-4b1b-ad65-c12c05c6b849 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844006146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_alert_test.844006146 |
Directory | /workspace/20.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_bijection.2232765 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 460272662190 ps |
CPU time | 1996.84 seconds |
Started | Jul 20 06:13:23 PM PDT 24 |
Finished | Jul 20 06:46:41 PM PDT 24 |
Peak memory | 203444 kb |
Host | smart-c99e3793-c6fe-4c99-915a-f8813cb7d224 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijecti on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection.2232765 |
Directory | /workspace/20.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_executable.769845955 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 7563684902 ps |
CPU time | 985.56 seconds |
Started | Jul 20 06:13:32 PM PDT 24 |
Finished | Jul 20 06:29:58 PM PDT 24 |
Peak memory | 379856 kb |
Host | smart-4c1a85fc-e9b2-4006-80af-46c0ce1c2cc4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769845955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executabl e.769845955 |
Directory | /workspace/20.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_lc_escalation.3632332167 |
Short name | T796 |
Test name | |
Test status | |
Simulation time | 23700004949 ps |
CPU time | 44.62 seconds |
Started | Jul 20 06:13:29 PM PDT 24 |
Finished | Jul 20 06:14:15 PM PDT 24 |
Peak memory | 215616 kb |
Host | smart-33da3f1b-50f6-4a41-b46f-d10fad4ffb2f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632332167 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_es calation.3632332167 |
Directory | /workspace/20.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_max_throughput.1223425040 |
Short name | T823 |
Test name | |
Test status | |
Simulation time | 725627914 ps |
CPU time | 19.29 seconds |
Started | Jul 20 06:13:29 PM PDT 24 |
Finished | Jul 20 06:13:49 PM PDT 24 |
Peak memory | 260172 kb |
Host | smart-e16d9a5c-f74c-4435-a351-83142bafb204 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223425040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_max_throughput.1223425040 |
Directory | /workspace/20.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2008577046 |
Short name | T714 |
Test name | |
Test status | |
Simulation time | 5243170073 ps |
CPU time | 181.48 seconds |
Started | Jul 20 06:13:32 PM PDT 24 |
Finished | Jul 20 06:16:34 PM PDT 24 |
Peak memory | 219220 kb |
Host | smart-23597855-26d0-4704-b92e-875dcbbd1b23 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008577046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_mem_partial_access.2008577046 |
Directory | /workspace/20.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_mem_walk.3635770324 |
Short name | T805 |
Test name | |
Test status | |
Simulation time | 10513788363 ps |
CPU time | 160.24 seconds |
Started | Jul 20 06:13:29 PM PDT 24 |
Finished | Jul 20 06:16:10 PM PDT 24 |
Peak memory | 211068 kb |
Host | smart-d933e239-5d22-4e98-892b-3713d4a5bee4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635770324 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr l_mem_walk.3635770324 |
Directory | /workspace/20.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_multiple_keys.2608316674 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 5127447316 ps |
CPU time | 228.14 seconds |
Started | Jul 20 06:13:20 PM PDT 24 |
Finished | Jul 20 06:17:09 PM PDT 24 |
Peak memory | 303240 kb |
Host | smart-75b2bfd0-452c-475d-b592-fb33291681c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608316674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi ple_keys.2608316674 |
Directory | /workspace/20.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access.2595493615 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 1080179783 ps |
CPU time | 12.64 seconds |
Started | Jul 20 06:13:27 PM PDT 24 |
Finished | Jul 20 06:13:40 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-61634b61-1e43-4c62-b75f-1e83cbb095ae |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595493615 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20. sram_ctrl_partial_access.2595493615 |
Directory | /workspace/20.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.43215371 |
Short name | T748 |
Test name | |
Test status | |
Simulation time | 39389815559 ps |
CPU time | 250.47 seconds |
Started | Jul 20 06:13:27 PM PDT 24 |
Finished | Jul 20 06:17:38 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-0dc5796f-bb3c-4e1b-afc9-b222713f0ee9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43215371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 20.sram_ctrl_partial_access_b2b.43215371 |
Directory | /workspace/20.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_ram_cfg.3869855218 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 1350885119 ps |
CPU time | 3.5 seconds |
Started | Jul 20 06:13:29 PM PDT 24 |
Finished | Jul 20 06:13:34 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-b1c7cd02-b066-42b5-8924-2ecebf764ca7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869855218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.3869855218 |
Directory | /workspace/20.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_regwen.171723603 |
Short name | T732 |
Test name | |
Test status | |
Simulation time | 1777934972 ps |
CPU time | 634.84 seconds |
Started | Jul 20 06:13:30 PM PDT 24 |
Finished | Jul 20 06:24:06 PM PDT 24 |
Peak memory | 378684 kb |
Host | smart-72b17eea-b93b-44c7-a066-9d66c4fbd857 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171723603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.171723603 |
Directory | /workspace/20.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_smoke.286740686 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 7721719209 ps |
CPU time | 19.69 seconds |
Started | Jul 20 06:13:21 PM PDT 24 |
Finished | Jul 20 06:13:41 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-96b849f0-201d-4aea-bb6b-4f0add6f06e3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286740686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.286740686 |
Directory | /workspace/20.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all.2231877790 |
Short name | T928 |
Test name | |
Test status | |
Simulation time | 258158342010 ps |
CPU time | 4019.6 seconds |
Started | Jul 20 06:13:29 PM PDT 24 |
Finished | Jul 20 07:20:30 PM PDT 24 |
Peak memory | 379080 kb |
Host | smart-f0fe171f-86b6-4b88-8e72-3d35307873a0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231877790 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.sram_ctrl_stress_all.2231877790 |
Directory | /workspace/20.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3107754093 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 8206821182 ps |
CPU time | 30.83 seconds |
Started | Jul 20 06:13:29 PM PDT 24 |
Finished | Jul 20 06:14:01 PM PDT 24 |
Peak memory | 211288 kb |
Host | smart-9fa1450e-bcb2-4835-9a4d-a88dd4cd762c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3107754093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_stress_all_with_rand_reset.3107754093 |
Directory | /workspace/20.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_stress_pipeline.2029684052 |
Short name | T602 |
Test name | |
Test status | |
Simulation time | 18743736775 ps |
CPU time | 298.83 seconds |
Started | Jul 20 06:13:22 PM PDT 24 |
Finished | Jul 20 06:18:22 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-92a91206-2cac-4b33-be24-024790319671 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029684052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 0.sram_ctrl_stress_pipeline.2029684052 |
Directory | /workspace/20.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.183373864 |
Short name | T662 |
Test name | |
Test status | |
Simulation time | 797057721 ps |
CPU time | 71.39 seconds |
Started | Jul 20 06:13:29 PM PDT 24 |
Finished | Jul 20 06:14:41 PM PDT 24 |
Peak memory | 319408 kb |
Host | smart-e5ff2655-bd16-409d-afaa-d6f01c85ddd4 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183373864 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 20.sram_ctrl_throughput_w_partial_write.183373864 |
Directory | /workspace/20.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_access_during_key_req.399203219 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 7380749425 ps |
CPU time | 150.61 seconds |
Started | Jul 20 06:13:38 PM PDT 24 |
Finished | Jul 20 06:16:10 PM PDT 24 |
Peak memory | 343864 kb |
Host | smart-ee4729e8-6843-4b56-9f49-e0e6c0cf0e85 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399203219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 21.sram_ctrl_access_during_key_req.399203219 |
Directory | /workspace/21.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_alert_test.1428661951 |
Short name | T706 |
Test name | |
Test status | |
Simulation time | 12052107 ps |
CPU time | 0.67 seconds |
Started | Jul 20 06:13:46 PM PDT 24 |
Finished | Jul 20 06:13:47 PM PDT 24 |
Peak memory | 202504 kb |
Host | smart-6ec0bc64-9daa-40b5-b459-789a11e0ef01 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428661951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_alert_test.1428661951 |
Directory | /workspace/21.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_bijection.1815224340 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 398809171388 ps |
CPU time | 1950.21 seconds |
Started | Jul 20 06:13:29 PM PDT 24 |
Finished | Jul 20 06:46:01 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-e51005af-f79c-4311-99df-333773ec8327 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815224340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection .1815224340 |
Directory | /workspace/21.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_executable.1193480492 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 82001505528 ps |
CPU time | 1851.3 seconds |
Started | Jul 20 06:13:44 PM PDT 24 |
Finished | Jul 20 06:44:37 PM PDT 24 |
Peak memory | 379800 kb |
Host | smart-279b2898-3c9b-4fbf-9d77-c30348ec2278 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193480492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executab le.1193480492 |
Directory | /workspace/21.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_lc_escalation.4183886399 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 225795037350 ps |
CPU time | 82.52 seconds |
Started | Jul 20 06:13:40 PM PDT 24 |
Finished | Jul 20 06:15:03 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-e52466f9-ab23-42d8-86b2-cc3d281ce658 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183886399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es calation.4183886399 |
Directory | /workspace/21.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_max_throughput.528694570 |
Short name | T773 |
Test name | |
Test status | |
Simulation time | 749195534 ps |
CPU time | 52.01 seconds |
Started | Jul 20 06:13:28 PM PDT 24 |
Finished | Jul 20 06:14:21 PM PDT 24 |
Peak memory | 326564 kb |
Host | smart-92910c98-2263-481a-b9b2-3570378eae92 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528694570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.sram_ctrl_max_throughput.528694570 |
Directory | /workspace/21.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_partial_access.4210365021 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 2445701449 ps |
CPU time | 145.78 seconds |
Started | Jul 20 06:13:45 PM PDT 24 |
Finished | Jul 20 06:16:12 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-998a40a6-cb87-4d36-bbca-474327838e5f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210365021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_mem_partial_access.4210365021 |
Directory | /workspace/21.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_mem_walk.1859103117 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 14584669544 ps |
CPU time | 315.63 seconds |
Started | Jul 20 06:13:37 PM PDT 24 |
Finished | Jul 20 06:18:53 PM PDT 24 |
Peak memory | 212236 kb |
Host | smart-330dd66a-ab9b-48bb-9b63-b11fe03ff56c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859103117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctr l_mem_walk.1859103117 |
Directory | /workspace/21.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_multiple_keys.2043332025 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 6895305669 ps |
CPU time | 218.67 seconds |
Started | Jul 20 06:13:29 PM PDT 24 |
Finished | Jul 20 06:17:09 PM PDT 24 |
Peak memory | 319512 kb |
Host | smart-5007c7b4-4c85-4e97-bcea-3a35e2a7b97d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043332025 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi ple_keys.2043332025 |
Directory | /workspace/21.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access.2691738213 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 4856778574 ps |
CPU time | 20 seconds |
Started | Jul 20 06:13:29 PM PDT 24 |
Finished | Jul 20 06:13:50 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-82708bbc-1a78-49ed-a82d-e1cc9e8607b1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691738213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21. sram_ctrl_partial_access.2691738213 |
Directory | /workspace/21.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3105092289 |
Short name | T674 |
Test name | |
Test status | |
Simulation time | 9842903642 ps |
CPU time | 309.15 seconds |
Started | Jul 20 06:13:29 PM PDT 24 |
Finished | Jul 20 06:18:39 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-f4aa980b-2c93-4b0d-8494-250c07ddc216 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105092289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 21.sram_ctrl_partial_access_b2b.3105092289 |
Directory | /workspace/21.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_ram_cfg.1628469000 |
Short name | T651 |
Test name | |
Test status | |
Simulation time | 361064917 ps |
CPU time | 3.23 seconds |
Started | Jul 20 06:13:38 PM PDT 24 |
Finished | Jul 20 06:13:42 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-6dc846d2-7c89-4804-a1b5-9e976ff2b686 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628469000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.1628469000 |
Directory | /workspace/21.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_regwen.3320502849 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 4969540751 ps |
CPU time | 41.85 seconds |
Started | Jul 20 06:13:39 PM PDT 24 |
Finished | Jul 20 06:14:21 PM PDT 24 |
Peak memory | 219420 kb |
Host | smart-6f489394-a450-46b9-a91b-bc8e162f4020 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320502849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.3320502849 |
Directory | /workspace/21.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_smoke.1258126950 |
Short name | T616 |
Test name | |
Test status | |
Simulation time | 1634814822 ps |
CPU time | 9.94 seconds |
Started | Jul 20 06:13:31 PM PDT 24 |
Finished | Jul 20 06:13:42 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-3432fe2b-eab1-41e2-aa39-4b1695682512 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258126950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.1258126950 |
Directory | /workspace/21.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all.2268021937 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 538564659157 ps |
CPU time | 4559.14 seconds |
Started | Jul 20 06:13:38 PM PDT 24 |
Finished | Jul 20 07:29:38 PM PDT 24 |
Peak memory | 387976 kb |
Host | smart-d5ec079d-8fee-45c1-9ec2-dafb017ba1b1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268021937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.sram_ctrl_stress_all.2268021937 |
Directory | /workspace/21.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2712747055 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 3570765521 ps |
CPU time | 150.3 seconds |
Started | Jul 20 06:13:50 PM PDT 24 |
Finished | Jul 20 06:16:20 PM PDT 24 |
Peak memory | 329788 kb |
Host | smart-445b83fd-aa43-45f9-846d-1a12e6bf2232 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2712747055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_stress_all_with_rand_reset.2712747055 |
Directory | /workspace/21.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_stress_pipeline.3745118607 |
Short name | T678 |
Test name | |
Test status | |
Simulation time | 8421407518 ps |
CPU time | 184.33 seconds |
Started | Jul 20 06:13:32 PM PDT 24 |
Finished | Jul 20 06:16:37 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-dd70c3e1-4a8c-4d52-bdd3-d956a1268405 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745118607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 1.sram_ctrl_stress_pipeline.3745118607 |
Directory | /workspace/21.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.3396468524 |
Short name | T630 |
Test name | |
Test status | |
Simulation time | 720594317 ps |
CPU time | 12.28 seconds |
Started | Jul 20 06:13:27 PM PDT 24 |
Finished | Jul 20 06:13:40 PM PDT 24 |
Peak memory | 235728 kb |
Host | smart-1719006a-b384-43b4-9e4f-0a36072c49b7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396468524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sram_ctrl_throughput_w_partial_write.3396468524 |
Directory | /workspace/21.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_access_during_key_req.3760634305 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 4387679957 ps |
CPU time | 293.93 seconds |
Started | Jul 20 06:13:37 PM PDT 24 |
Finished | Jul 20 06:18:31 PM PDT 24 |
Peak memory | 366416 kb |
Host | smart-642ae971-ad72-4e79-a6e8-48caa12bf5e0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760634305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 22.sram_ctrl_access_during_key_req.3760634305 |
Directory | /workspace/22.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_alert_test.3088195427 |
Short name | T694 |
Test name | |
Test status | |
Simulation time | 18957828 ps |
CPU time | 0.62 seconds |
Started | Jul 20 06:13:45 PM PDT 24 |
Finished | Jul 20 06:13:46 PM PDT 24 |
Peak memory | 202656 kb |
Host | smart-62ba1c8a-0451-49a2-8f09-5c32a46792b9 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088195427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_alert_test.3088195427 |
Directory | /workspace/22.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_bijection.431943775 |
Short name | T768 |
Test name | |
Test status | |
Simulation time | 22685164130 ps |
CPU time | 1591.35 seconds |
Started | Jul 20 06:13:38 PM PDT 24 |
Finished | Jul 20 06:40:10 PM PDT 24 |
Peak memory | 203684 kb |
Host | smart-e1df922b-1b52-4b11-828f-5feb7add5464 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431943775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection. 431943775 |
Directory | /workspace/22.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_executable.3528474027 |
Short name | T872 |
Test name | |
Test status | |
Simulation time | 62533107950 ps |
CPU time | 1108.36 seconds |
Started | Jul 20 06:13:45 PM PDT 24 |
Finished | Jul 20 06:32:14 PM PDT 24 |
Peak memory | 379368 kb |
Host | smart-96dbd740-8482-4a56-b414-893d534798ad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528474027 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab le.3528474027 |
Directory | /workspace/22.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_lc_escalation.3976337126 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 6368472165 ps |
CPU time | 47.59 seconds |
Started | Jul 20 06:13:35 PM PDT 24 |
Finished | Jul 20 06:14:23 PM PDT 24 |
Peak memory | 203072 kb |
Host | smart-769f595a-03ea-4f89-acb4-abe6e2e12445 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976337126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es calation.3976337126 |
Directory | /workspace/22.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_max_throughput.2394695015 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 3055388753 ps |
CPU time | 169.66 seconds |
Started | Jul 20 06:13:34 PM PDT 24 |
Finished | Jul 20 06:16:25 PM PDT 24 |
Peak memory | 372580 kb |
Host | smart-11f53332-2464-4881-8619-238dd6a65d96 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394695015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 22.sram_ctrl_max_throughput.2394695015 |
Directory | /workspace/22.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_partial_access.4067255677 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 2439760445 ps |
CPU time | 152.84 seconds |
Started | Jul 20 06:13:45 PM PDT 24 |
Finished | Jul 20 06:16:19 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-6c9f15c1-75f3-4d64-970b-a9d4874cb5c5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067255677 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_mem_partial_access.4067255677 |
Directory | /workspace/22.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_mem_walk.899065210 |
Short name | T604 |
Test name | |
Test status | |
Simulation time | 4064617690 ps |
CPU time | 247.71 seconds |
Started | Jul 20 06:13:34 PM PDT 24 |
Finished | Jul 20 06:17:42 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-42bd47b1-188a-4b66-95ae-dcb27446d0d4 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899065210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl _mem_walk.899065210 |
Directory | /workspace/22.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_multiple_keys.1013562915 |
Short name | T932 |
Test name | |
Test status | |
Simulation time | 88400440192 ps |
CPU time | 987.05 seconds |
Started | Jul 20 06:13:38 PM PDT 24 |
Finished | Jul 20 06:30:06 PM PDT 24 |
Peak memory | 377904 kb |
Host | smart-66553cbc-8153-4d2b-af22-f8cd3ac42955 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013562915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi ple_keys.1013562915 |
Directory | /workspace/22.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access.4069155814 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 673050455 ps |
CPU time | 29.54 seconds |
Started | Jul 20 06:13:34 PM PDT 24 |
Finished | Jul 20 06:14:05 PM PDT 24 |
Peak memory | 278444 kb |
Host | smart-e2d009db-0125-41e5-8101-98ee47f63f37 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069155814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22. sram_ctrl_partial_access.4069155814 |
Directory | /workspace/22.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.655527667 |
Short name | T887 |
Test name | |
Test status | |
Simulation time | 23294625599 ps |
CPU time | 500.44 seconds |
Started | Jul 20 06:13:38 PM PDT 24 |
Finished | Jul 20 06:21:59 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-50c57663-998b-4fa3-aac4-497c5d3d7524 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655527667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 22.sram_ctrl_partial_access_b2b.655527667 |
Directory | /workspace/22.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_ram_cfg.3794445473 |
Short name | T603 |
Test name | |
Test status | |
Simulation time | 1408384754 ps |
CPU time | 3.82 seconds |
Started | Jul 20 06:13:35 PM PDT 24 |
Finished | Jul 20 06:13:39 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-1a41b099-7c2b-40e8-8224-fecca47230e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794445473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.3794445473 |
Directory | /workspace/22.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_regwen.3349397513 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 2684408696 ps |
CPU time | 348.43 seconds |
Started | Jul 20 06:13:38 PM PDT 24 |
Finished | Jul 20 06:19:27 PM PDT 24 |
Peak memory | 376692 kb |
Host | smart-939a8e40-4663-468f-8616-9d9a858b2fcb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349397513 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.3349397513 |
Directory | /workspace/22.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_smoke.1047010581 |
Short name | T810 |
Test name | |
Test status | |
Simulation time | 871044601 ps |
CPU time | 23.19 seconds |
Started | Jul 20 06:13:38 PM PDT 24 |
Finished | Jul 20 06:14:01 PM PDT 24 |
Peak memory | 263700 kb |
Host | smart-791c4bac-3f01-47d8-b5b1-d43719b5646a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047010581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.1047010581 |
Directory | /workspace/22.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all.384762002 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 48255047426 ps |
CPU time | 2834.97 seconds |
Started | Jul 20 06:13:44 PM PDT 24 |
Finished | Jul 20 07:01:00 PM PDT 24 |
Peak memory | 378776 kb |
Host | smart-edcd6f32-8f0e-417c-9eb6-e901c795b0ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384762002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 22.sram_ctrl_stress_all.384762002 |
Directory | /workspace/22.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3739438457 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 3385727628 ps |
CPU time | 21.16 seconds |
Started | Jul 20 06:13:45 PM PDT 24 |
Finished | Jul 20 06:14:07 PM PDT 24 |
Peak memory | 211220 kb |
Host | smart-0885eaac-5136-459f-8e04-39e6850b535d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3739438457 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_stress_all_with_rand_reset.3739438457 |
Directory | /workspace/22.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_stress_pipeline.2658001406 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 9966142610 ps |
CPU time | 293.05 seconds |
Started | Jul 20 06:13:37 PM PDT 24 |
Finished | Jul 20 06:18:30 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-182cf434-dc39-42e2-b5eb-ad337861d378 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658001406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.sram_ctrl_stress_pipeline.2658001406 |
Directory | /workspace/22.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1203631946 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 784252390 ps |
CPU time | 50.1 seconds |
Started | Jul 20 06:13:37 PM PDT 24 |
Finished | Jul 20 06:14:28 PM PDT 24 |
Peak memory | 317344 kb |
Host | smart-7da6de83-cdf4-4c9f-ae3b-c8661ee9f353 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203631946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.1203631946 |
Directory | /workspace/22.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3285355164 |
Short name | T756 |
Test name | |
Test status | |
Simulation time | 66339789341 ps |
CPU time | 945.47 seconds |
Started | Jul 20 06:13:44 PM PDT 24 |
Finished | Jul 20 06:29:30 PM PDT 24 |
Peak memory | 376748 kb |
Host | smart-b82e3ab3-3ca3-412c-8337-70fb51e92038 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285355164 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 23.sram_ctrl_access_during_key_req.3285355164 |
Directory | /workspace/23.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_alert_test.240470933 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 36399409 ps |
CPU time | 0.67 seconds |
Started | Jul 20 06:13:53 PM PDT 24 |
Finished | Jul 20 06:13:54 PM PDT 24 |
Peak memory | 202444 kb |
Host | smart-b243013d-0474-4147-badd-c857249dcd1d |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240470933 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_alert_test.240470933 |
Directory | /workspace/23.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_bijection.2601638549 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 288117570883 ps |
CPU time | 1236.27 seconds |
Started | Jul 20 06:13:43 PM PDT 24 |
Finished | Jul 20 06:34:20 PM PDT 24 |
Peak memory | 203504 kb |
Host | smart-72b4a63f-36ed-48bb-9274-6d00f4cc9a7e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601638549 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection .2601638549 |
Directory | /workspace/23.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_executable.1269920798 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 33529984351 ps |
CPU time | 961.26 seconds |
Started | Jul 20 06:13:43 PM PDT 24 |
Finished | Jul 20 06:29:45 PM PDT 24 |
Peak memory | 379744 kb |
Host | smart-6cdddba5-bd0b-47f7-a425-988864c12d90 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269920798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab le.1269920798 |
Directory | /workspace/23.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_lc_escalation.2173974471 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 15715433982 ps |
CPU time | 48.31 seconds |
Started | Jul 20 06:13:45 PM PDT 24 |
Finished | Jul 20 06:14:34 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-c7a1ad65-3dfd-45ba-b5e1-a795c28e6e53 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173974471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_es calation.2173974471 |
Directory | /workspace/23.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_max_throughput.368872530 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 2898992553 ps |
CPU time | 55.63 seconds |
Started | Jul 20 06:13:44 PM PDT 24 |
Finished | Jul 20 06:14:40 PM PDT 24 |
Peak memory | 301016 kb |
Host | smart-bf1483b8-3b7c-4135-8503-e523bd96c587 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368872530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.sram_ctrl_max_throughput.368872530 |
Directory | /workspace/23.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_partial_access.1600812548 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 12759144012 ps |
CPU time | 88.41 seconds |
Started | Jul 20 06:13:53 PM PDT 24 |
Finished | Jul 20 06:15:22 PM PDT 24 |
Peak memory | 219244 kb |
Host | smart-454d05aa-1c26-441b-8aff-f29632b71980 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600812548 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_mem_partial_access.1600812548 |
Directory | /workspace/23.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_mem_walk.464662859 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 276401688339 ps |
CPU time | 363.38 seconds |
Started | Jul 20 06:13:50 PM PDT 24 |
Finished | Jul 20 06:19:54 PM PDT 24 |
Peak memory | 211800 kb |
Host | smart-9e00a928-7309-4243-845d-23570fb1981d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464662859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl _mem_walk.464662859 |
Directory | /workspace/23.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_multiple_keys.754301117 |
Short name | T792 |
Test name | |
Test status | |
Simulation time | 39414179369 ps |
CPU time | 331.9 seconds |
Started | Jul 20 06:13:45 PM PDT 24 |
Finished | Jul 20 06:19:18 PM PDT 24 |
Peak memory | 346020 kb |
Host | smart-7e18b401-28fa-4a9d-9cef-e1ccc037fd16 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754301117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multip le_keys.754301117 |
Directory | /workspace/23.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access.2182284043 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 787108025 ps |
CPU time | 11.47 seconds |
Started | Jul 20 06:13:46 PM PDT 24 |
Finished | Jul 20 06:13:58 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-25880414-7c3b-45be-b4ba-e09756b2eed2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182284043 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23. sram_ctrl_partial_access.2182284043 |
Directory | /workspace/23.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3156663737 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 30806112540 ps |
CPU time | 213.03 seconds |
Started | Jul 20 06:13:43 PM PDT 24 |
Finished | Jul 20 06:17:17 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-784ac858-e769-43eb-9295-f735f835be03 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156663737 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 23.sram_ctrl_partial_access_b2b.3156663737 |
Directory | /workspace/23.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_ram_cfg.479224679 |
Short name | T693 |
Test name | |
Test status | |
Simulation time | 2001785394 ps |
CPU time | 3.67 seconds |
Started | Jul 20 06:13:47 PM PDT 24 |
Finished | Jul 20 06:13:51 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-167a0a2c-38a5-4634-80ff-4fc97ec5ca3d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479224679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.479224679 |
Directory | /workspace/23.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_regwen.2535904092 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 209269765091 ps |
CPU time | 1424.43 seconds |
Started | Jul 20 06:13:45 PM PDT 24 |
Finished | Jul 20 06:37:30 PM PDT 24 |
Peak memory | 378124 kb |
Host | smart-a522a24e-8b21-49ef-a649-171a6c96dcf1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535904092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.2535904092 |
Directory | /workspace/23.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_smoke.1785910729 |
Short name | T628 |
Test name | |
Test status | |
Simulation time | 770489517 ps |
CPU time | 19.06 seconds |
Started | Jul 20 06:13:44 PM PDT 24 |
Finished | Jul 20 06:14:03 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-38e27727-fd3b-4ea3-9930-21143bfe3d19 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785910729 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.1785910729 |
Directory | /workspace/23.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all.3496663595 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 405784246142 ps |
CPU time | 8117.73 seconds |
Started | Jul 20 06:13:56 PM PDT 24 |
Finished | Jul 20 08:29:15 PM PDT 24 |
Peak memory | 378764 kb |
Host | smart-34f40ebb-0a7e-40b0-9941-db4f1163ae8b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496663595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.sram_ctrl_stress_all.3496663595 |
Directory | /workspace/23.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.847240695 |
Short name | T821 |
Test name | |
Test status | |
Simulation time | 296096785 ps |
CPU time | 9.01 seconds |
Started | Jul 20 06:13:54 PM PDT 24 |
Finished | Jul 20 06:14:03 PM PDT 24 |
Peak memory | 211252 kb |
Host | smart-a4dfd583-6256-491c-bf8d-34c27942f4ae |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=847240695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_stress_all_with_rand_reset.847240695 |
Directory | /workspace/23.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_stress_pipeline.3865729156 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 2917288579 ps |
CPU time | 224.55 seconds |
Started | Jul 20 06:13:45 PM PDT 24 |
Finished | Jul 20 06:17:30 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-6caa6820-c6bb-4583-8968-ccd7b9ca2f55 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865729156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.sram_ctrl_stress_pipeline.3865729156 |
Directory | /workspace/23.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.4218765499 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 9297090372 ps |
CPU time | 61.76 seconds |
Started | Jul 20 06:13:44 PM PDT 24 |
Finished | Jul 20 06:14:47 PM PDT 24 |
Peak memory | 313216 kb |
Host | smart-c3e14238-a44d-461f-bc4b-bd3c5f8c9f05 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218765499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sram_ctrl_throughput_w_partial_write.4218765499 |
Directory | /workspace/23.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_access_during_key_req.2068661800 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 45730248938 ps |
CPU time | 1298.72 seconds |
Started | Jul 20 06:13:54 PM PDT 24 |
Finished | Jul 20 06:35:34 PM PDT 24 |
Peak memory | 379872 kb |
Host | smart-fbf60109-68e9-4838-8260-98e652373b33 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068661800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 24.sram_ctrl_access_during_key_req.2068661800 |
Directory | /workspace/24.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_alert_test.1869651554 |
Short name | T653 |
Test name | |
Test status | |
Simulation time | 15041324 ps |
CPU time | 0.69 seconds |
Started | Jul 20 06:14:05 PM PDT 24 |
Finished | Jul 20 06:14:07 PM PDT 24 |
Peak memory | 202656 kb |
Host | smart-567f1df3-9457-49c5-b5e2-c6bc4ce25e9c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869651554 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_alert_test.1869651554 |
Directory | /workspace/24.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_bijection.2797375469 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 316838640892 ps |
CPU time | 1289.87 seconds |
Started | Jul 20 06:13:56 PM PDT 24 |
Finished | Jul 20 06:35:26 PM PDT 24 |
Peak memory | 203668 kb |
Host | smart-7d8472a5-c2bd-443c-8d32-0f7bc95a086e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797375469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection .2797375469 |
Directory | /workspace/24.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_executable.4035431262 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 79776894542 ps |
CPU time | 834.49 seconds |
Started | Jul 20 06:13:53 PM PDT 24 |
Finished | Jul 20 06:27:48 PM PDT 24 |
Peak memory | 378732 kb |
Host | smart-82f7f8c3-434f-4c94-b3e3-fe3f472c69e4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035431262 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab le.4035431262 |
Directory | /workspace/24.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_lc_escalation.71209022 |
Short name | T636 |
Test name | |
Test status | |
Simulation time | 41258551137 ps |
CPU time | 63.48 seconds |
Started | Jul 20 06:13:56 PM PDT 24 |
Finished | Jul 20 06:15:00 PM PDT 24 |
Peak memory | 216176 kb |
Host | smart-425d3e85-3ac9-45c1-a297-d9891ab2ec38 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71209022 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_esca lation.71209022 |
Directory | /workspace/24.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_max_throughput.732591305 |
Short name | T581 |
Test name | |
Test status | |
Simulation time | 1498784165 ps |
CPU time | 74.34 seconds |
Started | Jul 20 06:13:52 PM PDT 24 |
Finished | Jul 20 06:15:06 PM PDT 24 |
Peak memory | 313268 kb |
Host | smart-121db822-18e8-473d-a80a-fdcde73d9fe2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732591305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.sram_ctrl_max_throughput.732591305 |
Directory | /workspace/24.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_partial_access.3904012461 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 1713114202 ps |
CPU time | 133.91 seconds |
Started | Jul 20 06:14:05 PM PDT 24 |
Finished | Jul 20 06:16:19 PM PDT 24 |
Peak memory | 210956 kb |
Host | smart-1952e18c-01d0-47fd-8afb-818631583ec4 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904012461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 4.sram_ctrl_mem_partial_access.3904012461 |
Directory | /workspace/24.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_mem_walk.2054926611 |
Short name | T632 |
Test name | |
Test status | |
Simulation time | 7213509773 ps |
CPU time | 169.23 seconds |
Started | Jul 20 06:14:04 PM PDT 24 |
Finished | Jul 20 06:16:54 PM PDT 24 |
Peak memory | 211024 kb |
Host | smart-5f5525c0-ce45-4105-9943-ad970f22fb0a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054926611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr l_mem_walk.2054926611 |
Directory | /workspace/24.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_multiple_keys.834323593 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 6700629065 ps |
CPU time | 352.27 seconds |
Started | Jul 20 06:13:54 PM PDT 24 |
Finished | Jul 20 06:19:47 PM PDT 24 |
Peak memory | 363368 kb |
Host | smart-9e0782a4-ca30-4120-91aa-4cccae0804d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834323593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multip le_keys.834323593 |
Directory | /workspace/24.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access.1646831201 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 2846070851 ps |
CPU time | 21.24 seconds |
Started | Jul 20 06:13:54 PM PDT 24 |
Finished | Jul 20 06:14:16 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-bb07ed2d-dd20-4e52-89b1-d52db56e676c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646831201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24. sram_ctrl_partial_access.1646831201 |
Directory | /workspace/24.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.3354770329 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 20650499820 ps |
CPU time | 277.93 seconds |
Started | Jul 20 06:13:54 PM PDT 24 |
Finished | Jul 20 06:18:33 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-cec12f47-d55a-4bd1-8f76-7aedd84f3a37 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354770329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 24.sram_ctrl_partial_access_b2b.3354770329 |
Directory | /workspace/24.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_ram_cfg.2387401822 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 346882954 ps |
CPU time | 3.12 seconds |
Started | Jul 20 06:14:01 PM PDT 24 |
Finished | Jul 20 06:14:04 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-218829ac-79c1-4014-bd05-a2787f73f49d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387401822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2387401822 |
Directory | /workspace/24.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_regwen.768829281 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 40696042671 ps |
CPU time | 730.76 seconds |
Started | Jul 20 06:13:55 PM PDT 24 |
Finished | Jul 20 06:26:06 PM PDT 24 |
Peak memory | 377724 kb |
Host | smart-1192d16d-8a3b-4e76-a439-9962b20270d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768829281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.768829281 |
Directory | /workspace/24.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_smoke.2331197884 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 1388111547 ps |
CPU time | 140.07 seconds |
Started | Jul 20 06:13:56 PM PDT 24 |
Finished | Jul 20 06:16:16 PM PDT 24 |
Peak memory | 370424 kb |
Host | smart-44187b19-da70-426b-931a-8d25394a79fc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331197884 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.2331197884 |
Directory | /workspace/24.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all.1425713956 |
Short name | T620 |
Test name | |
Test status | |
Simulation time | 319331625420 ps |
CPU time | 7300.64 seconds |
Started | Jul 20 06:14:06 PM PDT 24 |
Finished | Jul 20 08:15:49 PM PDT 24 |
Peak memory | 378840 kb |
Host | smart-f2f6275c-565f-42ca-8912-8e3d9cc10b18 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425713956 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.sram_ctrl_stress_all.1425713956 |
Directory | /workspace/24.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3885176182 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 7418376335 ps |
CPU time | 51.17 seconds |
Started | Jul 20 06:14:05 PM PDT 24 |
Finished | Jul 20 06:14:57 PM PDT 24 |
Peak memory | 211224 kb |
Host | smart-a40675c6-04ef-496a-9778-30239417cf1e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3885176182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_stress_all_with_rand_reset.3885176182 |
Directory | /workspace/24.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_stress_pipeline.457511547 |
Short name | T786 |
Test name | |
Test status | |
Simulation time | 22928781014 ps |
CPU time | 337.37 seconds |
Started | Jul 20 06:13:54 PM PDT 24 |
Finished | Jul 20 06:19:32 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-21623789-816f-42a7-afab-d58ff7ce777a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457511547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24 .sram_ctrl_stress_pipeline.457511547 |
Directory | /workspace/24.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1796785888 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 5349530863 ps |
CPU time | 13.05 seconds |
Started | Jul 20 06:13:53 PM PDT 24 |
Finished | Jul 20 06:14:06 PM PDT 24 |
Peak memory | 237756 kb |
Host | smart-9b67b244-6a73-4bc1-830b-e7b846fe37b8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796785888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1796785888 |
Directory | /workspace/24.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2216657963 |
Short name | T891 |
Test name | |
Test status | |
Simulation time | 38725601497 ps |
CPU time | 739.69 seconds |
Started | Jul 20 06:14:04 PM PDT 24 |
Finished | Jul 20 06:26:25 PM PDT 24 |
Peak memory | 371664 kb |
Host | smart-6ba8753e-0626-4d00-9a9d-f3245e85caba |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216657963 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 25.sram_ctrl_access_during_key_req.2216657963 |
Directory | /workspace/25.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_alert_test.4279190242 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 32833225 ps |
CPU time | 0.72 seconds |
Started | Jul 20 06:14:13 PM PDT 24 |
Finished | Jul 20 06:14:14 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-2e962ee4-2439-4079-9b3b-53f379ccbbbd |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279190242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_alert_test.4279190242 |
Directory | /workspace/25.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_executable.1063405754 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 21993842921 ps |
CPU time | 209.58 seconds |
Started | Jul 20 06:14:00 PM PDT 24 |
Finished | Jul 20 06:17:30 PM PDT 24 |
Peak memory | 351148 kb |
Host | smart-db073ab6-a96c-4500-b25c-635f85cbe178 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063405754 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executab le.1063405754 |
Directory | /workspace/25.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_lc_escalation.3200012321 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 14887832658 ps |
CPU time | 20.69 seconds |
Started | Jul 20 06:14:04 PM PDT 24 |
Finished | Jul 20 06:14:26 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-3a5d563f-c1ff-4915-a3e4-35e079925fd5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200012321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_es calation.3200012321 |
Directory | /workspace/25.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_max_throughput.1207702897 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 5818746350 ps |
CPU time | 21.6 seconds |
Started | Jul 20 06:14:04 PM PDT 24 |
Finished | Jul 20 06:14:26 PM PDT 24 |
Peak memory | 259512 kb |
Host | smart-d52aa081-cfd6-47a7-83d4-154c2974ac88 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207702897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 25.sram_ctrl_max_throughput.1207702897 |
Directory | /workspace/25.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2934209654 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 5801843480 ps |
CPU time | 77.16 seconds |
Started | Jul 20 06:14:05 PM PDT 24 |
Finished | Jul 20 06:15:23 PM PDT 24 |
Peak memory | 219236 kb |
Host | smart-e3182526-bb0c-4209-ac32-3a39a41feeda |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934209654 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_mem_partial_access.2934209654 |
Directory | /workspace/25.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_mem_walk.2619032629 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 10500734429 ps |
CPU time | 317.51 seconds |
Started | Jul 20 06:14:05 PM PDT 24 |
Finished | Jul 20 06:19:24 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-3ff702a8-9bd2-44d1-8199-2a93d46cb07e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619032629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctr l_mem_walk.2619032629 |
Directory | /workspace/25.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_multiple_keys.3823506657 |
Short name | T666 |
Test name | |
Test status | |
Simulation time | 32576892296 ps |
CPU time | 688.59 seconds |
Started | Jul 20 06:14:04 PM PDT 24 |
Finished | Jul 20 06:25:34 PM PDT 24 |
Peak memory | 378760 kb |
Host | smart-65cfd6e0-70a1-4acf-89ff-5e52ecd01729 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823506657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multi ple_keys.3823506657 |
Directory | /workspace/25.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access.3153637055 |
Short name | T875 |
Test name | |
Test status | |
Simulation time | 1035473354 ps |
CPU time | 13.16 seconds |
Started | Jul 20 06:14:05 PM PDT 24 |
Finished | Jul 20 06:14:19 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-6e1596e6-ece4-43fe-a04b-2ca04a5dffa8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153637055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25. sram_ctrl_partial_access.3153637055 |
Directory | /workspace/25.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.4288134506 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 16612669610 ps |
CPU time | 396.16 seconds |
Started | Jul 20 06:14:04 PM PDT 24 |
Finished | Jul 20 06:20:41 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-0d13039a-0d51-4aa9-a6a5-ebaaafcf9e5a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288134506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 25.sram_ctrl_partial_access_b2b.4288134506 |
Directory | /workspace/25.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_ram_cfg.1516538356 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 1532093726 ps |
CPU time | 3.79 seconds |
Started | Jul 20 06:14:03 PM PDT 24 |
Finished | Jul 20 06:14:08 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-4fd1fba4-d81e-44fa-9d70-8dcbca3156c9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516538356 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.1516538356 |
Directory | /workspace/25.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_regwen.3238054208 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 81647846710 ps |
CPU time | 894.06 seconds |
Started | Jul 20 06:13:59 PM PDT 24 |
Finished | Jul 20 06:28:54 PM PDT 24 |
Peak memory | 376676 kb |
Host | smart-62e1d805-a1b8-49d8-9361-f269ad419b7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238054208 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.3238054208 |
Directory | /workspace/25.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_smoke.2772029761 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 730232850 ps |
CPU time | 9.58 seconds |
Started | Jul 20 06:14:01 PM PDT 24 |
Finished | Jul 20 06:14:11 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-cc8aa8d5-f076-43da-92cf-9bb9fb17ba6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772029761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2772029761 |
Directory | /workspace/25.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.4127768494 |
Short name | T870 |
Test name | |
Test status | |
Simulation time | 19279451586 ps |
CPU time | 42.03 seconds |
Started | Jul 20 06:14:04 PM PDT 24 |
Finished | Jul 20 06:14:46 PM PDT 24 |
Peak memory | 212976 kb |
Host | smart-5ef40f10-7a19-49d4-9dea-9ef9e067ed9d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4127768494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_stress_all_with_rand_reset.4127768494 |
Directory | /workspace/25.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_stress_pipeline.2768521580 |
Short name | T794 |
Test name | |
Test status | |
Simulation time | 4273099066 ps |
CPU time | 237.77 seconds |
Started | Jul 20 06:14:04 PM PDT 24 |
Finished | Jul 20 06:18:03 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-8619887f-5e1c-45e9-9ca6-5aa9cd332bee |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768521580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.sram_ctrl_stress_pipeline.2768521580 |
Directory | /workspace/25.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.2560896428 |
Short name | T762 |
Test name | |
Test status | |
Simulation time | 1479278108 ps |
CPU time | 58.68 seconds |
Started | Jul 20 06:14:04 PM PDT 24 |
Finished | Jul 20 06:15:04 PM PDT 24 |
Peak memory | 302072 kb |
Host | smart-5fbbd210-37ef-4653-8867-86dde9b9e317 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560896428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 25.sram_ctrl_throughput_w_partial_write.2560896428 |
Directory | /workspace/25.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_access_during_key_req.2248478626 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 11929618125 ps |
CPU time | 1116.61 seconds |
Started | Jul 20 06:14:11 PM PDT 24 |
Finished | Jul 20 06:32:48 PM PDT 24 |
Peak memory | 370564 kb |
Host | smart-ae874d2d-65e3-406c-9754-99d2e44e3351 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248478626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 26.sram_ctrl_access_during_key_req.2248478626 |
Directory | /workspace/26.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_alert_test.4021042628 |
Short name | T886 |
Test name | |
Test status | |
Simulation time | 40185489 ps |
CPU time | 0.69 seconds |
Started | Jul 20 06:14:14 PM PDT 24 |
Finished | Jul 20 06:14:15 PM PDT 24 |
Peak memory | 202684 kb |
Host | smart-9de2bfe1-37bb-40ca-8504-e60fdae42a8f |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021042628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_alert_test.4021042628 |
Directory | /workspace/26.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_bijection.1312840453 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 32806826465 ps |
CPU time | 595.16 seconds |
Started | Jul 20 06:14:07 PM PDT 24 |
Finished | Jul 20 06:24:03 PM PDT 24 |
Peak memory | 203184 kb |
Host | smart-53df0a3f-d109-4dc3-95e3-f2f357b4c73f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312840453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection .1312840453 |
Directory | /workspace/26.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_executable.695397560 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 10058090941 ps |
CPU time | 706.07 seconds |
Started | Jul 20 06:14:11 PM PDT 24 |
Finished | Jul 20 06:25:58 PM PDT 24 |
Peak memory | 374684 kb |
Host | smart-de248b24-6ec0-4ab9-ad70-2697725348c8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695397560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executabl e.695397560 |
Directory | /workspace/26.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_lc_escalation.703596462 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 2085291115 ps |
CPU time | 13.2 seconds |
Started | Jul 20 06:14:12 PM PDT 24 |
Finished | Jul 20 06:14:26 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-720aa882-b9a6-4a97-8b34-e2b7f229a82a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703596462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_lc_esc alation.703596462 |
Directory | /workspace/26.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_max_throughput.3574404292 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 816008451 ps |
CPU time | 20.83 seconds |
Started | Jul 20 06:14:09 PM PDT 24 |
Finished | Jul 20 06:14:30 PM PDT 24 |
Peak memory | 268296 kb |
Host | smart-480bc556-e2a5-4100-87e7-97b5e63b8714 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574404292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_max_throughput.3574404292 |
Directory | /workspace/26.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_partial_access.495780804 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 12257520624 ps |
CPU time | 85.23 seconds |
Started | Jul 20 06:14:12 PM PDT 24 |
Finished | Jul 20 06:15:38 PM PDT 24 |
Peak memory | 219192 kb |
Host | smart-b8fd7ba0-956f-44b3-ae3c-42d9b9d376ad |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495780804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26 .sram_ctrl_mem_partial_access.495780804 |
Directory | /workspace/26.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_mem_walk.1152139692 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 68996846379 ps |
CPU time | 384.56 seconds |
Started | Jul 20 06:14:11 PM PDT 24 |
Finished | Jul 20 06:20:36 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-e4b55967-1466-4692-ba4e-2da6c74302ae |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152139692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctr l_mem_walk.1152139692 |
Directory | /workspace/26.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_multiple_keys.3473453978 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 69906609719 ps |
CPU time | 2088.59 seconds |
Started | Jul 20 06:14:14 PM PDT 24 |
Finished | Jul 20 06:49:04 PM PDT 24 |
Peak memory | 380136 kb |
Host | smart-d7b05ebe-62a7-4310-a7d3-89545f6eae7b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473453978 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi ple_keys.3473453978 |
Directory | /workspace/26.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access.3339850777 |
Short name | T847 |
Test name | |
Test status | |
Simulation time | 2623168322 ps |
CPU time | 9.97 seconds |
Started | Jul 20 06:14:10 PM PDT 24 |
Finished | Jul 20 06:14:20 PM PDT 24 |
Peak memory | 202952 kb |
Host | smart-c8ca30ac-5c82-4487-871d-493dc45cbe53 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339850777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26. sram_ctrl_partial_access.3339850777 |
Directory | /workspace/26.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3908483298 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 10961037235 ps |
CPU time | 285.97 seconds |
Started | Jul 20 06:14:14 PM PDT 24 |
Finished | Jul 20 06:19:01 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-44df2c6c-1be8-4ba4-bf6d-411b788cc738 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908483298 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_partial_access_b2b.3908483298 |
Directory | /workspace/26.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_ram_cfg.3451696343 |
Short name | T919 |
Test name | |
Test status | |
Simulation time | 365828574 ps |
CPU time | 3.32 seconds |
Started | Jul 20 06:14:12 PM PDT 24 |
Finished | Jul 20 06:14:16 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-61cd91e4-daa2-4df0-bdf4-49f188ce2eac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451696343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.3451696343 |
Directory | /workspace/26.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_regwen.3820282484 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 60394123210 ps |
CPU time | 1025.49 seconds |
Started | Jul 20 06:14:13 PM PDT 24 |
Finished | Jul 20 06:31:20 PM PDT 24 |
Peak memory | 374640 kb |
Host | smart-6f39606a-d0b4-43a9-9083-ab88ce441301 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820282484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.3820282484 |
Directory | /workspace/26.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_smoke.3407527179 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 806149266 ps |
CPU time | 15.86 seconds |
Started | Jul 20 06:14:08 PM PDT 24 |
Finished | Jul 20 06:14:25 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-953bb9dc-42be-4bc7-a494-584fbf9726c1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407527179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.3407527179 |
Directory | /workspace/26.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all.721553822 |
Short name | T727 |
Test name | |
Test status | |
Simulation time | 89354279348 ps |
CPU time | 5196.26 seconds |
Started | Jul 20 06:14:09 PM PDT 24 |
Finished | Jul 20 07:40:46 PM PDT 24 |
Peak memory | 381892 kb |
Host | smart-ea4cb78f-90f4-4f00-a6b0-b8f9b64c5a92 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721553822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.sram_ctrl_stress_all.721553822 |
Directory | /workspace/26.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3859629390 |
Short name | T829 |
Test name | |
Test status | |
Simulation time | 10516399253 ps |
CPU time | 184.53 seconds |
Started | Jul 20 06:14:09 PM PDT 24 |
Finished | Jul 20 06:17:14 PM PDT 24 |
Peak memory | 364856 kb |
Host | smart-c815e5bc-dc1e-4df3-bb17-b16d1b2476bc |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3859629390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_stress_all_with_rand_reset.3859629390 |
Directory | /workspace/26.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_stress_pipeline.2237914603 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 4905402669 ps |
CPU time | 352.37 seconds |
Started | Jul 20 06:14:12 PM PDT 24 |
Finished | Jul 20 06:20:05 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-b7a7862e-e657-4779-a49c-07b84c2bbf7f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237914603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.sram_ctrl_stress_pipeline.2237914603 |
Directory | /workspace/26.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.803189300 |
Short name | T900 |
Test name | |
Test status | |
Simulation time | 737137999 ps |
CPU time | 37.6 seconds |
Started | Jul 20 06:14:14 PM PDT 24 |
Finished | Jul 20 06:14:52 PM PDT 24 |
Peak memory | 287716 kb |
Host | smart-93b72c6f-aa07-467a-a57e-5d29b72492b1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803189300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 26.sram_ctrl_throughput_w_partial_write.803189300 |
Directory | /workspace/26.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1377666152 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 3818317631 ps |
CPU time | 194.6 seconds |
Started | Jul 20 06:14:19 PM PDT 24 |
Finished | Jul 20 06:17:34 PM PDT 24 |
Peak memory | 340948 kb |
Host | smart-a45d3cbe-b23b-4b00-a17c-51211f01760f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377666152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 27.sram_ctrl_access_during_key_req.1377666152 |
Directory | /workspace/27.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_alert_test.3853702081 |
Short name | T882 |
Test name | |
Test status | |
Simulation time | 16312039 ps |
CPU time | 0.67 seconds |
Started | Jul 20 06:14:21 PM PDT 24 |
Finished | Jul 20 06:14:22 PM PDT 24 |
Peak memory | 202480 kb |
Host | smart-2ea5adde-77dd-4ff0-8e80-0c6cecc20e9b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853702081 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_alert_test.3853702081 |
Directory | /workspace/27.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_bijection.2820308353 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 156927481960 ps |
CPU time | 1779.67 seconds |
Started | Jul 20 06:14:11 PM PDT 24 |
Finished | Jul 20 06:43:52 PM PDT 24 |
Peak memory | 203496 kb |
Host | smart-6d633c02-bb89-4a7d-b3cd-ad6df38d9aff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820308353 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection .2820308353 |
Directory | /workspace/27.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_executable.4060093731 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 21256288348 ps |
CPU time | 701.87 seconds |
Started | Jul 20 06:14:19 PM PDT 24 |
Finished | Jul 20 06:26:01 PM PDT 24 |
Peak memory | 369564 kb |
Host | smart-0b6bf799-0f05-41f4-a6e1-042f4afd4b8b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060093731 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab le.4060093731 |
Directory | /workspace/27.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_lc_escalation.3784896157 |
Short name | T775 |
Test name | |
Test status | |
Simulation time | 28908636987 ps |
CPU time | 55.57 seconds |
Started | Jul 20 06:14:18 PM PDT 24 |
Finished | Jul 20 06:15:15 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-a47fceb9-af46-4643-bfed-353337bab3f2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784896157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es calation.3784896157 |
Directory | /workspace/27.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_max_throughput.3638851200 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 1503460009 ps |
CPU time | 87.23 seconds |
Started | Jul 20 06:14:13 PM PDT 24 |
Finished | Jul 20 06:15:41 PM PDT 24 |
Peak memory | 335696 kb |
Host | smart-28928bd6-d304-4f86-a1b7-f25702fbd6b6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638851200 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_max_throughput.3638851200 |
Directory | /workspace/27.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2112473968 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 5046582707 ps |
CPU time | 156.67 seconds |
Started | Jul 20 06:14:20 PM PDT 24 |
Finished | Jul 20 06:16:57 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-bf9a5194-69d1-4733-90ef-bcef2a04cfe4 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112473968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.sram_ctrl_mem_partial_access.2112473968 |
Directory | /workspace/27.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_mem_walk.2326388796 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 4025162602 ps |
CPU time | 255.16 seconds |
Started | Jul 20 06:14:21 PM PDT 24 |
Finished | Jul 20 06:18:37 PM PDT 24 |
Peak memory | 211036 kb |
Host | smart-d3b08340-4279-4c5b-a088-a37d7b99fc39 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326388796 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr l_mem_walk.2326388796 |
Directory | /workspace/27.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_multiple_keys.770535093 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 105056399363 ps |
CPU time | 1718.14 seconds |
Started | Jul 20 06:14:08 PM PDT 24 |
Finished | Jul 20 06:42:47 PM PDT 24 |
Peak memory | 377872 kb |
Host | smart-f54c5efc-699c-46a5-9de4-960247bda0e0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770535093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multip le_keys.770535093 |
Directory | /workspace/27.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access.3494492498 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 3418577795 ps |
CPU time | 60.07 seconds |
Started | Jul 20 06:14:11 PM PDT 24 |
Finished | Jul 20 06:15:12 PM PDT 24 |
Peak memory | 316044 kb |
Host | smart-81f6ecd2-6742-427b-89ac-698fc911b905 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494492498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27. sram_ctrl_partial_access.3494492498 |
Directory | /workspace/27.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.3633629775 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 60259509182 ps |
CPU time | 234.66 seconds |
Started | Jul 20 06:14:09 PM PDT 24 |
Finished | Jul 20 06:18:04 PM PDT 24 |
Peak memory | 203080 kb |
Host | smart-c89db709-f2d7-4c69-ab46-cb7d3481d75c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633629775 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_partial_access_b2b.3633629775 |
Directory | /workspace/27.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_ram_cfg.1098107847 |
Short name | T791 |
Test name | |
Test status | |
Simulation time | 352159523 ps |
CPU time | 3.34 seconds |
Started | Jul 20 06:14:17 PM PDT 24 |
Finished | Jul 20 06:14:21 PM PDT 24 |
Peak memory | 203080 kb |
Host | smart-a011350f-c705-4ebf-916a-255b5ad19196 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098107847 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.1098107847 |
Directory | /workspace/27.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_regwen.2533549762 |
Short name | T901 |
Test name | |
Test status | |
Simulation time | 27532935852 ps |
CPU time | 1123.52 seconds |
Started | Jul 20 06:14:20 PM PDT 24 |
Finished | Jul 20 06:33:04 PM PDT 24 |
Peak memory | 372568 kb |
Host | smart-0af08022-fff0-47d0-8fcc-25005e4fc0ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533549762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.2533549762 |
Directory | /workspace/27.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_smoke.489947357 |
Short name | T578 |
Test name | |
Test status | |
Simulation time | 1053191188 ps |
CPU time | 35.89 seconds |
Started | Jul 20 06:14:12 PM PDT 24 |
Finished | Jul 20 06:14:49 PM PDT 24 |
Peak memory | 303108 kb |
Host | smart-cf19cc14-a1f5-45bb-97a0-bafb278c7ab6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489947357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.489947357 |
Directory | /workspace/27.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all.246808483 |
Short name | T878 |
Test name | |
Test status | |
Simulation time | 117736626166 ps |
CPU time | 2205.85 seconds |
Started | Jul 20 06:14:16 PM PDT 24 |
Finished | Jul 20 06:51:03 PM PDT 24 |
Peak memory | 204508 kb |
Host | smart-8a04ff66-cbe4-4a29-aa5a-64e033f8bb40 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246808483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 27.sram_ctrl_stress_all.246808483 |
Directory | /workspace/27.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.2827159078 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 2551017626 ps |
CPU time | 22.97 seconds |
Started | Jul 20 06:14:18 PM PDT 24 |
Finished | Jul 20 06:14:41 PM PDT 24 |
Peak memory | 211244 kb |
Host | smart-c3af0199-1c74-4ae8-9e7c-b68f044432fb |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2827159078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_stress_all_with_rand_reset.2827159078 |
Directory | /workspace/27.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_stress_pipeline.887816800 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 5171298921 ps |
CPU time | 342.98 seconds |
Started | Jul 20 06:14:10 PM PDT 24 |
Finished | Jul 20 06:19:53 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-22dbeaca-85f3-4012-a361-09b405361983 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887816800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27 .sram_ctrl_stress_pipeline.887816800 |
Directory | /workspace/27.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.583476394 |
Short name | T640 |
Test name | |
Test status | |
Simulation time | 3096010263 ps |
CPU time | 43.66 seconds |
Started | Jul 20 06:14:10 PM PDT 24 |
Finished | Jul 20 06:14:55 PM PDT 24 |
Peak memory | 291316 kb |
Host | smart-c3c9de98-52a8-431c-bac9-1f70afd44787 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583476394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 27.sram_ctrl_throughput_w_partial_write.583476394 |
Directory | /workspace/27.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_access_during_key_req.946561229 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 27047593906 ps |
CPU time | 856.08 seconds |
Started | Jul 20 06:14:28 PM PDT 24 |
Finished | Jul 20 06:28:45 PM PDT 24 |
Peak memory | 378860 kb |
Host | smart-20c0cfe1-dc7b-44e3-9ef9-10df945f86ff |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946561229 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 28.sram_ctrl_access_during_key_req.946561229 |
Directory | /workspace/28.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_alert_test.927052817 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 24211453 ps |
CPU time | 0.68 seconds |
Started | Jul 20 06:14:28 PM PDT 24 |
Finished | Jul 20 06:14:29 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-6919a372-0da4-48e7-bd61-6e57ed7d1b25 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927052817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_alert_test.927052817 |
Directory | /workspace/28.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_bijection.3929565560 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 64145768143 ps |
CPU time | 1100.45 seconds |
Started | Jul 20 06:14:19 PM PDT 24 |
Finished | Jul 20 06:32:41 PM PDT 24 |
Peak memory | 203528 kb |
Host | smart-98bf21a9-173e-4ae6-b32c-29b4d3534fd4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929565560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection .3929565560 |
Directory | /workspace/28.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_executable.1144562452 |
Short name | T883 |
Test name | |
Test status | |
Simulation time | 37724864960 ps |
CPU time | 1094.02 seconds |
Started | Jul 20 06:14:30 PM PDT 24 |
Finished | Jul 20 06:32:45 PM PDT 24 |
Peak memory | 377780 kb |
Host | smart-3aa440a9-4a24-4667-a325-e3c91b781227 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144562452 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab le.1144562452 |
Directory | /workspace/28.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_lc_escalation.3417987104 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 13604252525 ps |
CPU time | 89.64 seconds |
Started | Jul 20 06:14:29 PM PDT 24 |
Finished | Jul 20 06:15:59 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-4c039f27-a25a-44c2-a570-5b1c8153d18a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417987104 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es calation.3417987104 |
Directory | /workspace/28.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_max_throughput.1566528988 |
Short name | T802 |
Test name | |
Test status | |
Simulation time | 768267139 ps |
CPU time | 48.44 seconds |
Started | Jul 20 06:14:20 PM PDT 24 |
Finished | Jul 20 06:15:09 PM PDT 24 |
Peak memory | 301032 kb |
Host | smart-84f6a0b5-e83d-4751-8f31-185e9496bc0d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566528988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 28.sram_ctrl_max_throughput.1566528988 |
Directory | /workspace/28.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_partial_access.595868829 |
Short name | T845 |
Test name | |
Test status | |
Simulation time | 4547268087 ps |
CPU time | 76.66 seconds |
Started | Jul 20 06:14:29 PM PDT 24 |
Finished | Jul 20 06:15:47 PM PDT 24 |
Peak memory | 211112 kb |
Host | smart-eb482f21-7c74-48e2-871d-a1517692c9cc |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595868829 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28 .sram_ctrl_mem_partial_access.595868829 |
Directory | /workspace/28.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_mem_walk.2848120943 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 179215502903 ps |
CPU time | 413.76 seconds |
Started | Jul 20 06:14:28 PM PDT 24 |
Finished | Jul 20 06:21:22 PM PDT 24 |
Peak memory | 211144 kb |
Host | smart-9c2ced5f-2b20-41fe-8649-74f367f66df1 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848120943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr l_mem_walk.2848120943 |
Directory | /workspace/28.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_multiple_keys.989529784 |
Short name | T902 |
Test name | |
Test status | |
Simulation time | 18841183743 ps |
CPU time | 1170.57 seconds |
Started | Jul 20 06:14:17 PM PDT 24 |
Finished | Jul 20 06:33:48 PM PDT 24 |
Peak memory | 376940 kb |
Host | smart-9f5709e6-5dbd-44e3-b3e5-608c307cd8c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989529784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multip le_keys.989529784 |
Directory | /workspace/28.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access.936320711 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 649588044 ps |
CPU time | 24.57 seconds |
Started | Jul 20 06:14:19 PM PDT 24 |
Finished | Jul 20 06:14:44 PM PDT 24 |
Peak memory | 270288 kb |
Host | smart-0354df1e-8bf9-4748-8578-08b2b146cc86 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936320711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.s ram_ctrl_partial_access.936320711 |
Directory | /workspace/28.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.771272416 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 11403118312 ps |
CPU time | 278.88 seconds |
Started | Jul 20 06:14:19 PM PDT 24 |
Finished | Jul 20 06:18:59 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-4465630e-8329-4573-8c43-3d8b4739a45a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771272416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 28.sram_ctrl_partial_access_b2b.771272416 |
Directory | /workspace/28.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_ram_cfg.1618415882 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 366046320 ps |
CPU time | 3.04 seconds |
Started | Jul 20 06:14:26 PM PDT 24 |
Finished | Jul 20 06:14:29 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-810998c0-22a0-4325-8639-10c7b5041b96 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618415882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.1618415882 |
Directory | /workspace/28.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_regwen.3187331453 |
Short name | T936 |
Test name | |
Test status | |
Simulation time | 11219125019 ps |
CPU time | 729.24 seconds |
Started | Jul 20 06:14:26 PM PDT 24 |
Finished | Jul 20 06:26:36 PM PDT 24 |
Peak memory | 371556 kb |
Host | smart-36f7697e-c092-4aee-aec1-58898a0b4922 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187331453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.3187331453 |
Directory | /workspace/28.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_smoke.3447936645 |
Short name | T937 |
Test name | |
Test status | |
Simulation time | 810768737 ps |
CPU time | 138.48 seconds |
Started | Jul 20 06:14:21 PM PDT 24 |
Finished | Jul 20 06:16:40 PM PDT 24 |
Peak memory | 368408 kb |
Host | smart-3a2a84ee-18dd-44f0-9107-efc8872a31f8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447936645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.3447936645 |
Directory | /workspace/28.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all.2747904709 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 52807536319 ps |
CPU time | 2464.52 seconds |
Started | Jul 20 06:14:29 PM PDT 24 |
Finished | Jul 20 06:55:34 PM PDT 24 |
Peak memory | 376808 kb |
Host | smart-cae35511-6f77-48e6-b54c-11d060b88f85 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747904709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.sram_ctrl_stress_all.2747904709 |
Directory | /workspace/28.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1958732420 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 3437726876 ps |
CPU time | 48.1 seconds |
Started | Jul 20 06:14:30 PM PDT 24 |
Finished | Jul 20 06:15:18 PM PDT 24 |
Peak memory | 211164 kb |
Host | smart-6d9f23ca-bb8a-4532-add4-f8de3bdb3441 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1958732420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_stress_all_with_rand_reset.1958732420 |
Directory | /workspace/28.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_stress_pipeline.4276322080 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 7882209047 ps |
CPU time | 300.32 seconds |
Started | Jul 20 06:14:17 PM PDT 24 |
Finished | Jul 20 06:19:18 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-2d59336c-3d0e-442c-9f8d-5d1f2ee77b56 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276322080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 8.sram_ctrl_stress_pipeline.4276322080 |
Directory | /workspace/28.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.4131294789 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 4105880516 ps |
CPU time | 153.12 seconds |
Started | Jul 20 06:14:27 PM PDT 24 |
Finished | Jul 20 06:17:01 PM PDT 24 |
Peak memory | 371832 kb |
Host | smart-0c21c869-33e0-4d47-af6d-267f9876a206 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131294789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.4131294789 |
Directory | /workspace/28.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2596119674 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 20887541386 ps |
CPU time | 776.49 seconds |
Started | Jul 20 06:14:37 PM PDT 24 |
Finished | Jul 20 06:27:34 PM PDT 24 |
Peak memory | 375620 kb |
Host | smart-2087948b-9b65-450b-91c1-970f334a23d3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596119674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 29.sram_ctrl_access_during_key_req.2596119674 |
Directory | /workspace/29.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_alert_test.1767755961 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 21446836 ps |
CPU time | 0.65 seconds |
Started | Jul 20 06:14:38 PM PDT 24 |
Finished | Jul 20 06:14:39 PM PDT 24 |
Peak memory | 202580 kb |
Host | smart-4e6a9011-a6fe-4c4a-a7d3-32bfdecbb5c4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767755961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_alert_test.1767755961 |
Directory | /workspace/29.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_bijection.188843265 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 166002928754 ps |
CPU time | 1970.7 seconds |
Started | Jul 20 06:14:27 PM PDT 24 |
Finished | Jul 20 06:47:18 PM PDT 24 |
Peak memory | 203656 kb |
Host | smart-63da0949-6008-42c1-b9f1-9486ec2cc6eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188843265 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection. 188843265 |
Directory | /workspace/29.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_executable.1680255278 |
Short name | T822 |
Test name | |
Test status | |
Simulation time | 57768743593 ps |
CPU time | 1246.06 seconds |
Started | Jul 20 06:14:36 PM PDT 24 |
Finished | Jul 20 06:35:23 PM PDT 24 |
Peak memory | 376768 kb |
Host | smart-4f415148-abc7-4413-abee-849bfb73d116 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680255278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab le.1680255278 |
Directory | /workspace/29.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_lc_escalation.3452523814 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 8705668769 ps |
CPU time | 48.83 seconds |
Started | Jul 20 06:14:35 PM PDT 24 |
Finished | Jul 20 06:15:25 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-0be24168-488f-41e6-ae58-c6f4cf5f104b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452523814 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es calation.3452523814 |
Directory | /workspace/29.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_max_throughput.77236891 |
Short name | T893 |
Test name | |
Test status | |
Simulation time | 1480992210 ps |
CPU time | 35.48 seconds |
Started | Jul 20 06:14:38 PM PDT 24 |
Finished | Jul 20 06:15:14 PM PDT 24 |
Peak memory | 293768 kb |
Host | smart-d67c3df4-677a-44e0-b31d-6b98294abc10 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77236891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 29.sram_ctrl_max_throughput.77236891 |
Directory | /workspace/29.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_partial_access.3435578891 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 18191375865 ps |
CPU time | 76.57 seconds |
Started | Jul 20 06:14:36 PM PDT 24 |
Finished | Jul 20 06:15:53 PM PDT 24 |
Peak memory | 211400 kb |
Host | smart-954969b9-b499-437a-a405-af21b64a7625 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435578891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_mem_partial_access.3435578891 |
Directory | /workspace/29.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_mem_walk.1042975387 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 7357194344 ps |
CPU time | 162.68 seconds |
Started | Jul 20 06:14:36 PM PDT 24 |
Finished | Jul 20 06:17:19 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-a96374ad-edcc-465e-a1ce-48d532a952cc |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042975387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr l_mem_walk.1042975387 |
Directory | /workspace/29.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_multiple_keys.1473215821 |
Short name | T638 |
Test name | |
Test status | |
Simulation time | 1826602253 ps |
CPU time | 134.14 seconds |
Started | Jul 20 06:14:25 PM PDT 24 |
Finished | Jul 20 06:16:40 PM PDT 24 |
Peak memory | 370456 kb |
Host | smart-0d616662-ce2e-4dbd-a607-1b9f0bb75be1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473215821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi ple_keys.1473215821 |
Directory | /workspace/29.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access.2799568986 |
Short name | T755 |
Test name | |
Test status | |
Simulation time | 6653326292 ps |
CPU time | 14.59 seconds |
Started | Jul 20 06:14:35 PM PDT 24 |
Finished | Jul 20 06:14:50 PM PDT 24 |
Peak memory | 203064 kb |
Host | smart-f7081f8b-fe3a-49d0-9b9e-b00024ec1fae |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799568986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29. sram_ctrl_partial_access.2799568986 |
Directory | /workspace/29.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.4276828602 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 27964991225 ps |
CPU time | 408.34 seconds |
Started | Jul 20 06:14:33 PM PDT 24 |
Finished | Jul 20 06:21:22 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-c40a90bc-7295-4b35-8b46-f56f24ba212f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276828602 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_partial_access_b2b.4276828602 |
Directory | /workspace/29.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_ram_cfg.2675063184 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 1352156430 ps |
CPU time | 3.7 seconds |
Started | Jul 20 06:14:37 PM PDT 24 |
Finished | Jul 20 06:14:41 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-c27c3b1a-a833-49d7-914c-b5cbea798594 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675063184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.2675063184 |
Directory | /workspace/29.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_regwen.3174177608 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 70356613307 ps |
CPU time | 655.67 seconds |
Started | Jul 20 06:14:34 PM PDT 24 |
Finished | Jul 20 06:25:30 PM PDT 24 |
Peak memory | 372616 kb |
Host | smart-4ba7f4b6-dabd-48c6-9df6-1ba6d5d95e1e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174177608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.3174177608 |
Directory | /workspace/29.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_smoke.979991702 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 1446778245 ps |
CPU time | 12 seconds |
Started | Jul 20 06:14:28 PM PDT 24 |
Finished | Jul 20 06:14:40 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-d21b2dee-9b4d-4160-b1b3-ec0273b79421 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979991702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.979991702 |
Directory | /workspace/29.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all.294790950 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 46562366899 ps |
CPU time | 2687.06 seconds |
Started | Jul 20 06:14:37 PM PDT 24 |
Finished | Jul 20 06:59:25 PM PDT 24 |
Peak memory | 381876 kb |
Host | smart-7b6d7af4-230b-4278-bb61-acd0b72dc326 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294790950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 29.sram_ctrl_stress_all.294790950 |
Directory | /workspace/29.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.610821046 |
Short name | T731 |
Test name | |
Test status | |
Simulation time | 914874224 ps |
CPU time | 21.06 seconds |
Started | Jul 20 06:14:37 PM PDT 24 |
Finished | Jul 20 06:14:58 PM PDT 24 |
Peak memory | 211168 kb |
Host | smart-5625ae1b-7e11-49b2-9e3a-0bd9c914ed8c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=610821046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_stress_all_with_rand_reset.610821046 |
Directory | /workspace/29.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_stress_pipeline.2740955159 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 4697600887 ps |
CPU time | 334.53 seconds |
Started | Jul 20 06:14:36 PM PDT 24 |
Finished | Jul 20 06:20:11 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-d1e04d93-19f6-4508-9d54-c31f1b027682 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740955159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 9.sram_ctrl_stress_pipeline.2740955159 |
Directory | /workspace/29.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2133031447 |
Short name | T639 |
Test name | |
Test status | |
Simulation time | 1600543675 ps |
CPU time | 54.85 seconds |
Started | Jul 20 06:14:37 PM PDT 24 |
Finished | Jul 20 06:15:33 PM PDT 24 |
Peak memory | 323476 kb |
Host | smart-d26d066f-506a-4fbc-a82e-1ef39fa4cb69 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133031447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.2133031447 |
Directory | /workspace/29.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_access_during_key_req.3708169318 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 228576285901 ps |
CPU time | 985.12 seconds |
Started | Jul 20 06:12:32 PM PDT 24 |
Finished | Jul 20 06:28:59 PM PDT 24 |
Peak memory | 377684 kb |
Host | smart-facde4cc-d842-4361-a0cf-0c32c6bd9f8f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708169318 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.sram_ctrl_access_during_key_req.3708169318 |
Directory | /workspace/3.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_alert_test.479649603 |
Short name | T607 |
Test name | |
Test status | |
Simulation time | 27780747 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:12:39 PM PDT 24 |
Peak memory | 202456 kb |
Host | smart-fe40e45a-4b09-4b1e-a902-2de21db197b7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479649603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_alert_test.479649603 |
Directory | /workspace/3.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_bijection.1323314428 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 32837810497 ps |
CPU time | 2246.56 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:50:05 PM PDT 24 |
Peak memory | 203024 kb |
Host | smart-22175ae2-8ad5-4cba-9d30-09ec8486aec4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323314428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection. 1323314428 |
Directory | /workspace/3.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_executable.1598070776 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 87056580885 ps |
CPU time | 979.55 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:28:58 PM PDT 24 |
Peak memory | 379036 kb |
Host | smart-2edf748d-5e5b-4e06-80ae-92705bd244f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598070776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl e.1598070776 |
Directory | /workspace/3.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_lc_escalation.1620987185 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 49163300381 ps |
CPU time | 51.72 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:13:30 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-a76a3c49-5f76-4f98-b314-c43768225b31 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620987185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esc alation.1620987185 |
Directory | /workspace/3.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_max_throughput.1627598050 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 2834037469 ps |
CPU time | 147.93 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:15:06 PM PDT 24 |
Peak memory | 371864 kb |
Host | smart-eb5a407d-7a96-49ed-8810-6434a9db6d78 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627598050 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_max_throughput.1627598050 |
Directory | /workspace/3.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_partial_access.74456726 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 6323478687 ps |
CPU time | 129.31 seconds |
Started | Jul 20 06:12:35 PM PDT 24 |
Finished | Jul 20 06:14:46 PM PDT 24 |
Peak memory | 219172 kb |
Host | smart-633dda65-aacf-42d8-9360-93f44817f63e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74456726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.s ram_ctrl_mem_partial_access.74456726 |
Directory | /workspace/3.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_mem_walk.3846049948 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 5256371181 ps |
CPU time | 304.33 seconds |
Started | Jul 20 06:12:37 PM PDT 24 |
Finished | Jul 20 06:17:43 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-3e89b8d2-9a65-4406-a973-66340591686e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846049948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl _mem_walk.3846049948 |
Directory | /workspace/3.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_multiple_keys.630497876 |
Short name | T728 |
Test name | |
Test status | |
Simulation time | 112601280263 ps |
CPU time | 1937.36 seconds |
Started | Jul 20 06:12:32 PM PDT 24 |
Finished | Jul 20 06:44:51 PM PDT 24 |
Peak memory | 380336 kb |
Host | smart-e38ed8c5-eebf-47e8-818b-2f4e86dcd751 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630497876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multipl e_keys.630497876 |
Directory | /workspace/3.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access.157357379 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 4131767809 ps |
CPU time | 12.79 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:12:51 PM PDT 24 |
Peak memory | 230508 kb |
Host | smart-427b5414-a7f1-4bb8-a400-5b15639f76a4 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157357379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sr am_ctrl_partial_access.157357379 |
Directory | /workspace/3.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.111066338 |
Short name | T749 |
Test name | |
Test status | |
Simulation time | 17255345025 ps |
CPU time | 451.42 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:20:07 PM PDT 24 |
Peak memory | 202816 kb |
Host | smart-5bea3e27-4d67-4f58-8c3e-5f75866d59da |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111066338 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 3.sram_ctrl_partial_access_b2b.111066338 |
Directory | /workspace/3.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_ram_cfg.2505496840 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 363105655 ps |
CPU time | 3.11 seconds |
Started | Jul 20 06:12:33 PM PDT 24 |
Finished | Jul 20 06:12:37 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-330b2eac-c5b6-422a-a6b9-4ba7374c6f0a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505496840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2505496840 |
Directory | /workspace/3.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_regwen.1090461611 |
Short name | T592 |
Test name | |
Test status | |
Simulation time | 4360572821 ps |
CPU time | 93.51 seconds |
Started | Jul 20 06:12:30 PM PDT 24 |
Finished | Jul 20 06:14:05 PM PDT 24 |
Peak memory | 313180 kb |
Host | smart-a0231550-96f6-4d71-817c-86ffeff26a81 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090461611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1090461611 |
Directory | /workspace/3.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_sec_cm.1453397717 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 280725585 ps |
CPU time | 3.23 seconds |
Started | Jul 20 06:12:35 PM PDT 24 |
Finished | Jul 20 06:12:41 PM PDT 24 |
Peak memory | 222116 kb |
Host | smart-22538de9-40a8-4c1e-b03e-6bb4ec3818e1 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453397717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_sec_cm.1453397717 |
Directory | /workspace/3.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_smoke.1848790867 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 1880924451 ps |
CPU time | 152.14 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:15:08 PM PDT 24 |
Peak memory | 369512 kb |
Host | smart-e29228cb-69f7-49ac-870f-4872969d2b95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848790867 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.1848790867 |
Directory | /workspace/3.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all.708394628 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 523913783193 ps |
CPU time | 5183.17 seconds |
Started | Jul 20 06:12:30 PM PDT 24 |
Finished | Jul 20 07:38:55 PM PDT 24 |
Peak memory | 378864 kb |
Host | smart-d10c9b24-8f49-474b-8e2a-591bda5a1c68 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708394628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.sram_ctrl_stress_all.708394628 |
Directory | /workspace/3.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.2197746552 |
Short name | T579 |
Test name | |
Test status | |
Simulation time | 1855927393 ps |
CPU time | 74.75 seconds |
Started | Jul 20 06:12:37 PM PDT 24 |
Finished | Jul 20 06:13:53 PM PDT 24 |
Peak memory | 213592 kb |
Host | smart-d1a6aead-e119-4357-bc56-cf56f30b1cc8 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2197746552 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_stress_all_with_rand_reset.2197746552 |
Directory | /workspace/3.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_stress_pipeline.218868033 |
Short name | T705 |
Test name | |
Test status | |
Simulation time | 11838393228 ps |
CPU time | 286.33 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:17:22 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-212620e0-9035-4674-9e54-2554a9abe81b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218868033 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3. sram_ctrl_stress_pipeline.218868033 |
Directory | /workspace/3.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.596345791 |
Short name | T697 |
Test name | |
Test status | |
Simulation time | 744131812 ps |
CPU time | 56.09 seconds |
Started | Jul 20 06:12:33 PM PDT 24 |
Finished | Jul 20 06:13:31 PM PDT 24 |
Peak memory | 302024 kb |
Host | smart-d46cd427-8a23-4081-ab6f-645586d2a87c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596345791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.sram_ctrl_throughput_w_partial_write.596345791 |
Directory | /workspace/3.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_access_during_key_req.2644128560 |
Short name | T681 |
Test name | |
Test status | |
Simulation time | 62623990372 ps |
CPU time | 957.39 seconds |
Started | Jul 20 06:14:41 PM PDT 24 |
Finished | Jul 20 06:30:40 PM PDT 24 |
Peak memory | 376732 kb |
Host | smart-07b40211-9052-4096-9e0b-dd77b671eeb3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644128560 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 30.sram_ctrl_access_during_key_req.2644128560 |
Directory | /workspace/30.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_alert_test.1476728403 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 32485632 ps |
CPU time | 0.65 seconds |
Started | Jul 20 06:14:41 PM PDT 24 |
Finished | Jul 20 06:14:42 PM PDT 24 |
Peak memory | 202492 kb |
Host | smart-fe21b5c0-4416-48bf-bb50-f2154428b12e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476728403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_alert_test.1476728403 |
Directory | /workspace/30.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_bijection.1246430283 |
Short name | T740 |
Test name | |
Test status | |
Simulation time | 64303165810 ps |
CPU time | 1186.81 seconds |
Started | Jul 20 06:14:34 PM PDT 24 |
Finished | Jul 20 06:34:21 PM PDT 24 |
Peak memory | 203452 kb |
Host | smart-c486bb32-ac59-402d-b71c-572647a765cb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246430283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection .1246430283 |
Directory | /workspace/30.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_executable.998064794 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 20666851297 ps |
CPU time | 1110.59 seconds |
Started | Jul 20 06:14:43 PM PDT 24 |
Finished | Jul 20 06:33:15 PM PDT 24 |
Peak memory | 374840 kb |
Host | smart-f926d1a6-40f6-4987-ac64-7a96fa83162b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998064794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executabl e.998064794 |
Directory | /workspace/30.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_lc_escalation.2378849169 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 9036527149 ps |
CPU time | 49.43 seconds |
Started | Jul 20 06:14:45 PM PDT 24 |
Finished | Jul 20 06:15:35 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-2e73ce54-2a86-45bb-9f5e-7b8178926ee8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378849169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_es calation.2378849169 |
Directory | /workspace/30.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_max_throughput.906103869 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 3601135915 ps |
CPU time | 28.88 seconds |
Started | Jul 20 06:14:43 PM PDT 24 |
Finished | Jul 20 06:15:13 PM PDT 24 |
Peak memory | 284656 kb |
Host | smart-928fd8b3-4181-470c-bfdc-bb083c975712 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906103869 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 30.sram_ctrl_max_throughput.906103869 |
Directory | /workspace/30.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2554810341 |
Short name | T623 |
Test name | |
Test status | |
Simulation time | 3467328570 ps |
CPU time | 73.79 seconds |
Started | Jul 20 06:14:45 PM PDT 24 |
Finished | Jul 20 06:15:59 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-9cad4651-eeef-4738-884d-8ea774c84065 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554810341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_mem_partial_access.2554810341 |
Directory | /workspace/30.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_mem_walk.1198294178 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 27629817800 ps |
CPU time | 309.85 seconds |
Started | Jul 20 06:14:43 PM PDT 24 |
Finished | Jul 20 06:19:54 PM PDT 24 |
Peak memory | 211068 kb |
Host | smart-48bd72a3-00e0-4cc2-b511-3e6021b04095 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198294178 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr l_mem_walk.1198294178 |
Directory | /workspace/30.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_multiple_keys.1411501568 |
Short name | T760 |
Test name | |
Test status | |
Simulation time | 20520238580 ps |
CPU time | 1355.89 seconds |
Started | Jul 20 06:14:36 PM PDT 24 |
Finished | Jul 20 06:37:13 PM PDT 24 |
Peak memory | 378792 kb |
Host | smart-f3ddc89f-bc7a-449f-aa8d-509f0252eb64 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411501568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi ple_keys.1411501568 |
Directory | /workspace/30.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access.3638148385 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 2923078218 ps |
CPU time | 23.44 seconds |
Started | Jul 20 06:14:40 PM PDT 24 |
Finished | Jul 20 06:15:04 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-fb3953ca-a1c2-48c0-acef-b3f80ff8382c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638148385 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30. sram_ctrl_partial_access.3638148385 |
Directory | /workspace/30.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.420380949 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 48967951296 ps |
CPU time | 549.71 seconds |
Started | Jul 20 06:14:44 PM PDT 24 |
Finished | Jul 20 06:23:54 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-9e83565e-98fd-4942-b726-6d10243e8c5b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420380949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 30.sram_ctrl_partial_access_b2b.420380949 |
Directory | /workspace/30.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_ram_cfg.593504116 |
Short name | T686 |
Test name | |
Test status | |
Simulation time | 346757993 ps |
CPU time | 3.2 seconds |
Started | Jul 20 06:14:44 PM PDT 24 |
Finished | Jul 20 06:14:48 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-e1b4ef67-a247-4be0-aec8-403228b56b83 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593504116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.593504116 |
Directory | /workspace/30.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_regwen.643160308 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 54735435236 ps |
CPU time | 1066.41 seconds |
Started | Jul 20 06:14:43 PM PDT 24 |
Finished | Jul 20 06:32:31 PM PDT 24 |
Peak memory | 380648 kb |
Host | smart-9e9e83b1-8f49-4b37-a574-11b4bb83c18c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643160308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.643160308 |
Directory | /workspace/30.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_smoke.59911253 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 2710512649 ps |
CPU time | 7.14 seconds |
Started | Jul 20 06:14:34 PM PDT 24 |
Finished | Jul 20 06:14:41 PM PDT 24 |
Peak memory | 202828 kb |
Host | smart-f1f0dbd7-ff69-4aac-8249-cf30a875b727 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59911253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.59911253 |
Directory | /workspace/30.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all.869166980 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 239029626445 ps |
CPU time | 1702.59 seconds |
Started | Jul 20 06:14:43 PM PDT 24 |
Finished | Jul 20 06:43:07 PM PDT 24 |
Peak memory | 379780 kb |
Host | smart-023c8132-d096-434d-833f-92d3112a3b63 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869166980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 30.sram_ctrl_stress_all.869166980 |
Directory | /workspace/30.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3651901305 |
Short name | T643 |
Test name | |
Test status | |
Simulation time | 2381670571 ps |
CPU time | 35.2 seconds |
Started | Jul 20 06:14:43 PM PDT 24 |
Finished | Jul 20 06:15:18 PM PDT 24 |
Peak memory | 211220 kb |
Host | smart-ecbcb809-6a8c-496d-8af0-2b59c4ab6fac |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3651901305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_stress_all_with_rand_reset.3651901305 |
Directory | /workspace/30.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_stress_pipeline.1375645195 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 22484308970 ps |
CPU time | 304.23 seconds |
Started | Jul 20 06:14:43 PM PDT 24 |
Finished | Jul 20 06:19:48 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-a37ccc04-151f-40cb-8a33-950e684db25b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375645195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 0.sram_ctrl_stress_pipeline.1375645195 |
Directory | /workspace/30.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.801172628 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 1106581455 ps |
CPU time | 18.07 seconds |
Started | Jul 20 06:14:44 PM PDT 24 |
Finished | Jul 20 06:15:03 PM PDT 24 |
Peak memory | 252968 kb |
Host | smart-088b6d1d-ca79-4433-868d-dd8ccb4dec75 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801172628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 30.sram_ctrl_throughput_w_partial_write.801172628 |
Directory | /workspace/30.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_access_during_key_req.1418153320 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 3909355600 ps |
CPU time | 301.85 seconds |
Started | Jul 20 06:14:52 PM PDT 24 |
Finished | Jul 20 06:19:55 PM PDT 24 |
Peak memory | 369352 kb |
Host | smart-c838cd51-0c3b-4d37-a0a3-b4e12eb87e79 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418153320 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 31.sram_ctrl_access_during_key_req.1418153320 |
Directory | /workspace/31.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_alert_test.2052303272 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 152961877 ps |
CPU time | 0.64 seconds |
Started | Jul 20 06:14:51 PM PDT 24 |
Finished | Jul 20 06:14:52 PM PDT 24 |
Peak memory | 202624 kb |
Host | smart-ffc22517-6762-49c6-831e-0d91cff55242 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052303272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_alert_test.2052303272 |
Directory | /workspace/31.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_bijection.2196371004 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 29474504213 ps |
CPU time | 2124.03 seconds |
Started | Jul 20 06:14:45 PM PDT 24 |
Finished | Jul 20 06:50:10 PM PDT 24 |
Peak memory | 203692 kb |
Host | smart-cf643b00-e9ab-4842-9dbe-1f504b4a31d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196371004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection .2196371004 |
Directory | /workspace/31.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_executable.2717531264 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 9626783979 ps |
CPU time | 398.85 seconds |
Started | Jul 20 06:14:52 PM PDT 24 |
Finished | Jul 20 06:21:32 PM PDT 24 |
Peak memory | 344168 kb |
Host | smart-05737fd8-fe2c-42c4-859d-099158b10e9f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717531264 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab le.2717531264 |
Directory | /workspace/31.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_lc_escalation.493098614 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 15076391007 ps |
CPU time | 93.44 seconds |
Started | Jul 20 06:14:54 PM PDT 24 |
Finished | Jul 20 06:16:27 PM PDT 24 |
Peak memory | 214872 kb |
Host | smart-0d1c66b6-41b6-4701-8773-117f767caeb7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493098614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_esc alation.493098614 |
Directory | /workspace/31.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_max_throughput.3785222147 |
Short name | T752 |
Test name | |
Test status | |
Simulation time | 1433100303 ps |
CPU time | 6.52 seconds |
Started | Jul 20 06:14:52 PM PDT 24 |
Finished | Jul 20 06:14:59 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-84707721-a55e-4cbc-9867-1adc78c0d31e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785222147 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 31.sram_ctrl_max_throughput.3785222147 |
Directory | /workspace/31.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_partial_access.4276992159 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 5484870382 ps |
CPU time | 78.63 seconds |
Started | Jul 20 06:14:49 PM PDT 24 |
Finished | Jul 20 06:16:08 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-2e205a7f-faa4-4373-9660-12a0ab759482 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276992159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_mem_partial_access.4276992159 |
Directory | /workspace/31.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_mem_walk.1679229593 |
Short name | T700 |
Test name | |
Test status | |
Simulation time | 18717077980 ps |
CPU time | 175.83 seconds |
Started | Jul 20 06:14:52 PM PDT 24 |
Finished | Jul 20 06:17:48 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-a3d6cda4-7dc0-4c0a-bc70-076c70a4908f |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679229593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr l_mem_walk.1679229593 |
Directory | /workspace/31.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_multiple_keys.1255478484 |
Short name | T850 |
Test name | |
Test status | |
Simulation time | 22527573190 ps |
CPU time | 448.31 seconds |
Started | Jul 20 06:14:42 PM PDT 24 |
Finished | Jul 20 06:22:11 PM PDT 24 |
Peak memory | 353232 kb |
Host | smart-29faf419-9688-402e-ac20-3cc8e0349e1d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255478484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi ple_keys.1255478484 |
Directory | /workspace/31.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access.2125156930 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 2590567177 ps |
CPU time | 150.09 seconds |
Started | Jul 20 06:14:46 PM PDT 24 |
Finished | Jul 20 06:17:17 PM PDT 24 |
Peak memory | 360308 kb |
Host | smart-52c14864-08be-484f-bda4-5559e8a3abfc |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125156930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31. sram_ctrl_partial_access.2125156930 |
Directory | /workspace/31.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.1148841563 |
Short name | T906 |
Test name | |
Test status | |
Simulation time | 7426296182 ps |
CPU time | 379.46 seconds |
Started | Jul 20 06:14:54 PM PDT 24 |
Finished | Jul 20 06:21:14 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-aba594a9-008e-4443-9ea0-c5edca4378e9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148841563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 31.sram_ctrl_partial_access_b2b.1148841563 |
Directory | /workspace/31.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_ram_cfg.2728570207 |
Short name | T690 |
Test name | |
Test status | |
Simulation time | 910077045 ps |
CPU time | 3.4 seconds |
Started | Jul 20 06:14:51 PM PDT 24 |
Finished | Jul 20 06:14:55 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-2f245d85-0781-4ebb-95c2-b24a3031fff4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728570207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.2728570207 |
Directory | /workspace/31.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_regwen.3469705412 |
Short name | T736 |
Test name | |
Test status | |
Simulation time | 2230134410 ps |
CPU time | 851.81 seconds |
Started | Jul 20 06:14:49 PM PDT 24 |
Finished | Jul 20 06:29:01 PM PDT 24 |
Peak memory | 379816 kb |
Host | smart-fe4005ad-2960-4f37-bc17-6c8a51386a56 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469705412 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.3469705412 |
Directory | /workspace/31.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_smoke.1331704142 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 502950102 ps |
CPU time | 12.7 seconds |
Started | Jul 20 06:14:44 PM PDT 24 |
Finished | Jul 20 06:14:57 PM PDT 24 |
Peak memory | 202804 kb |
Host | smart-b3441aeb-579c-40c0-9ca2-28570f262540 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331704142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.1331704142 |
Directory | /workspace/31.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all.2212556157 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 1113626193497 ps |
CPU time | 8136.66 seconds |
Started | Jul 20 06:14:51 PM PDT 24 |
Finished | Jul 20 08:30:30 PM PDT 24 |
Peak memory | 381872 kb |
Host | smart-3b3ca945-9e2b-4df5-980c-5dba26ad47eb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212556157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 31.sram_ctrl_stress_all.2212556157 |
Directory | /workspace/31.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.122600409 |
Short name | T718 |
Test name | |
Test status | |
Simulation time | 787750756 ps |
CPU time | 22.34 seconds |
Started | Jul 20 06:14:51 PM PDT 24 |
Finished | Jul 20 06:15:13 PM PDT 24 |
Peak memory | 211508 kb |
Host | smart-a00dc080-c368-4942-9e41-3decd8f4c5d3 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=122600409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_stress_all_with_rand_reset.122600409 |
Directory | /workspace/31.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_stress_pipeline.1852323981 |
Short name | T599 |
Test name | |
Test status | |
Simulation time | 6035411397 ps |
CPU time | 193.76 seconds |
Started | Jul 20 06:14:43 PM PDT 24 |
Finished | Jul 20 06:17:57 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-12378dc2-62a2-4d49-834c-cedaea689182 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852323981 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 1.sram_ctrl_stress_pipeline.1852323981 |
Directory | /workspace/31.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.3988562791 |
Short name | T759 |
Test name | |
Test status | |
Simulation time | 2948496401 ps |
CPU time | 19.84 seconds |
Started | Jul 20 06:14:50 PM PDT 24 |
Finished | Jul 20 06:15:10 PM PDT 24 |
Peak memory | 258224 kb |
Host | smart-7985878d-b6d6-4a3f-8b63-49fd9e85fe4a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988562791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.3988562791 |
Directory | /workspace/31.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_access_during_key_req.385472740 |
Short name | T869 |
Test name | |
Test status | |
Simulation time | 10923945337 ps |
CPU time | 214.85 seconds |
Started | Jul 20 06:14:59 PM PDT 24 |
Finished | Jul 20 06:18:35 PM PDT 24 |
Peak memory | 360456 kb |
Host | smart-b92c1f7f-51b4-4ffb-9689-e2f167f12653 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385472740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 32.sram_ctrl_access_during_key_req.385472740 |
Directory | /workspace/32.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_alert_test.92626465 |
Short name | T929 |
Test name | |
Test status | |
Simulation time | 80508660 ps |
CPU time | 0.65 seconds |
Started | Jul 20 06:14:59 PM PDT 24 |
Finished | Jul 20 06:15:00 PM PDT 24 |
Peak memory | 202276 kb |
Host | smart-b9c38b14-1cc4-47f0-b016-3990db7177e7 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92626465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_alert_test.92626465 |
Directory | /workspace/32.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_bijection.2264262625 |
Short name | T744 |
Test name | |
Test status | |
Simulation time | 148051590536 ps |
CPU time | 901.91 seconds |
Started | Jul 20 06:14:49 PM PDT 24 |
Finished | Jul 20 06:29:52 PM PDT 24 |
Peak memory | 203624 kb |
Host | smart-71a64806-ca16-4ecd-ab5e-927a0f86eca5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264262625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection .2264262625 |
Directory | /workspace/32.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_executable.2375851841 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 25573493779 ps |
CPU time | 529.77 seconds |
Started | Jul 20 06:14:59 PM PDT 24 |
Finished | Jul 20 06:23:49 PM PDT 24 |
Peak memory | 362104 kb |
Host | smart-17f0d0f2-30ac-4dba-98c4-7faeaca2924f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375851841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab le.2375851841 |
Directory | /workspace/32.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_lc_escalation.1886373785 |
Short name | T767 |
Test name | |
Test status | |
Simulation time | 8333248955 ps |
CPU time | 43.15 seconds |
Started | Jul 20 06:15:00 PM PDT 24 |
Finished | Jul 20 06:15:44 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-366248aa-cb2e-4f47-a03a-95947e7f9f8f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886373785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es calation.1886373785 |
Directory | /workspace/32.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_max_throughput.394359408 |
Short name | T743 |
Test name | |
Test status | |
Simulation time | 2733374138 ps |
CPU time | 11.12 seconds |
Started | Jul 20 06:14:58 PM PDT 24 |
Finished | Jul 20 06:15:10 PM PDT 24 |
Peak memory | 235692 kb |
Host | smart-57dceb0a-d181-46f3-a652-9172aae314d5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394359408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 32.sram_ctrl_max_throughput.394359408 |
Directory | /workspace/32.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_partial_access.1165735417 |
Short name | T825 |
Test name | |
Test status | |
Simulation time | 5366163922 ps |
CPU time | 85.81 seconds |
Started | Jul 20 06:15:01 PM PDT 24 |
Finished | Jul 20 06:16:28 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-a67d0ad5-a389-4986-885b-bec3be9f2fa9 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165735417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_mem_partial_access.1165735417 |
Directory | /workspace/32.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_mem_walk.2254285431 |
Short name | T663 |
Test name | |
Test status | |
Simulation time | 6989755371 ps |
CPU time | 174.73 seconds |
Started | Jul 20 06:14:58 PM PDT 24 |
Finished | Jul 20 06:17:53 PM PDT 24 |
Peak memory | 211016 kb |
Host | smart-6a9ecece-da29-4f3f-a2f8-296809efac06 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254285431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctr l_mem_walk.2254285431 |
Directory | /workspace/32.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_multiple_keys.1461745866 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 3375723094 ps |
CPU time | 198.71 seconds |
Started | Jul 20 06:14:53 PM PDT 24 |
Finished | Jul 20 06:18:12 PM PDT 24 |
Peak memory | 369372 kb |
Host | smart-cf5fdd74-ec8d-4c94-b8ca-556728e3ebe0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461745866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi ple_keys.1461745866 |
Directory | /workspace/32.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access.1450400182 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 1665016308 ps |
CPU time | 8.41 seconds |
Started | Jul 20 06:14:49 PM PDT 24 |
Finished | Jul 20 06:14:58 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-f0099160-641d-4e11-b2c9-928f977c11be |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450400182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32. sram_ctrl_partial_access.1450400182 |
Directory | /workspace/32.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3812362515 |
Short name | T930 |
Test name | |
Test status | |
Simulation time | 63742411980 ps |
CPU time | 394.54 seconds |
Started | Jul 20 06:14:52 PM PDT 24 |
Finished | Jul 20 06:21:27 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-feec36d6-00ac-46e8-b82c-8404b74b083b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812362515 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_partial_access_b2b.3812362515 |
Directory | /workspace/32.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_ram_cfg.4175304305 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 366264435 ps |
CPU time | 3.17 seconds |
Started | Jul 20 06:14:57 PM PDT 24 |
Finished | Jul 20 06:15:01 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-65475b21-02fc-4964-afc5-89699545f526 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175304305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.4175304305 |
Directory | /workspace/32.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_regwen.2740858117 |
Short name | T764 |
Test name | |
Test status | |
Simulation time | 14020019266 ps |
CPU time | 911.15 seconds |
Started | Jul 20 06:14:57 PM PDT 24 |
Finished | Jul 20 06:30:09 PM PDT 24 |
Peak memory | 378836 kb |
Host | smart-ced27b54-6f95-4b0a-9f97-28fab6dded30 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740858117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.2740858117 |
Directory | /workspace/32.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_smoke.2954847680 |
Short name | T659 |
Test name | |
Test status | |
Simulation time | 998899477 ps |
CPU time | 37.21 seconds |
Started | Jul 20 06:14:54 PM PDT 24 |
Finished | Jul 20 06:15:31 PM PDT 24 |
Peak memory | 280508 kb |
Host | smart-2e1372bb-7ff4-4a74-93d9-cb8b9f9b8892 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954847680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.2954847680 |
Directory | /workspace/32.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all.278957702 |
Short name | T655 |
Test name | |
Test status | |
Simulation time | 229659805229 ps |
CPU time | 7386.29 seconds |
Started | Jul 20 06:15:00 PM PDT 24 |
Finished | Jul 20 08:18:07 PM PDT 24 |
Peak memory | 382884 kb |
Host | smart-80d0a6d7-c874-454d-aaa6-45f5a649b8d2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278957702 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 32.sram_ctrl_stress_all.278957702 |
Directory | /workspace/32.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.3834055903 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 589615113 ps |
CPU time | 16.87 seconds |
Started | Jul 20 06:15:01 PM PDT 24 |
Finished | Jul 20 06:15:18 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-3284c88e-d0bc-4b8b-85a0-a5a7212ad887 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3834055903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_stress_all_with_rand_reset.3834055903 |
Directory | /workspace/32.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_stress_pipeline.3582759073 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 6411419367 ps |
CPU time | 147.79 seconds |
Started | Jul 20 06:14:54 PM PDT 24 |
Finished | Jul 20 06:17:22 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-3eb968e3-a0a6-4358-ab3d-52101c33817f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582759073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 2.sram_ctrl_stress_pipeline.3582759073 |
Directory | /workspace/32.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3878100629 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 696844681 ps |
CPU time | 6.39 seconds |
Started | Jul 20 06:15:00 PM PDT 24 |
Finished | Jul 20 06:15:07 PM PDT 24 |
Peak memory | 211020 kb |
Host | smart-be265a66-17db-465a-ac23-85766ddf09b0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878100629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.3878100629 |
Directory | /workspace/32.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_access_during_key_req.581985122 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 7014094993 ps |
CPU time | 568.14 seconds |
Started | Jul 20 06:15:12 PM PDT 24 |
Finished | Jul 20 06:24:40 PM PDT 24 |
Peak memory | 373612 kb |
Host | smart-f92ea7b4-dc97-4894-a509-48017aa2c859 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581985122 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 33.sram_ctrl_access_during_key_req.581985122 |
Directory | /workspace/33.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_alert_test.725618066 |
Short name | T925 |
Test name | |
Test status | |
Simulation time | 19860699 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:15:11 PM PDT 24 |
Finished | Jul 20 06:15:12 PM PDT 24 |
Peak memory | 202484 kb |
Host | smart-d528cbd9-e0b5-4b8b-98a0-79101250cf38 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725618066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_alert_test.725618066 |
Directory | /workspace/33.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_bijection.39817857 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 85034534410 ps |
CPU time | 961.81 seconds |
Started | Jul 20 06:15:01 PM PDT 24 |
Finished | Jul 20 06:31:03 PM PDT 24 |
Peak memory | 203416 kb |
Host | smart-3445d650-adf4-4f35-a986-6542372246fe |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39817857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection.39817857 |
Directory | /workspace/33.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_executable.1076384629 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 35710118863 ps |
CPU time | 584.83 seconds |
Started | Jul 20 06:15:09 PM PDT 24 |
Finished | Jul 20 06:24:55 PM PDT 24 |
Peak memory | 336928 kb |
Host | smart-4d29e7ad-dc76-4099-b902-9c17b724b78a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076384629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executab le.1076384629 |
Directory | /workspace/33.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_lc_escalation.4057238871 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 49882422892 ps |
CPU time | 90.02 seconds |
Started | Jul 20 06:15:09 PM PDT 24 |
Finished | Jul 20 06:16:40 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-823ae460-2e69-4baf-a07d-5c29107729b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057238871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_es calation.4057238871 |
Directory | /workspace/33.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_max_throughput.4050653474 |
Short name | T907 |
Test name | |
Test status | |
Simulation time | 786621954 ps |
CPU time | 16.14 seconds |
Started | Jul 20 06:15:08 PM PDT 24 |
Finished | Jul 20 06:15:25 PM PDT 24 |
Peak memory | 244680 kb |
Host | smart-7e3233b7-c72d-405e-b048-cc2ea6d9d50b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050653474 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_max_throughput.4050653474 |
Directory | /workspace/33.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2378970036 |
Short name | T692 |
Test name | |
Test status | |
Simulation time | 9987385001 ps |
CPU time | 162.47 seconds |
Started | Jul 20 06:15:10 PM PDT 24 |
Finished | Jul 20 06:17:53 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-a1f33b33-47cc-4cf0-8b25-15f3018f71b4 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378970036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_mem_partial_access.2378970036 |
Directory | /workspace/33.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_mem_walk.1658074075 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 13872536400 ps |
CPU time | 311.87 seconds |
Started | Jul 20 06:15:09 PM PDT 24 |
Finished | Jul 20 06:20:21 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-85919b17-ce7f-4ebd-851d-f36efaa8fb9c |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658074075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctr l_mem_walk.1658074075 |
Directory | /workspace/33.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_multiple_keys.2179122096 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 80090168422 ps |
CPU time | 893.91 seconds |
Started | Jul 20 06:15:00 PM PDT 24 |
Finished | Jul 20 06:29:55 PM PDT 24 |
Peak memory | 379952 kb |
Host | smart-b56bf734-fc9c-4bb1-b551-92f65588e0a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179122096 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multi ple_keys.2179122096 |
Directory | /workspace/33.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access.3692517962 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 795928550 ps |
CPU time | 12.02 seconds |
Started | Jul 20 06:15:14 PM PDT 24 |
Finished | Jul 20 06:15:26 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-635f6627-b106-41fb-a3a2-87a3b4991126 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692517962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33. sram_ctrl_partial_access.3692517962 |
Directory | /workspace/33.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.341166238 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 28335657678 ps |
CPU time | 450.79 seconds |
Started | Jul 20 06:15:10 PM PDT 24 |
Finished | Jul 20 06:22:41 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-1c4ffcb7-a9d2-4266-90b3-ffe49f6d5c02 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341166238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 33.sram_ctrl_partial_access_b2b.341166238 |
Directory | /workspace/33.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_ram_cfg.1680366179 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 2793732648 ps |
CPU time | 3.68 seconds |
Started | Jul 20 06:15:09 PM PDT 24 |
Finished | Jul 20 06:15:14 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-13e029b6-dac0-42be-9b26-a046d1fe7483 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680366179 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.1680366179 |
Directory | /workspace/33.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_regwen.3635924203 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 2895583096 ps |
CPU time | 140.95 seconds |
Started | Jul 20 06:15:11 PM PDT 24 |
Finished | Jul 20 06:17:32 PM PDT 24 |
Peak memory | 362928 kb |
Host | smart-68713314-0bdc-4c3f-a3f1-de5f3a6f9486 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635924203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.3635924203 |
Directory | /workspace/33.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_smoke.2074887234 |
Short name | T665 |
Test name | |
Test status | |
Simulation time | 704763338 ps |
CPU time | 6.25 seconds |
Started | Jul 20 06:15:00 PM PDT 24 |
Finished | Jul 20 06:15:07 PM PDT 24 |
Peak memory | 203012 kb |
Host | smart-edf8c256-3ff8-43b3-a5ab-01a8349ebff9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074887234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.2074887234 |
Directory | /workspace/33.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all.3418537288 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 73836097548 ps |
CPU time | 1671.02 seconds |
Started | Jul 20 06:15:09 PM PDT 24 |
Finished | Jul 20 06:43:01 PM PDT 24 |
Peak memory | 388020 kb |
Host | smart-752e9f16-fc28-4545-89bf-9aa68deb4537 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418537288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 33.sram_ctrl_stress_all.3418537288 |
Directory | /workspace/33.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.3791464227 |
Short name | T884 |
Test name | |
Test status | |
Simulation time | 1511870665 ps |
CPU time | 138.99 seconds |
Started | Jul 20 06:15:08 PM PDT 24 |
Finished | Jul 20 06:17:27 PM PDT 24 |
Peak memory | 348056 kb |
Host | smart-ad201bf0-b1f6-43ff-949c-4fe125fdafdd |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3791464227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_stress_all_with_rand_reset.3791464227 |
Directory | /workspace/33.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_stress_pipeline.2897816048 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 4451987141 ps |
CPU time | 259.8 seconds |
Started | Jul 20 06:14:57 PM PDT 24 |
Finished | Jul 20 06:19:18 PM PDT 24 |
Peak memory | 202928 kb |
Host | smart-10d55a79-2af7-43ce-82db-eef3af8f9480 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897816048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 3.sram_ctrl_stress_pipeline.2897816048 |
Directory | /workspace/33.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.211199207 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 2719193930 ps |
CPU time | 8.42 seconds |
Started | Jul 20 06:15:11 PM PDT 24 |
Finished | Jul 20 06:15:21 PM PDT 24 |
Peak memory | 219240 kb |
Host | smart-534a777e-04ce-4ed8-836c-ab767d03c1a9 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211199207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 33.sram_ctrl_throughput_w_partial_write.211199207 |
Directory | /workspace/33.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_access_during_key_req.3218457227 |
Short name | T827 |
Test name | |
Test status | |
Simulation time | 58739766979 ps |
CPU time | 1217.2 seconds |
Started | Jul 20 06:15:18 PM PDT 24 |
Finished | Jul 20 06:35:35 PM PDT 24 |
Peak memory | 378756 kb |
Host | smart-df932a07-a28e-4258-a4bb-54c3cbd76b63 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218457227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 34.sram_ctrl_access_during_key_req.3218457227 |
Directory | /workspace/34.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_alert_test.1282137728 |
Short name | T734 |
Test name | |
Test status | |
Simulation time | 22784451 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:15:16 PM PDT 24 |
Finished | Jul 20 06:15:17 PM PDT 24 |
Peak memory | 202696 kb |
Host | smart-a912dc4d-3886-4d65-94c0-98d3350b4830 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282137728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_alert_test.1282137728 |
Directory | /workspace/34.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_bijection.1918954912 |
Short name | T720 |
Test name | |
Test status | |
Simulation time | 63594511104 ps |
CPU time | 2331.38 seconds |
Started | Jul 20 06:15:08 PM PDT 24 |
Finished | Jul 20 06:54:00 PM PDT 24 |
Peak memory | 203680 kb |
Host | smart-7d2c7358-214b-4c62-a9fb-3d7f77bc698b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918954912 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection .1918954912 |
Directory | /workspace/34.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_executable.133083014 |
Short name | T656 |
Test name | |
Test status | |
Simulation time | 21539459240 ps |
CPU time | 504.51 seconds |
Started | Jul 20 06:15:18 PM PDT 24 |
Finished | Jul 20 06:23:44 PM PDT 24 |
Peak memory | 375672 kb |
Host | smart-abf58978-3890-4639-a9de-838ff22ddb18 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133083014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executabl e.133083014 |
Directory | /workspace/34.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_lc_escalation.3114870819 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 14908577129 ps |
CPU time | 55.65 seconds |
Started | Jul 20 06:15:18 PM PDT 24 |
Finished | Jul 20 06:16:15 PM PDT 24 |
Peak memory | 211064 kb |
Host | smart-eb03d1d3-b9b8-4584-9140-1758254803fc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114870819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es calation.3114870819 |
Directory | /workspace/34.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_max_throughput.977247901 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 2900450219 ps |
CPU time | 39.89 seconds |
Started | Jul 20 06:15:08 PM PDT 24 |
Finished | Jul 20 06:15:49 PM PDT 24 |
Peak memory | 301004 kb |
Host | smart-8905b70e-d65d-4ec5-9ac2-507a9bc70178 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977247901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.sram_ctrl_max_throughput.977247901 |
Directory | /workspace/34.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_partial_access.637581965 |
Short name | T920 |
Test name | |
Test status | |
Simulation time | 8971996614 ps |
CPU time | 163.89 seconds |
Started | Jul 20 06:15:18 PM PDT 24 |
Finished | Jul 20 06:18:02 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-8fc80953-8ed4-420e-87f1-1d742aba88dc |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637581965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34 .sram_ctrl_mem_partial_access.637581965 |
Directory | /workspace/34.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_mem_walk.1253637332 |
Short name | T627 |
Test name | |
Test status | |
Simulation time | 4787162253 ps |
CPU time | 147.46 seconds |
Started | Jul 20 06:15:15 PM PDT 24 |
Finished | Jul 20 06:17:43 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-5ae7ffc1-d61d-404e-9c8e-7a2c2c9b20df |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253637332 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr l_mem_walk.1253637332 |
Directory | /workspace/34.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_multiple_keys.3789982477 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 41836463027 ps |
CPU time | 459.64 seconds |
Started | Jul 20 06:15:11 PM PDT 24 |
Finished | Jul 20 06:22:51 PM PDT 24 |
Peak memory | 378244 kb |
Host | smart-ccd2f24c-724b-4034-ab97-5bcad16ab47a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789982477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi ple_keys.3789982477 |
Directory | /workspace/34.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access.2307430077 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 895021689 ps |
CPU time | 20.56 seconds |
Started | Jul 20 06:15:12 PM PDT 24 |
Finished | Jul 20 06:15:34 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-8597b17a-d71e-4f41-85ab-1c107af9d68e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307430077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34. sram_ctrl_partial_access.2307430077 |
Directory | /workspace/34.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.685223767 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 34383375761 ps |
CPU time | 478.12 seconds |
Started | Jul 20 06:15:09 PM PDT 24 |
Finished | Jul 20 06:23:08 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-6f082420-2ce8-4553-a5b0-d1e54b2959b2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685223767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 34.sram_ctrl_partial_access_b2b.685223767 |
Directory | /workspace/34.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_ram_cfg.1673151591 |
Short name | T842 |
Test name | |
Test status | |
Simulation time | 352687438 ps |
CPU time | 3.31 seconds |
Started | Jul 20 06:15:16 PM PDT 24 |
Finished | Jul 20 06:15:20 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-0f0f4b76-3dc1-4359-8353-e8e28f5256f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673151591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.1673151591 |
Directory | /workspace/34.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_regwen.3778653980 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 2203232025 ps |
CPU time | 288.28 seconds |
Started | Jul 20 06:15:18 PM PDT 24 |
Finished | Jul 20 06:20:07 PM PDT 24 |
Peak memory | 367412 kb |
Host | smart-eab58bd5-63dc-48d7-8370-3ff6422d50ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778653980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.3778653980 |
Directory | /workspace/34.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_smoke.4278327807 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 425919579 ps |
CPU time | 6.37 seconds |
Started | Jul 20 06:15:13 PM PDT 24 |
Finished | Jul 20 06:15:20 PM PDT 24 |
Peak memory | 213536 kb |
Host | smart-c8306eff-8be3-4c16-92f3-40783694631e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278327807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.4278327807 |
Directory | /workspace/34.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2999649040 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 3975834930 ps |
CPU time | 10.98 seconds |
Started | Jul 20 06:15:19 PM PDT 24 |
Finished | Jul 20 06:15:30 PM PDT 24 |
Peak memory | 211624 kb |
Host | smart-b147332c-d597-4afe-8267-b5091e9ecbcb |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2999649040 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_stress_all_with_rand_reset.2999649040 |
Directory | /workspace/34.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_stress_pipeline.455676585 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 8359924375 ps |
CPU time | 319.21 seconds |
Started | Jul 20 06:15:12 PM PDT 24 |
Finished | Jul 20 06:20:32 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-c4d7d984-0512-4294-b298-f66e261593df |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455676585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34 .sram_ctrl_stress_pipeline.455676585 |
Directory | /workspace/34.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2400299250 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 1376406028 ps |
CPU time | 6.57 seconds |
Started | Jul 20 06:15:10 PM PDT 24 |
Finished | Jul 20 06:15:17 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-803e4fbd-6a65-4974-8914-22ff4ec6db47 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400299250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.2400299250 |
Directory | /workspace/34.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2342286464 |
Short name | T895 |
Test name | |
Test status | |
Simulation time | 11069775306 ps |
CPU time | 1217.97 seconds |
Started | Jul 20 06:15:26 PM PDT 24 |
Finished | Jul 20 06:35:44 PM PDT 24 |
Peak memory | 379128 kb |
Host | smart-dea295ab-01d8-409f-9efe-bd4027b360bd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342286464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 35.sram_ctrl_access_during_key_req.2342286464 |
Directory | /workspace/35.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_alert_test.4266057599 |
Short name | T657 |
Test name | |
Test status | |
Simulation time | 178799779 ps |
CPU time | 0.7 seconds |
Started | Jul 20 06:15:34 PM PDT 24 |
Finished | Jul 20 06:15:36 PM PDT 24 |
Peak memory | 202624 kb |
Host | smart-2cd56a6f-43b2-4a48-85fa-6ebdd6a22114 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266057599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_alert_test.4266057599 |
Directory | /workspace/35.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_bijection.2687129984 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 422477907637 ps |
CPU time | 1407.95 seconds |
Started | Jul 20 06:15:14 PM PDT 24 |
Finished | Jul 20 06:38:43 PM PDT 24 |
Peak memory | 203492 kb |
Host | smart-2c5f064b-c3d2-42fb-a512-340163d51a57 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687129984 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection .2687129984 |
Directory | /workspace/35.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_executable.1342554020 |
Short name | T801 |
Test name | |
Test status | |
Simulation time | 1660962193 ps |
CPU time | 139.6 seconds |
Started | Jul 20 06:15:28 PM PDT 24 |
Finished | Jul 20 06:17:48 PM PDT 24 |
Peak memory | 347848 kb |
Host | smart-782c54ef-6a44-4b3e-b726-2e6a3d65df64 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342554020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab le.1342554020 |
Directory | /workspace/35.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_lc_escalation.1813142143 |
Short name | T621 |
Test name | |
Test status | |
Simulation time | 7625293371 ps |
CPU time | 44.63 seconds |
Started | Jul 20 06:15:26 PM PDT 24 |
Finished | Jul 20 06:16:12 PM PDT 24 |
Peak memory | 211076 kb |
Host | smart-21fdac1c-8337-400f-84f9-569642f4adb1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813142143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es calation.1813142143 |
Directory | /workspace/35.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_max_throughput.3465717233 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 1593087472 ps |
CPU time | 110.4 seconds |
Started | Jul 20 06:15:18 PM PDT 24 |
Finished | Jul 20 06:17:08 PM PDT 24 |
Peak memory | 371492 kb |
Host | smart-274ec112-851a-4f89-89be-bb2242309c18 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465717233 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 35.sram_ctrl_max_throughput.3465717233 |
Directory | /workspace/35.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_partial_access.813539905 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 29051618676 ps |
CPU time | 172.98 seconds |
Started | Jul 20 06:15:26 PM PDT 24 |
Finished | Jul 20 06:18:20 PM PDT 24 |
Peak memory | 211116 kb |
Host | smart-43516c91-b3e4-4b19-a98b-67d96ff4964c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813539905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35 .sram_ctrl_mem_partial_access.813539905 |
Directory | /workspace/35.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_mem_walk.2726472490 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 5976680247 ps |
CPU time | 152.67 seconds |
Started | Jul 20 06:15:26 PM PDT 24 |
Finished | Jul 20 06:18:00 PM PDT 24 |
Peak memory | 211056 kb |
Host | smart-19b8dcf5-5db7-47fe-969c-5270953d865b |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726472490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr l_mem_walk.2726472490 |
Directory | /workspace/35.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_multiple_keys.608556986 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 17345724008 ps |
CPU time | 67.49 seconds |
Started | Jul 20 06:15:19 PM PDT 24 |
Finished | Jul 20 06:16:27 PM PDT 24 |
Peak memory | 212940 kb |
Host | smart-02467c92-acdf-4de0-ae04-54f7e1642240 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608556986 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multip le_keys.608556986 |
Directory | /workspace/35.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access.922279142 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 437312549 ps |
CPU time | 7.12 seconds |
Started | Jul 20 06:15:16 PM PDT 24 |
Finished | Jul 20 06:15:23 PM PDT 24 |
Peak memory | 218260 kb |
Host | smart-38c7a129-234c-43d1-8a06-f774a018580b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922279142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.s ram_ctrl_partial_access.922279142 |
Directory | /workspace/35.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.4098605185 |
Short name | T776 |
Test name | |
Test status | |
Simulation time | 112027544744 ps |
CPU time | 477.85 seconds |
Started | Jul 20 06:15:18 PM PDT 24 |
Finished | Jul 20 06:23:17 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-1401eecb-29c1-4904-a766-4a452a3d63a9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098605185 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_partial_access_b2b.4098605185 |
Directory | /workspace/35.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_ram_cfg.87658718 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 2832921768 ps |
CPU time | 3.51 seconds |
Started | Jul 20 06:15:26 PM PDT 24 |
Finished | Jul 20 06:15:30 PM PDT 24 |
Peak memory | 202960 kb |
Host | smart-e82cd4ae-3186-4462-b526-f66a5020c0f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87658718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cf g_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.87658718 |
Directory | /workspace/35.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_regwen.793005111 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 5109403590 ps |
CPU time | 328.39 seconds |
Started | Jul 20 06:15:23 PM PDT 24 |
Finished | Jul 20 06:20:52 PM PDT 24 |
Peak memory | 357704 kb |
Host | smart-1230a518-a2c6-43b0-943b-734929306fc4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793005111 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.793005111 |
Directory | /workspace/35.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_smoke.3243863317 |
Short name | T577 |
Test name | |
Test status | |
Simulation time | 3170837772 ps |
CPU time | 24.87 seconds |
Started | Jul 20 06:15:19 PM PDT 24 |
Finished | Jul 20 06:15:44 PM PDT 24 |
Peak memory | 259592 kb |
Host | smart-8f440768-3600-49e0-be1c-56fcfcee721f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243863317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.3243863317 |
Directory | /workspace/35.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all.777697023 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 79004609861 ps |
CPU time | 4355.89 seconds |
Started | Jul 20 06:15:26 PM PDT 24 |
Finished | Jul 20 07:28:03 PM PDT 24 |
Peak memory | 369764 kb |
Host | smart-0ff4b8ee-c899-4bd3-add3-7dbfd4f1a8d5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777697023 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 35.sram_ctrl_stress_all.777697023 |
Directory | /workspace/35.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4245519614 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 1069444176 ps |
CPU time | 39.56 seconds |
Started | Jul 20 06:15:28 PM PDT 24 |
Finished | Jul 20 06:16:08 PM PDT 24 |
Peak memory | 265236 kb |
Host | smart-9a6ba58d-dc6f-47c8-a7d6-50542cb1f756 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4245519614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_stress_all_with_rand_reset.4245519614 |
Directory | /workspace/35.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_stress_pipeline.1059341680 |
Short name | T877 |
Test name | |
Test status | |
Simulation time | 22582258260 ps |
CPU time | 453.01 seconds |
Started | Jul 20 06:15:18 PM PDT 24 |
Finished | Jul 20 06:22:52 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-2be31320-0cae-40c5-ad78-a2798fc2387c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059341680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 5.sram_ctrl_stress_pipeline.1059341680 |
Directory | /workspace/35.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.65690772 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 2992038388 ps |
CPU time | 57.37 seconds |
Started | Jul 20 06:15:18 PM PDT 24 |
Finished | Jul 20 06:16:16 PM PDT 24 |
Peak memory | 318284 kb |
Host | smart-90f01b7b-32a9-4c4b-918b-b32a5bd65964 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65690772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.sram_ctrl_throughput_w_partial_write.65690772 |
Directory | /workspace/35.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_access_during_key_req.69417150 |
Short name | T814 |
Test name | |
Test status | |
Simulation time | 33197629983 ps |
CPU time | 404.82 seconds |
Started | Jul 20 06:15:34 PM PDT 24 |
Finished | Jul 20 06:22:19 PM PDT 24 |
Peak memory | 374304 kb |
Host | smart-c0c04e89-761c-4499-8fe0-81a487adccae |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69417150 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 36.sram_ctrl_access_during_key_req.69417150 |
Directory | /workspace/36.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_alert_test.755817444 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 62163503 ps |
CPU time | 0.68 seconds |
Started | Jul 20 06:15:42 PM PDT 24 |
Finished | Jul 20 06:15:44 PM PDT 24 |
Peak memory | 202472 kb |
Host | smart-e7c9ddeb-f584-4520-b487-db3c8726718c |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755817444 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_alert_test.755817444 |
Directory | /workspace/36.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_bijection.3469083666 |
Short name | T721 |
Test name | |
Test status | |
Simulation time | 479427795552 ps |
CPU time | 2792.41 seconds |
Started | Jul 20 06:15:34 PM PDT 24 |
Finished | Jul 20 07:02:07 PM PDT 24 |
Peak memory | 203140 kb |
Host | smart-7c9e89cc-fcd2-44dd-baca-04357650baa6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469083666 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection .3469083666 |
Directory | /workspace/36.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_executable.983346982 |
Short name | T769 |
Test name | |
Test status | |
Simulation time | 23830937173 ps |
CPU time | 1099.69 seconds |
Started | Jul 20 06:15:42 PM PDT 24 |
Finished | Jul 20 06:34:03 PM PDT 24 |
Peak memory | 371616 kb |
Host | smart-b76bbd3d-f2b7-4f75-9847-50cb8a8bd785 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983346982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executabl e.983346982 |
Directory | /workspace/36.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_lc_escalation.3434650351 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 7075844638 ps |
CPU time | 43.94 seconds |
Started | Jul 20 06:15:30 PM PDT 24 |
Finished | Jul 20 06:16:15 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-0fe3755e-2efd-4872-a4ea-8914b32fef71 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434650351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es calation.3434650351 |
Directory | /workspace/36.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_max_throughput.1009160284 |
Short name | T688 |
Test name | |
Test status | |
Simulation time | 732850608 ps |
CPU time | 43.87 seconds |
Started | Jul 20 06:15:30 PM PDT 24 |
Finished | Jul 20 06:16:15 PM PDT 24 |
Peak memory | 300980 kb |
Host | smart-b4933304-a641-447f-ab6e-826021bcac2a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009160284 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 36.sram_ctrl_max_throughput.1009160284 |
Directory | /workspace/36.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_mem_walk.1485344378 |
Short name | T729 |
Test name | |
Test status | |
Simulation time | 1978098499 ps |
CPU time | 131.02 seconds |
Started | Jul 20 06:15:42 PM PDT 24 |
Finished | Jul 20 06:17:55 PM PDT 24 |
Peak memory | 210920 kb |
Host | smart-95ca3315-1ef0-438a-bfff-ec8731c038e7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485344378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctr l_mem_walk.1485344378 |
Directory | /workspace/36.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_multiple_keys.4078540858 |
Short name | T918 |
Test name | |
Test status | |
Simulation time | 19782278037 ps |
CPU time | 1475.59 seconds |
Started | Jul 20 06:15:33 PM PDT 24 |
Finished | Jul 20 06:40:09 PM PDT 24 |
Peak memory | 375644 kb |
Host | smart-53b7d866-f7e7-45a0-84d4-d4d0678180c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078540858 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi ple_keys.4078540858 |
Directory | /workspace/36.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access.15210624 |
Short name | T615 |
Test name | |
Test status | |
Simulation time | 998930160 ps |
CPU time | 168.09 seconds |
Started | Jul 20 06:15:35 PM PDT 24 |
Finished | Jul 20 06:18:24 PM PDT 24 |
Peak memory | 369456 kb |
Host | smart-85a4d59b-b420-4c75-8b1a-8126c6e5362b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15210624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE ST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sr am_ctrl_partial_access.15210624 |
Directory | /workspace/36.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3969698519 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 12280907456 ps |
CPU time | 298.11 seconds |
Started | Jul 20 06:15:34 PM PDT 24 |
Finished | Jul 20 06:20:32 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-ac63db94-6100-427d-922c-9d54f43a122c |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969698519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 36.sram_ctrl_partial_access_b2b.3969698519 |
Directory | /workspace/36.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_ram_cfg.1985022066 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 717467795 ps |
CPU time | 3.28 seconds |
Started | Jul 20 06:15:40 PM PDT 24 |
Finished | Jul 20 06:15:45 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-895b9292-871a-44ea-b83f-cd72ade6a180 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985022066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.1985022066 |
Directory | /workspace/36.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_regwen.1974608254 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 17525439678 ps |
CPU time | 953.68 seconds |
Started | Jul 20 06:15:42 PM PDT 24 |
Finished | Jul 20 06:31:36 PM PDT 24 |
Peak memory | 374632 kb |
Host | smart-c13b4f70-ced9-4bdd-ac31-2ccbc2757ca0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974608254 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.1974608254 |
Directory | /workspace/36.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_smoke.3129241065 |
Short name | T853 |
Test name | |
Test status | |
Simulation time | 3411359648 ps |
CPU time | 13.94 seconds |
Started | Jul 20 06:15:34 PM PDT 24 |
Finished | Jul 20 06:15:48 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-59da89e2-5696-475a-93d3-29d77b6cbd70 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129241065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.3129241065 |
Directory | /workspace/36.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all.1502031235 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 417835218929 ps |
CPU time | 3293.82 seconds |
Started | Jul 20 06:15:43 PM PDT 24 |
Finished | Jul 20 07:10:38 PM PDT 24 |
Peak memory | 387000 kb |
Host | smart-65f38240-3b8b-4885-9afe-151c7d5c8476 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502031235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 36.sram_ctrl_stress_all.1502031235 |
Directory | /workspace/36.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.257264080 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 1361983691 ps |
CPU time | 194.42 seconds |
Started | Jul 20 06:15:38 PM PDT 24 |
Finished | Jul 20 06:18:53 PM PDT 24 |
Peak memory | 371472 kb |
Host | smart-1b39b2c8-aeb7-4cbd-aedf-bdc2577f4ac0 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=257264080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_stress_all_with_rand_reset.257264080 |
Directory | /workspace/36.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_stress_pipeline.3806438213 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 5078129462 ps |
CPU time | 186.44 seconds |
Started | Jul 20 06:15:33 PM PDT 24 |
Finished | Jul 20 06:18:40 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-cbd71beb-b110-4a9c-be94-6ddf49ae3b5c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806438213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 6.sram_ctrl_stress_pipeline.3806438213 |
Directory | /workspace/36.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2778425234 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 5323823798 ps |
CPU time | 62.35 seconds |
Started | Jul 20 06:15:30 PM PDT 24 |
Finished | Jul 20 06:16:33 PM PDT 24 |
Peak memory | 313688 kb |
Host | smart-9df2e614-179b-4594-b9ec-106b766c4316 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778425234 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.2778425234 |
Directory | /workspace/36.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_access_during_key_req.3894181853 |
Short name | T716 |
Test name | |
Test status | |
Simulation time | 4897153789 ps |
CPU time | 298.19 seconds |
Started | Jul 20 06:15:42 PM PDT 24 |
Finished | Jul 20 06:20:40 PM PDT 24 |
Peak memory | 360996 kb |
Host | smart-83c3f07a-8597-4977-baf9-480c349759b5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894181853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 37.sram_ctrl_access_during_key_req.3894181853 |
Directory | /workspace/37.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_alert_test.1073337609 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 40239984 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:15:46 PM PDT 24 |
Finished | Jul 20 06:15:47 PM PDT 24 |
Peak memory | 202800 kb |
Host | smart-5f38f971-983e-49da-a271-05ae4ed99805 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073337609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_alert_test.1073337609 |
Directory | /workspace/37.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_bijection.231538603 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 57706904012 ps |
CPU time | 975.32 seconds |
Started | Jul 20 06:15:40 PM PDT 24 |
Finished | Jul 20 06:31:57 PM PDT 24 |
Peak memory | 203744 kb |
Host | smart-e3bc821b-5e7f-4ab2-947e-ea4679c3a82c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231538603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection. 231538603 |
Directory | /workspace/37.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_executable.44004142 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 10041556155 ps |
CPU time | 1129.65 seconds |
Started | Jul 20 06:15:39 PM PDT 24 |
Finished | Jul 20 06:34:30 PM PDT 24 |
Peak memory | 372652 kb |
Host | smart-a0a9b2a3-0364-4114-b040-a5c35a2621d0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44004142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executable .44004142 |
Directory | /workspace/37.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_lc_escalation.3293645951 |
Short name | T645 |
Test name | |
Test status | |
Simulation time | 12748872484 ps |
CPU time | 41.06 seconds |
Started | Jul 20 06:15:40 PM PDT 24 |
Finished | Jul 20 06:16:21 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-167c0c34-a4a4-4a4a-8351-39850030b68b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293645951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_es calation.3293645951 |
Directory | /workspace/37.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_max_throughput.2114691804 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 3051290830 ps |
CPU time | 121.92 seconds |
Started | Jul 20 06:15:42 PM PDT 24 |
Finished | Jul 20 06:17:45 PM PDT 24 |
Peak memory | 372580 kb |
Host | smart-689abc8c-1e6f-4993-a563-7d9566487b05 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114691804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 37.sram_ctrl_max_throughput.2114691804 |
Directory | /workspace/37.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_partial_access.330080727 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 10178183369 ps |
CPU time | 150.02 seconds |
Started | Jul 20 06:15:50 PM PDT 24 |
Finished | Jul 20 06:18:21 PM PDT 24 |
Peak memory | 211124 kb |
Host | smart-b9dec1b0-7942-42a1-9164-7b7d8d4b7163 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330080727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37 .sram_ctrl_mem_partial_access.330080727 |
Directory | /workspace/37.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_mem_walk.2079664498 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 14378529469 ps |
CPU time | 308.15 seconds |
Started | Jul 20 06:15:43 PM PDT 24 |
Finished | Jul 20 06:20:52 PM PDT 24 |
Peak memory | 210992 kb |
Host | smart-542ec2c8-b66b-43b8-9da4-ce15597fb124 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079664498 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr l_mem_walk.2079664498 |
Directory | /workspace/37.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_multiple_keys.17208983 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 11052156294 ps |
CPU time | 469.14 seconds |
Started | Jul 20 06:15:43 PM PDT 24 |
Finished | Jul 20 06:23:33 PM PDT 24 |
Peak memory | 357712 kb |
Host | smart-7af538ed-0a2d-4c85-9a47-4d1c6deee055 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17208983 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multipl e_keys.17208983 |
Directory | /workspace/37.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access.2584721414 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 6633196371 ps |
CPU time | 8.45 seconds |
Started | Jul 20 06:15:41 PM PDT 24 |
Finished | Jul 20 06:15:50 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-d53f62b1-1fef-4e5a-a0a0-5afa5ec5b92d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584721414 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37. sram_ctrl_partial_access.2584721414 |
Directory | /workspace/37.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1537342507 |
Short name | T709 |
Test name | |
Test status | |
Simulation time | 12918659387 ps |
CPU time | 195.57 seconds |
Started | Jul 20 06:15:43 PM PDT 24 |
Finished | Jul 20 06:18:59 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-eed9ec7a-95ac-440b-9f6e-100c3919dc77 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537342507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 37.sram_ctrl_partial_access_b2b.1537342507 |
Directory | /workspace/37.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_ram_cfg.2724114745 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 1686753689 ps |
CPU time | 3.39 seconds |
Started | Jul 20 06:15:43 PM PDT 24 |
Finished | Jul 20 06:15:48 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-f1535c99-0bbc-4a36-8dfe-04c2e2854d9c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724114745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.2724114745 |
Directory | /workspace/37.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_regwen.4106749585 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 2556902351 ps |
CPU time | 1082.42 seconds |
Started | Jul 20 06:15:42 PM PDT 24 |
Finished | Jul 20 06:33:46 PM PDT 24 |
Peak memory | 379828 kb |
Host | smart-7b32c793-46b7-44fb-9a6c-2dc324aeefd3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106749585 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.4106749585 |
Directory | /workspace/37.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_smoke.3672590491 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 3237921227 ps |
CPU time | 97.68 seconds |
Started | Jul 20 06:15:43 PM PDT 24 |
Finished | Jul 20 06:17:21 PM PDT 24 |
Peak memory | 333688 kb |
Host | smart-1c5d62e6-8a3f-40fb-86fc-fe48d6ff1d2a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672590491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.3672590491 |
Directory | /workspace/37.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all.3645658427 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 302784007855 ps |
CPU time | 5401.87 seconds |
Started | Jul 20 06:15:48 PM PDT 24 |
Finished | Jul 20 07:45:51 PM PDT 24 |
Peak memory | 374700 kb |
Host | smart-fb3883bf-aceb-4784-8b4c-e90beb81cb7d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645658427 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 37.sram_ctrl_stress_all.3645658427 |
Directory | /workspace/37.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.3950639885 |
Short name | T689 |
Test name | |
Test status | |
Simulation time | 3439988471 ps |
CPU time | 50.03 seconds |
Started | Jul 20 06:15:50 PM PDT 24 |
Finished | Jul 20 06:16:41 PM PDT 24 |
Peak memory | 244336 kb |
Host | smart-0f489aa1-eea7-4323-b24b-406bf32f39c7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3950639885 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_stress_all_with_rand_reset.3950639885 |
Directory | /workspace/37.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_stress_pipeline.4134016587 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 3782302182 ps |
CPU time | 126.1 seconds |
Started | Jul 20 06:15:42 PM PDT 24 |
Finished | Jul 20 06:17:48 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-fe880577-ca14-43e4-8d4a-35f7b6e6fe35 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134016587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 7.sram_ctrl_stress_pipeline.4134016587 |
Directory | /workspace/37.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3802089059 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 3163338997 ps |
CPU time | 89.22 seconds |
Started | Jul 20 06:15:39 PM PDT 24 |
Finished | Jul 20 06:17:09 PM PDT 24 |
Peak memory | 341984 kb |
Host | smart-627af2b3-a757-40d5-85c2-806d4b6457ac |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802089059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sram_ctrl_throughput_w_partial_write.3802089059 |
Directory | /workspace/37.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_access_during_key_req.1368050112 |
Short name | T798 |
Test name | |
Test status | |
Simulation time | 12254375554 ps |
CPU time | 309.68 seconds |
Started | Jul 20 06:15:48 PM PDT 24 |
Finished | Jul 20 06:20:58 PM PDT 24 |
Peak memory | 375656 kb |
Host | smart-d6885ee4-a83b-4e13-9d07-244ca4e3614b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368050112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 38.sram_ctrl_access_during_key_req.1368050112 |
Directory | /workspace/38.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_alert_test.77274484 |
Short name | T896 |
Test name | |
Test status | |
Simulation time | 53562788 ps |
CPU time | 0.66 seconds |
Started | Jul 20 06:15:56 PM PDT 24 |
Finished | Jul 20 06:15:57 PM PDT 24 |
Peak memory | 202488 kb |
Host | smart-4e1188fd-d49f-4beb-9ed4-ad066633874b |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77274484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_alert_test.77274484 |
Directory | /workspace/38.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_bijection.4116956160 |
Short name | T598 |
Test name | |
Test status | |
Simulation time | 38616214831 ps |
CPU time | 883.43 seconds |
Started | Jul 20 06:15:52 PM PDT 24 |
Finished | Jul 20 06:30:36 PM PDT 24 |
Peak memory | 203524 kb |
Host | smart-6311640d-33e2-4a6d-a843-2d4ae9453887 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116956160 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection .4116956160 |
Directory | /workspace/38.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_executable.3272515728 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 11867973551 ps |
CPU time | 802.89 seconds |
Started | Jul 20 06:15:51 PM PDT 24 |
Finished | Jul 20 06:29:14 PM PDT 24 |
Peak memory | 379844 kb |
Host | smart-3309d7db-d961-4e4f-8eab-a4d2976aa4f2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272515728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab le.3272515728 |
Directory | /workspace/38.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_lc_escalation.4288065836 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 44931652173 ps |
CPU time | 77.59 seconds |
Started | Jul 20 06:15:47 PM PDT 24 |
Finished | Jul 20 06:17:05 PM PDT 24 |
Peak memory | 203076 kb |
Host | smart-7cd666e2-7b1d-418e-a2a5-bd9f1494fbf9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288065836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es calation.4288065836 |
Directory | /workspace/38.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_max_throughput.645241222 |
Short name | T746 |
Test name | |
Test status | |
Simulation time | 3038637521 ps |
CPU time | 42.83 seconds |
Started | Jul 20 06:15:48 PM PDT 24 |
Finished | Jul 20 06:16:32 PM PDT 24 |
Peak memory | 304108 kb |
Host | smart-85ae42e4-0cc2-4251-a50b-948ccc1a9413 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645241222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.sram_ctrl_max_throughput.645241222 |
Directory | /workspace/38.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_partial_access.3304017921 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 9849988716 ps |
CPU time | 79.69 seconds |
Started | Jul 20 06:15:49 PM PDT 24 |
Finished | Jul 20 06:17:09 PM PDT 24 |
Peak memory | 211080 kb |
Host | smart-91cec8ae-b964-4fcc-b2c3-377d37670c28 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304017921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_mem_partial_access.3304017921 |
Directory | /workspace/38.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_mem_walk.1346221992 |
Short name | T679 |
Test name | |
Test status | |
Simulation time | 10353560909 ps |
CPU time | 167.99 seconds |
Started | Jul 20 06:15:51 PM PDT 24 |
Finished | Jul 20 06:18:39 PM PDT 24 |
Peak memory | 211008 kb |
Host | smart-91e38738-78e3-4866-8a57-1e98c8865c70 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346221992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr l_mem_walk.1346221992 |
Directory | /workspace/38.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_multiple_keys.3337279175 |
Short name | T787 |
Test name | |
Test status | |
Simulation time | 7646840415 ps |
CPU time | 702.69 seconds |
Started | Jul 20 06:15:52 PM PDT 24 |
Finished | Jul 20 06:27:35 PM PDT 24 |
Peak memory | 367480 kb |
Host | smart-6b40e9f1-ba72-41fc-9f2a-70b5bfc2ad35 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337279175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi ple_keys.3337279175 |
Directory | /workspace/38.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access.701703711 |
Short name | T702 |
Test name | |
Test status | |
Simulation time | 740071532 ps |
CPU time | 18.85 seconds |
Started | Jul 20 06:15:50 PM PDT 24 |
Finished | Jul 20 06:16:10 PM PDT 24 |
Peak memory | 262988 kb |
Host | smart-b0c27486-eedc-4a14-bbf5-f0e5b2027f0f |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701703711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.s ram_ctrl_partial_access.701703711 |
Directory | /workspace/38.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1076422581 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 11552097226 ps |
CPU time | 179.99 seconds |
Started | Jul 20 06:15:50 PM PDT 24 |
Finished | Jul 20 06:18:50 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-ab719319-d99e-4bb4-9529-d983d03067d8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076422581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 38.sram_ctrl_partial_access_b2b.1076422581 |
Directory | /workspace/38.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_ram_cfg.2177793465 |
Short name | T908 |
Test name | |
Test status | |
Simulation time | 350956430 ps |
CPU time | 3.13 seconds |
Started | Jul 20 06:15:50 PM PDT 24 |
Finished | Jul 20 06:15:54 PM PDT 24 |
Peak memory | 203100 kb |
Host | smart-923ee217-ca0f-4c40-b3b6-35fb977e138c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177793465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.2177793465 |
Directory | /workspace/38.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_regwen.3711602680 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 144389726877 ps |
CPU time | 1183.7 seconds |
Started | Jul 20 06:15:53 PM PDT 24 |
Finished | Jul 20 06:35:37 PM PDT 24 |
Peak memory | 374684 kb |
Host | smart-f3a718ed-8088-48dc-809b-c2a3f8a2256b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711602680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.3711602680 |
Directory | /workspace/38.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_smoke.183256213 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 2672818718 ps |
CPU time | 6.12 seconds |
Started | Jul 20 06:15:50 PM PDT 24 |
Finished | Jul 20 06:15:57 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-985369de-29b9-45d3-9fe9-94dc7921bada |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183256213 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.183256213 |
Directory | /workspace/38.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all.1112397788 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 11628662715 ps |
CPU time | 63.66 seconds |
Started | Jul 20 06:15:52 PM PDT 24 |
Finished | Jul 20 06:16:56 PM PDT 24 |
Peak memory | 216356 kb |
Host | smart-92226c1b-2741-4bd0-be6f-d54624228b38 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112397788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 38.sram_ctrl_stress_all.1112397788 |
Directory | /workspace/38.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2271373434 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 1149736929 ps |
CPU time | 75.29 seconds |
Started | Jul 20 06:15:47 PM PDT 24 |
Finished | Jul 20 06:17:03 PM PDT 24 |
Peak memory | 293884 kb |
Host | smart-48bac3f6-9a8a-4eae-ba14-f7fef31f069a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2271373434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_stress_all_with_rand_reset.2271373434 |
Directory | /workspace/38.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2272189949 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 20609434567 ps |
CPU time | 260.43 seconds |
Started | Jul 20 06:15:51 PM PDT 24 |
Finished | Jul 20 06:20:12 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-6224d214-2123-4cd8-8bd1-2a7449a553b8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272189949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 8.sram_ctrl_stress_pipeline.2272189949 |
Directory | /workspace/38.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.4129215896 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 1408754812 ps |
CPU time | 7.26 seconds |
Started | Jul 20 06:15:50 PM PDT 24 |
Finished | Jul 20 06:15:58 PM PDT 24 |
Peak memory | 217492 kb |
Host | smart-28d4d07d-225f-4b49-a249-c433297b7312 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129215896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.4129215896 |
Directory | /workspace/38.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_access_during_key_req.4004848791 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 43572682062 ps |
CPU time | 691.7 seconds |
Started | Jul 20 06:16:00 PM PDT 24 |
Finished | Jul 20 06:27:32 PM PDT 24 |
Peak memory | 369552 kb |
Host | smart-f1dff8b7-64cf-49d8-b8f2-46fe586f43fa |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004848791 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 39.sram_ctrl_access_during_key_req.4004848791 |
Directory | /workspace/39.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_alert_test.2133135826 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 17788603 ps |
CPU time | 0.64 seconds |
Started | Jul 20 06:15:59 PM PDT 24 |
Finished | Jul 20 06:16:00 PM PDT 24 |
Peak memory | 202392 kb |
Host | smart-d87eac56-e076-4cd3-85c7-c1c9d94a6eef |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133135826 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_alert_test.2133135826 |
Directory | /workspace/39.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_bijection.1986575518 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 64979866995 ps |
CPU time | 871.66 seconds |
Started | Jul 20 06:15:57 PM PDT 24 |
Finished | Jul 20 06:30:29 PM PDT 24 |
Peak memory | 203428 kb |
Host | smart-fe73c0c9-360e-481a-a790-8178d5fcfba7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986575518 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection .1986575518 |
Directory | /workspace/39.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_executable.2938705798 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 29910740381 ps |
CPU time | 603.06 seconds |
Started | Jul 20 06:15:59 PM PDT 24 |
Finished | Jul 20 06:26:03 PM PDT 24 |
Peak memory | 353368 kb |
Host | smart-f3b41e1a-a2bd-49bc-a7f1-3ebf493cb8d1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938705798 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab le.2938705798 |
Directory | /workspace/39.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_lc_escalation.1068045639 |
Short name | T866 |
Test name | |
Test status | |
Simulation time | 9513504033 ps |
CPU time | 57.56 seconds |
Started | Jul 20 06:16:00 PM PDT 24 |
Finished | Jul 20 06:16:58 PM PDT 24 |
Peak memory | 211120 kb |
Host | smart-f0f7f88e-07d2-40e4-9ccb-36ae220cf27e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068045639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es calation.1068045639 |
Directory | /workspace/39.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_max_throughput.3809720535 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 759046416 ps |
CPU time | 39.41 seconds |
Started | Jul 20 06:15:59 PM PDT 24 |
Finished | Jul 20 06:16:39 PM PDT 24 |
Peak memory | 288784 kb |
Host | smart-6c7edd39-4800-4b82-a423-5c0b57284980 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809720535 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 39.sram_ctrl_max_throughput.3809720535 |
Directory | /workspace/39.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_partial_access.584940747 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 6280899521 ps |
CPU time | 78.09 seconds |
Started | Jul 20 06:15:58 PM PDT 24 |
Finished | Jul 20 06:17:16 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-c10d1d74-c9f6-4ae7-ac86-f3780b4c69c5 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584940747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39 .sram_ctrl_mem_partial_access.584940747 |
Directory | /workspace/39.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_mem_walk.1972341408 |
Short name | T583 |
Test name | |
Test status | |
Simulation time | 7732455240 ps |
CPU time | 249.84 seconds |
Started | Jul 20 06:15:56 PM PDT 24 |
Finished | Jul 20 06:20:06 PM PDT 24 |
Peak memory | 211044 kb |
Host | smart-8c8ef5bb-b9f0-4746-a666-8dac508c4f34 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972341408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr l_mem_walk.1972341408 |
Directory | /workspace/39.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_multiple_keys.2648321819 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 28943507315 ps |
CPU time | 791.5 seconds |
Started | Jul 20 06:15:57 PM PDT 24 |
Finished | Jul 20 06:29:09 PM PDT 24 |
Peak memory | 375612 kb |
Host | smart-ec5b8aa9-ea35-4813-944d-71d0159fc0b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648321819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi ple_keys.2648321819 |
Directory | /workspace/39.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access.3993496163 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 527687930 ps |
CPU time | 157.78 seconds |
Started | Jul 20 06:16:00 PM PDT 24 |
Finished | Jul 20 06:18:38 PM PDT 24 |
Peak memory | 369448 kb |
Host | smart-fb26d59f-3ff7-4e59-bb12-ac2ca78c5090 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993496163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39. sram_ctrl_partial_access.3993496163 |
Directory | /workspace/39.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.4036314268 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 14017783117 ps |
CPU time | 355.34 seconds |
Started | Jul 20 06:15:59 PM PDT 24 |
Finished | Jul 20 06:21:55 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-5d5563a9-98eb-43cf-ad5b-c668d651c5db |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036314268 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 39.sram_ctrl_partial_access_b2b.4036314268 |
Directory | /workspace/39.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_ram_cfg.3403847303 |
Short name | T841 |
Test name | |
Test status | |
Simulation time | 1351515969 ps |
CPU time | 3.23 seconds |
Started | Jul 20 06:16:00 PM PDT 24 |
Finished | Jul 20 06:16:04 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-268c084a-827f-40fa-81aa-cd7623ea1434 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403847303 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.3403847303 |
Directory | /workspace/39.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_regwen.863435831 |
Short name | T861 |
Test name | |
Test status | |
Simulation time | 71232780661 ps |
CPU time | 990.14 seconds |
Started | Jul 20 06:16:01 PM PDT 24 |
Finished | Jul 20 06:32:32 PM PDT 24 |
Peak memory | 374708 kb |
Host | smart-8db61f27-3936-44bc-9925-9e602330bc8c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863435831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.863435831 |
Directory | /workspace/39.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_smoke.1393404173 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 759641208 ps |
CPU time | 63.66 seconds |
Started | Jul 20 06:15:56 PM PDT 24 |
Finished | Jul 20 06:17:00 PM PDT 24 |
Peak memory | 305752 kb |
Host | smart-44285e91-75f8-42c4-8aac-6c4aed987100 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393404173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.1393404173 |
Directory | /workspace/39.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all.2718887196 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 167884204135 ps |
CPU time | 5976.03 seconds |
Started | Jul 20 06:16:01 PM PDT 24 |
Finished | Jul 20 07:55:37 PM PDT 24 |
Peak memory | 383936 kb |
Host | smart-658ffd5d-70e4-49fd-b425-b351cc6b4700 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718887196 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 39.sram_ctrl_stress_all.2718887196 |
Directory | /workspace/39.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3740657 |
Short name | T683 |
Test name | |
Test status | |
Simulation time | 364415320 ps |
CPU time | 6.45 seconds |
Started | Jul 20 06:15:56 PM PDT 24 |
Finished | Jul 20 06:16:03 PM PDT 24 |
Peak memory | 211176 kb |
Host | smart-123e4439-193f-4e2c-8fa8-8469fd850dd0 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3740657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_stress_all_with_rand_reset.3740657 |
Directory | /workspace/39.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_stress_pipeline.574236803 |
Short name | T820 |
Test name | |
Test status | |
Simulation time | 7842936838 ps |
CPU time | 216.19 seconds |
Started | Jul 20 06:15:58 PM PDT 24 |
Finished | Jul 20 06:19:35 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-a1a4817c-2477-431b-9f14-8069ba4f19b3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574236803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39 .sram_ctrl_stress_pipeline.574236803 |
Directory | /workspace/39.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2711747301 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 2954008445 ps |
CPU time | 19.93 seconds |
Started | Jul 20 06:16:00 PM PDT 24 |
Finished | Jul 20 06:16:21 PM PDT 24 |
Peak memory | 260148 kb |
Host | smart-5d12fa62-ee44-4f78-a6e0-054e90c08ef7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711747301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.2711747301 |
Directory | /workspace/39.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_access_during_key_req.2201192426 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 39038177312 ps |
CPU time | 650.36 seconds |
Started | Jul 20 06:12:35 PM PDT 24 |
Finished | Jul 20 06:23:28 PM PDT 24 |
Peak memory | 378780 kb |
Host | smart-6e1f7b4d-ac57-4dd9-8a69-da4e173c9a77 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201192426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.sram_ctrl_access_during_key_req.2201192426 |
Directory | /workspace/4.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_alert_test.2894856491 |
Short name | T735 |
Test name | |
Test status | |
Simulation time | 30536128 ps |
CPU time | 0.68 seconds |
Started | Jul 20 06:12:45 PM PDT 24 |
Finished | Jul 20 06:12:48 PM PDT 24 |
Peak memory | 202644 kb |
Host | smart-6da06724-e3dc-4cfe-bdfb-e04005d47b13 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894856491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_alert_test.2894856491 |
Directory | /workspace/4.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_executable.2708389581 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 22953311300 ps |
CPU time | 889.44 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:27:27 PM PDT 24 |
Peak memory | 382896 kb |
Host | smart-83389048-3a5a-4da9-8065-e8314a0e3c4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708389581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl e.2708389581 |
Directory | /workspace/4.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_lc_escalation.449391680 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 141828902222 ps |
CPU time | 101.04 seconds |
Started | Jul 20 06:12:34 PM PDT 24 |
Finished | Jul 20 06:14:17 PM PDT 24 |
Peak memory | 215168 kb |
Host | smart-f5193b6c-fb91-4d38-8270-35cf6bbbb45b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449391680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esca lation.449391680 |
Directory | /workspace/4.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_max_throughput.3210232454 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 3226792728 ps |
CPU time | 114.06 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:14:40 PM PDT 24 |
Peak memory | 337832 kb |
Host | smart-b382cc9d-8102-491b-a85d-1b42de9f8699 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210232454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.sram_ctrl_max_throughput.3210232454 |
Directory | /workspace/4.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_partial_access.1913060804 |
Short name | T677 |
Test name | |
Test status | |
Simulation time | 2683932738 ps |
CPU time | 70.56 seconds |
Started | Jul 20 06:12:37 PM PDT 24 |
Finished | Jul 20 06:13:49 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-2e876ca1-a969-4ac9-b85c-7a8e21c611ae |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913060804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_mem_partial_access.1913060804 |
Directory | /workspace/4.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_mem_walk.3174369590 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 37522253025 ps |
CPU time | 180.14 seconds |
Started | Jul 20 06:12:37 PM PDT 24 |
Finished | Jul 20 06:15:39 PM PDT 24 |
Peak memory | 202772 kb |
Host | smart-d4e2e494-f19e-4dc2-8800-38a7014daa8a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174369590 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl _mem_walk.3174369590 |
Directory | /workspace/4.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_multiple_keys.3619571171 |
Short name | T785 |
Test name | |
Test status | |
Simulation time | 15150877663 ps |
CPU time | 999.89 seconds |
Started | Jul 20 06:12:37 PM PDT 24 |
Finished | Jul 20 06:29:19 PM PDT 24 |
Peak memory | 380776 kb |
Host | smart-b16d4f2d-519d-4030-8d2e-70f7291eb760 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619571171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multip le_keys.3619571171 |
Directory | /workspace/4.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access.406913717 |
Short name | T858 |
Test name | |
Test status | |
Simulation time | 2735100021 ps |
CPU time | 22.65 seconds |
Started | Jul 20 06:12:33 PM PDT 24 |
Finished | Jul 20 06:12:58 PM PDT 24 |
Peak memory | 202876 kb |
Host | smart-fb7f8af8-5999-4a65-8850-a2c378580ff9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406913717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sr am_ctrl_partial_access.406913717 |
Directory | /workspace/4.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2434342156 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 64696913991 ps |
CPU time | 314.14 seconds |
Started | Jul 20 06:12:31 PM PDT 24 |
Finished | Jul 20 06:17:47 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-c563abfe-4469-4e3f-a0c1-1509cd3f495d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434342156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.sram_ctrl_partial_access_b2b.2434342156 |
Directory | /workspace/4.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_ram_cfg.1415734411 |
Short name | T851 |
Test name | |
Test status | |
Simulation time | 709995157 ps |
CPU time | 3.53 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 06:12:49 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-8a8b34c7-209d-4f49-9cfc-a1870567082f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415734411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.1415734411 |
Directory | /workspace/4.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_regwen.1496649822 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 10194286661 ps |
CPU time | 1283.33 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 06:34:08 PM PDT 24 |
Peak memory | 377804 kb |
Host | smart-ff548784-5226-46b8-aa03-c269fc56a17e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496649822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.1496649822 |
Directory | /workspace/4.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_sec_cm.580173903 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 230043782 ps |
CPU time | 2.1 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:12:40 PM PDT 24 |
Peak memory | 221996 kb |
Host | smart-5b57c662-36c0-4436-881d-5b3029ac1c79 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580173903 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_sec_cm.580173903 |
Directory | /workspace/4.sram_ctrl_sec_cm/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_smoke.2818894120 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 3890659350 ps |
CPU time | 9.05 seconds |
Started | Jul 20 06:12:31 PM PDT 24 |
Finished | Jul 20 06:12:42 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-d8eb2be3-2470-4f64-89f8-4fcadf31f65a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818894120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.2818894120 |
Directory | /workspace/4.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_all.3839243046 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 1050587133867 ps |
CPU time | 5191.82 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 07:39:18 PM PDT 24 |
Peak memory | 362352 kb |
Host | smart-c6e22933-d42a-4543-b8b0-8f62cc08773a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839243046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 4.sram_ctrl_stress_all.3839243046 |
Directory | /workspace/4.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3348691779 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 2936734290 ps |
CPU time | 172.91 seconds |
Started | Jul 20 06:12:36 PM PDT 24 |
Finished | Jul 20 06:15:31 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-3363e92e-c699-460e-8ab7-a0f64222f80d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348691779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .sram_ctrl_stress_pipeline.3348691779 |
Directory | /workspace/4.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3696297093 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 769327741 ps |
CPU time | 129.17 seconds |
Started | Jul 20 06:12:47 PM PDT 24 |
Finished | Jul 20 06:14:58 PM PDT 24 |
Peak memory | 347948 kb |
Host | smart-801d04ad-964c-46af-b32e-fbae4d7a5668 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696297093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sram_ctrl_throughput_w_partial_write.3696297093 |
Directory | /workspace/4.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_access_during_key_req.220202741 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 28734271186 ps |
CPU time | 461.32 seconds |
Started | Jul 20 06:16:11 PM PDT 24 |
Finished | Jul 20 06:23:53 PM PDT 24 |
Peak memory | 352264 kb |
Host | smart-99c1f0d7-56fb-4867-b4f2-0d87984e7af8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220202741 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 40.sram_ctrl_access_during_key_req.220202741 |
Directory | /workspace/40.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_alert_test.1161016563 |
Short name | T584 |
Test name | |
Test status | |
Simulation time | 46953336 ps |
CPU time | 0.67 seconds |
Started | Jul 20 06:16:10 PM PDT 24 |
Finished | Jul 20 06:16:11 PM PDT 24 |
Peak memory | 202656 kb |
Host | smart-2d7337b3-37f8-434e-879c-6dab169c9256 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161016563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_alert_test.1161016563 |
Directory | /workspace/40.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_bijection.3300742690 |
Short name | T737 |
Test name | |
Test status | |
Simulation time | 124883374144 ps |
CPU time | 1462.23 seconds |
Started | Jul 20 06:16:01 PM PDT 24 |
Finished | Jul 20 06:40:24 PM PDT 24 |
Peak memory | 203560 kb |
Host | smart-2fe33b93-3a14-4802-b382-0357ea7718c3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300742690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection .3300742690 |
Directory | /workspace/40.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_executable.2253152075 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 34771999113 ps |
CPU time | 1395.4 seconds |
Started | Jul 20 06:16:08 PM PDT 24 |
Finished | Jul 20 06:39:24 PM PDT 24 |
Peak memory | 379784 kb |
Host | smart-44a488a3-9799-4bc5-a702-3159b23e530a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253152075 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab le.2253152075 |
Directory | /workspace/40.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_lc_escalation.4073981133 |
Short name | T712 |
Test name | |
Test status | |
Simulation time | 5204880294 ps |
CPU time | 35.81 seconds |
Started | Jul 20 06:16:10 PM PDT 24 |
Finished | Jul 20 06:16:47 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-9455611b-9e1c-4f03-bcd9-169e8696b697 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073981133 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es calation.4073981133 |
Directory | /workspace/40.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_max_throughput.587017386 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 770669078 ps |
CPU time | 122.36 seconds |
Started | Jul 20 06:16:12 PM PDT 24 |
Finished | Jul 20 06:18:15 PM PDT 24 |
Peak memory | 370588 kb |
Host | smart-d4c2d7b6-3c3c-4b48-baab-dc586060bdba |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587017386 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 40.sram_ctrl_max_throughput.587017386 |
Directory | /workspace/40.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_partial_access.303590445 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 12752946647 ps |
CPU time | 83.62 seconds |
Started | Jul 20 06:16:04 PM PDT 24 |
Finished | Jul 20 06:17:28 PM PDT 24 |
Peak memory | 211124 kb |
Host | smart-4405f2c3-766a-4da1-ad86-75f2098c9fec |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303590445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40 .sram_ctrl_mem_partial_access.303590445 |
Directory | /workspace/40.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_mem_walk.400155390 |
Short name | T605 |
Test name | |
Test status | |
Simulation time | 105008726769 ps |
CPU time | 317.49 seconds |
Started | Jul 20 06:16:05 PM PDT 24 |
Finished | Jul 20 06:21:23 PM PDT 24 |
Peak memory | 211924 kb |
Host | smart-88385557-871f-41bf-8245-ff5fcb6a7f84 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400155390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl _mem_walk.400155390 |
Directory | /workspace/40.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_multiple_keys.4277483241 |
Short name | T634 |
Test name | |
Test status | |
Simulation time | 11260767912 ps |
CPU time | 1530.03 seconds |
Started | Jul 20 06:16:01 PM PDT 24 |
Finished | Jul 20 06:41:31 PM PDT 24 |
Peak memory | 379840 kb |
Host | smart-896bedfc-807b-42bb-896f-12a2e9c3b790 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277483241 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi ple_keys.4277483241 |
Directory | /workspace/40.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access.4873768 |
Short name | T892 |
Test name | |
Test status | |
Simulation time | 3501349863 ps |
CPU time | 50.47 seconds |
Started | Jul 20 06:16:09 PM PDT 24 |
Finished | Jul 20 06:17:00 PM PDT 24 |
Peak memory | 295932 kb |
Host | smart-b44e70b5-96b9-4565-8719-e3ecf0f553e9 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4873768 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES T_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sra m_ctrl_partial_access.4873768 |
Directory | /workspace/40.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.913549154 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 27618777020 ps |
CPU time | 385.79 seconds |
Started | Jul 20 06:16:09 PM PDT 24 |
Finished | Jul 20 06:22:35 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-be606d9e-af73-449f-b324-e8f49a421ef7 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913549154 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 40.sram_ctrl_partial_access_b2b.913549154 |
Directory | /workspace/40.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_ram_cfg.2872488962 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 345701213 ps |
CPU time | 3.25 seconds |
Started | Jul 20 06:16:08 PM PDT 24 |
Finished | Jul 20 06:16:12 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-50afb4ca-dc20-4d2e-bdf9-06f251da52a4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872488962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.2872488962 |
Directory | /workspace/40.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_regwen.281231970 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 2679865328 ps |
CPU time | 179.94 seconds |
Started | Jul 20 06:16:07 PM PDT 24 |
Finished | Jul 20 06:19:08 PM PDT 24 |
Peak memory | 367492 kb |
Host | smart-fc8ba825-6b60-45c7-808e-c849be037a78 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281231970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.281231970 |
Directory | /workspace/40.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_smoke.3477871655 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 856640130 ps |
CPU time | 12.1 seconds |
Started | Jul 20 06:16:01 PM PDT 24 |
Finished | Jul 20 06:16:13 PM PDT 24 |
Peak memory | 232444 kb |
Host | smart-a6b12ee3-7a7e-4342-b2d2-69a6a57fc806 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477871655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.3477871655 |
Directory | /workspace/40.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all.1058396664 |
Short name | T745 |
Test name | |
Test status | |
Simulation time | 1495784864631 ps |
CPU time | 4994.64 seconds |
Started | Jul 20 06:16:09 PM PDT 24 |
Finished | Jul 20 07:39:25 PM PDT 24 |
Peak memory | 378820 kb |
Host | smart-faf97411-c397-4052-8a3a-2d03a0f2a8f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058396664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 40.sram_ctrl_stress_all.1058396664 |
Directory | /workspace/40.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.2376642364 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 662653795 ps |
CPU time | 18.74 seconds |
Started | Jul 20 06:16:09 PM PDT 24 |
Finished | Jul 20 06:16:28 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-cfb0a109-3736-4443-ac77-e704aa1c01d0 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2376642364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_stress_all_with_rand_reset.2376642364 |
Directory | /workspace/40.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_stress_pipeline.1753723778 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 13077974123 ps |
CPU time | 319.16 seconds |
Started | Jul 20 06:16:01 PM PDT 24 |
Finished | Jul 20 06:21:21 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-891d2f2e-00bb-44af-a5ca-4b82e7064850 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753723778 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 0.sram_ctrl_stress_pipeline.1753723778 |
Directory | /workspace/40.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1454473408 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 1577479852 ps |
CPU time | 65.77 seconds |
Started | Jul 20 06:16:09 PM PDT 24 |
Finished | Jul 20 06:17:16 PM PDT 24 |
Peak memory | 304012 kb |
Host | smart-26cff574-fb25-4ed5-a9b8-f84314f17ef6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454473408 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.1454473408 |
Directory | /workspace/40.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3260647996 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 65447478887 ps |
CPU time | 1108.89 seconds |
Started | Jul 20 06:16:18 PM PDT 24 |
Finished | Jul 20 06:34:47 PM PDT 24 |
Peak memory | 377752 kb |
Host | smart-f7ac44e5-80a7-4014-a840-060a8e51f692 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260647996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 41.sram_ctrl_access_during_key_req.3260647996 |
Directory | /workspace/41.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_alert_test.2112585849 |
Short name | T770 |
Test name | |
Test status | |
Simulation time | 37970064 ps |
CPU time | 0.67 seconds |
Started | Jul 20 06:16:24 PM PDT 24 |
Finished | Jul 20 06:16:26 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-cd726e83-2e53-4056-a447-892db13b87ca |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112585849 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_alert_test.2112585849 |
Directory | /workspace/41.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_executable.776762219 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 2521679548 ps |
CPU time | 50.17 seconds |
Started | Jul 20 06:16:18 PM PDT 24 |
Finished | Jul 20 06:17:08 PM PDT 24 |
Peak memory | 267328 kb |
Host | smart-e7a6952a-97d4-48f7-aaf1-33a670dd5b05 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776762219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executabl e.776762219 |
Directory | /workspace/41.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_lc_escalation.1147118477 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 10623819489 ps |
CPU time | 69.06 seconds |
Started | Jul 20 06:16:20 PM PDT 24 |
Finished | Jul 20 06:17:29 PM PDT 24 |
Peak memory | 216076 kb |
Host | smart-f7923cdc-c2e6-43c1-bf76-edb6c73d2a21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147118477 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es calation.1147118477 |
Directory | /workspace/41.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_max_throughput.2640945221 |
Short name | T779 |
Test name | |
Test status | |
Simulation time | 2496964614 ps |
CPU time | 6.69 seconds |
Started | Jul 20 06:16:20 PM PDT 24 |
Finished | Jul 20 06:16:27 PM PDT 24 |
Peak memory | 212132 kb |
Host | smart-fd6578d7-c417-4673-8883-ee835e6108f5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640945221 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 41.sram_ctrl_max_throughput.2640945221 |
Directory | /workspace/41.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_partial_access.2105028307 |
Short name | T934 |
Test name | |
Test status | |
Simulation time | 3834770914 ps |
CPU time | 64.44 seconds |
Started | Jul 20 06:16:19 PM PDT 24 |
Finished | Jul 20 06:17:24 PM PDT 24 |
Peak memory | 211140 kb |
Host | smart-72142699-b4d7-4201-b1df-a546ef11472e |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105028307 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 1.sram_ctrl_mem_partial_access.2105028307 |
Directory | /workspace/41.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_mem_walk.594917246 |
Short name | T741 |
Test name | |
Test status | |
Simulation time | 19317018427 ps |
CPU time | 334.99 seconds |
Started | Jul 20 06:16:20 PM PDT 24 |
Finished | Jul 20 06:21:56 PM PDT 24 |
Peak memory | 210988 kb |
Host | smart-40aaf244-b4ed-4794-a6f9-d4e10a89a818 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594917246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl _mem_walk.594917246 |
Directory | /workspace/41.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_multiple_keys.1496514380 |
Short name | T580 |
Test name | |
Test status | |
Simulation time | 7203972043 ps |
CPU time | 1680.98 seconds |
Started | Jul 20 06:16:11 PM PDT 24 |
Finished | Jul 20 06:44:13 PM PDT 24 |
Peak memory | 378804 kb |
Host | smart-a6d18b24-125c-4348-89b8-f4548c57be21 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496514380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multi ple_keys.1496514380 |
Directory | /workspace/41.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access.294048184 |
Short name | T701 |
Test name | |
Test status | |
Simulation time | 8864831868 ps |
CPU time | 21.79 seconds |
Started | Jul 20 06:16:11 PM PDT 24 |
Finished | Jul 20 06:16:33 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-7e2216b2-d255-483d-b997-57e6dce8620a |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294048184 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.s ram_ctrl_partial_access.294048184 |
Directory | /workspace/41.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.1051016696 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 12143233685 ps |
CPU time | 266.94 seconds |
Started | Jul 20 06:16:19 PM PDT 24 |
Finished | Jul 20 06:20:46 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-538d204b-c1cf-4dcf-a024-abdf12953012 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051016696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 41.sram_ctrl_partial_access_b2b.1051016696 |
Directory | /workspace/41.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_ram_cfg.1874466982 |
Short name | T594 |
Test name | |
Test status | |
Simulation time | 1350853967 ps |
CPU time | 3.14 seconds |
Started | Jul 20 06:16:20 PM PDT 24 |
Finished | Jul 20 06:16:23 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-3b1626e0-f9a9-4f31-ba1f-e931dbc18262 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874466982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1874466982 |
Directory | /workspace/41.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_regwen.2097191058 |
Short name | T646 |
Test name | |
Test status | |
Simulation time | 4400282880 ps |
CPU time | 142.81 seconds |
Started | Jul 20 06:16:23 PM PDT 24 |
Finished | Jul 20 06:18:46 PM PDT 24 |
Peak memory | 313620 kb |
Host | smart-6513d88c-6702-4e82-91dd-6a3d5a49ea4a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097191058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.2097191058 |
Directory | /workspace/41.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_smoke.396176274 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 816072645 ps |
CPU time | 66.93 seconds |
Started | Jul 20 06:16:09 PM PDT 24 |
Finished | Jul 20 06:17:17 PM PDT 24 |
Peak memory | 323452 kb |
Host | smart-11524df4-f079-4997-a739-ee5943a63d16 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396176274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.396176274 |
Directory | /workspace/41.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all.3341347684 |
Short name | T808 |
Test name | |
Test status | |
Simulation time | 1046013349672 ps |
CPU time | 6162.69 seconds |
Started | Jul 20 06:16:27 PM PDT 24 |
Finished | Jul 20 07:59:11 PM PDT 24 |
Peak memory | 379836 kb |
Host | smart-6d48856c-a892-4a3d-8c78-5c1b00b242db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341347684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 41.sram_ctrl_stress_all.3341347684 |
Directory | /workspace/41.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1557392995 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 321162381 ps |
CPU time | 11.02 seconds |
Started | Jul 20 06:16:23 PM PDT 24 |
Finished | Jul 20 06:16:34 PM PDT 24 |
Peak memory | 218504 kb |
Host | smart-4f81e4e9-5c63-439b-be1b-f817cc39b2e7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1557392995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_stress_all_with_rand_reset.1557392995 |
Directory | /workspace/41.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_stress_pipeline.534276475 |
Short name | T676 |
Test name | |
Test status | |
Simulation time | 9951520668 ps |
CPU time | 173.6 seconds |
Started | Jul 20 06:16:09 PM PDT 24 |
Finished | Jul 20 06:19:04 PM PDT 24 |
Peak memory | 202912 kb |
Host | smart-3503ae97-9f94-4ad6-aad6-dac7b169dd08 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534276475 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41 .sram_ctrl_stress_pipeline.534276475 |
Directory | /workspace/41.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2232329072 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 3574044017 ps |
CPU time | 154.58 seconds |
Started | Jul 20 06:16:18 PM PDT 24 |
Finished | Jul 20 06:18:53 PM PDT 24 |
Peak memory | 370808 kb |
Host | smart-1abb78ec-99dd-4f92-9323-a2151c1848f0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232329072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.2232329072 |
Directory | /workspace/41.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_access_during_key_req.463484231 |
Short name | T871 |
Test name | |
Test status | |
Simulation time | 74978514048 ps |
CPU time | 2143.23 seconds |
Started | Jul 20 06:16:28 PM PDT 24 |
Finished | Jul 20 06:52:12 PM PDT 24 |
Peak memory | 379756 kb |
Host | smart-b4f56dfa-af14-4492-a49b-27eea29e3793 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463484231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 42.sram_ctrl_access_during_key_req.463484231 |
Directory | /workspace/42.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_bijection.3943774592 |
Short name | T608 |
Test name | |
Test status | |
Simulation time | 31809379952 ps |
CPU time | 2324.22 seconds |
Started | Jul 20 06:16:25 PM PDT 24 |
Finished | Jul 20 06:55:10 PM PDT 24 |
Peak memory | 203620 kb |
Host | smart-0d52811f-b582-475a-946a-7b311f916b15 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943774592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection .3943774592 |
Directory | /workspace/42.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_executable.3014750323 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 8715124105 ps |
CPU time | 649.54 seconds |
Started | Jul 20 06:16:28 PM PDT 24 |
Finished | Jul 20 06:27:18 PM PDT 24 |
Peak memory | 380744 kb |
Host | smart-68dde433-567c-45b3-acdb-269243c471d9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014750323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab le.3014750323 |
Directory | /workspace/42.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_lc_escalation.4185081049 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 11167098825 ps |
CPU time | 61.23 seconds |
Started | Jul 20 06:16:27 PM PDT 24 |
Finished | Jul 20 06:17:29 PM PDT 24 |
Peak memory | 211136 kb |
Host | smart-9f50bcd0-1801-4c79-a0a2-d9bcbf6ee179 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185081049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es calation.4185081049 |
Directory | /workspace/42.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_max_throughput.2654757831 |
Short name | T837 |
Test name | |
Test status | |
Simulation time | 888121105 ps |
CPU time | 56.11 seconds |
Started | Jul 20 06:16:27 PM PDT 24 |
Finished | Jul 20 06:17:25 PM PDT 24 |
Peak memory | 304052 kb |
Host | smart-30599e8f-a49d-453a-bbf9-83355e65d062 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654757831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 42.sram_ctrl_max_throughput.2654757831 |
Directory | /workspace/42.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_partial_access.2742388805 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 975850728 ps |
CPU time | 65.82 seconds |
Started | Jul 20 06:16:29 PM PDT 24 |
Finished | Jul 20 06:17:35 PM PDT 24 |
Peak memory | 211028 kb |
Host | smart-f2ae23d8-19de-41bb-9cb7-a83bdba3942c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742388805 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_mem_partial_access.2742388805 |
Directory | /workspace/42.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_mem_walk.1151014551 |
Short name | T816 |
Test name | |
Test status | |
Simulation time | 98851385088 ps |
CPU time | 365.56 seconds |
Started | Jul 20 06:16:26 PM PDT 24 |
Finished | Jul 20 06:22:32 PM PDT 24 |
Peak memory | 211000 kb |
Host | smart-406e498e-ce29-43cb-98ab-0a87e19b170a |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151014551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctr l_mem_walk.1151014551 |
Directory | /workspace/42.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_multiple_keys.169931180 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 11051999630 ps |
CPU time | 470.83 seconds |
Started | Jul 20 06:16:27 PM PDT 24 |
Finished | Jul 20 06:24:18 PM PDT 24 |
Peak memory | 353108 kb |
Host | smart-486fb39e-f9c3-4b93-9767-11da9de8edb9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169931180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multip le_keys.169931180 |
Directory | /workspace/42.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access.810704225 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 657197327 ps |
CPU time | 20.09 seconds |
Started | Jul 20 06:16:25 PM PDT 24 |
Finished | Jul 20 06:16:46 PM PDT 24 |
Peak memory | 202980 kb |
Host | smart-bc9aa399-2939-4e2b-8edc-423a0133b98d |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810704225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.s ram_ctrl_partial_access.810704225 |
Directory | /workspace/42.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.4007538029 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 101439235334 ps |
CPU time | 575.87 seconds |
Started | Jul 20 06:16:27 PM PDT 24 |
Finished | Jul 20 06:26:03 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-cecdea89-01b8-4587-b6f3-642f648af981 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007538029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_partial_access_b2b.4007538029 |
Directory | /workspace/42.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_ram_cfg.2788827174 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 1405881138 ps |
CPU time | 3.26 seconds |
Started | Jul 20 06:16:25 PM PDT 24 |
Finished | Jul 20 06:16:29 PM PDT 24 |
Peak memory | 202924 kb |
Host | smart-e2570ac3-0874-4339-ad3f-15d51ab753b8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788827174 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.2788827174 |
Directory | /workspace/42.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_regwen.2149893893 |
Short name | T922 |
Test name | |
Test status | |
Simulation time | 55438820312 ps |
CPU time | 1068.51 seconds |
Started | Jul 20 06:16:27 PM PDT 24 |
Finished | Jul 20 06:34:16 PM PDT 24 |
Peak memory | 379708 kb |
Host | smart-8344b769-7f9c-4a23-b681-89bfe53794f0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149893893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.2149893893 |
Directory | /workspace/42.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_smoke.3171907210 |
Short name | T897 |
Test name | |
Test status | |
Simulation time | 2892576108 ps |
CPU time | 13.8 seconds |
Started | Jul 20 06:16:27 PM PDT 24 |
Finished | Jul 20 06:16:42 PM PDT 24 |
Peak memory | 242564 kb |
Host | smart-6fa4e729-a702-45ce-81f7-15516fdf1c13 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171907210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.3171907210 |
Directory | /workspace/42.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all.197766967 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 430603564252 ps |
CPU time | 9805.28 seconds |
Started | Jul 20 06:16:27 PM PDT 24 |
Finished | Jul 20 08:59:54 PM PDT 24 |
Peak memory | 380900 kb |
Host | smart-23870b86-9e74-4517-a4bf-a31e970d91d8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197766967 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 42.sram_ctrl_stress_all.197766967 |
Directory | /workspace/42.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.3583269063 |
Short name | T641 |
Test name | |
Test status | |
Simulation time | 392976163 ps |
CPU time | 14.26 seconds |
Started | Jul 20 06:16:27 PM PDT 24 |
Finished | Jul 20 06:16:42 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-2138a313-cc96-4f33-9f02-f1efbc2b6685 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3583269063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_stress_all_with_rand_reset.3583269063 |
Directory | /workspace/42.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_stress_pipeline.2012596440 |
Short name | T757 |
Test name | |
Test status | |
Simulation time | 12605114396 ps |
CPU time | 242.51 seconds |
Started | Jul 20 06:16:26 PM PDT 24 |
Finished | Jul 20 06:20:29 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-fae29941-a1ce-42b7-aa45-c61b79231174 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012596440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.sram_ctrl_stress_pipeline.2012596440 |
Directory | /workspace/42.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3678588540 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 804898597 ps |
CPU time | 121.18 seconds |
Started | Jul 20 06:16:28 PM PDT 24 |
Finished | Jul 20 06:18:30 PM PDT 24 |
Peak memory | 352128 kb |
Host | smart-f650f0db-5059-4fa1-9dbe-064573cc8b94 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678588540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sram_ctrl_throughput_w_partial_write.3678588540 |
Directory | /workspace/42.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2881976987 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 11840623794 ps |
CPU time | 728.25 seconds |
Started | Jul 20 06:16:34 PM PDT 24 |
Finished | Jul 20 06:28:43 PM PDT 24 |
Peak memory | 374660 kb |
Host | smart-ac477a31-2be5-4ce4-ac9a-3e1effd48658 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881976987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 43.sram_ctrl_access_during_key_req.2881976987 |
Directory | /workspace/43.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_alert_test.946139155 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 25640232 ps |
CPU time | 0.71 seconds |
Started | Jul 20 06:16:39 PM PDT 24 |
Finished | Jul 20 06:16:40 PM PDT 24 |
Peak memory | 202628 kb |
Host | smart-515b03e4-68e8-4ce9-a843-03d865b54026 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946139155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_alert_test.946139155 |
Directory | /workspace/43.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_bijection.1404876840 |
Short name | T915 |
Test name | |
Test status | |
Simulation time | 207154221739 ps |
CPU time | 1793.68 seconds |
Started | Jul 20 06:16:30 PM PDT 24 |
Finished | Jul 20 06:46:24 PM PDT 24 |
Peak memory | 203548 kb |
Host | smart-bcb9e10b-4fc4-44a3-b18b-6c9a45ac822a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404876840 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection .1404876840 |
Directory | /workspace/43.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_executable.139473517 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 76861342006 ps |
CPU time | 1353.21 seconds |
Started | Jul 20 06:16:32 PM PDT 24 |
Finished | Jul 20 06:39:06 PM PDT 24 |
Peak memory | 376796 kb |
Host | smart-e30fe8b3-a235-4827-aff1-e40639bb1518 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139473517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executabl e.139473517 |
Directory | /workspace/43.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_lc_escalation.4199366980 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 12550785427 ps |
CPU time | 73.25 seconds |
Started | Jul 20 06:16:26 PM PDT 24 |
Finished | Jul 20 06:17:40 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-ffdf851c-5856-449a-aa7f-061640bfc479 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199366980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es calation.4199366980 |
Directory | /workspace/43.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_max_throughput.1746055656 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 819312022 ps |
CPU time | 82.98 seconds |
Started | Jul 20 06:16:24 PM PDT 24 |
Finished | Jul 20 06:17:48 PM PDT 24 |
Peak memory | 358268 kb |
Host | smart-9211c06f-25c9-426c-ae92-2c5b6640d6b7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746055656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 43.sram_ctrl_max_throughput.1746055656 |
Directory | /workspace/43.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_partial_access.4026259101 |
Short name | T905 |
Test name | |
Test status | |
Simulation time | 115903166362 ps |
CPU time | 174.32 seconds |
Started | Jul 20 06:16:33 PM PDT 24 |
Finished | Jul 20 06:19:28 PM PDT 24 |
Peak memory | 214932 kb |
Host | smart-ac2611e9-e66d-4006-b026-26bee4be7059 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026259101 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 3.sram_ctrl_mem_partial_access.4026259101 |
Directory | /workspace/43.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_mem_walk.3482453209 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 10358222458 ps |
CPU time | 165.47 seconds |
Started | Jul 20 06:16:33 PM PDT 24 |
Finished | Jul 20 06:19:19 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-20234cc5-555b-49bd-9c17-60b4faab7b77 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482453209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctr l_mem_walk.3482453209 |
Directory | /workspace/43.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_multiple_keys.2057342237 |
Short name | T691 |
Test name | |
Test status | |
Simulation time | 10290273675 ps |
CPU time | 441.36 seconds |
Started | Jul 20 06:16:27 PM PDT 24 |
Finished | Jul 20 06:23:50 PM PDT 24 |
Peak memory | 376676 kb |
Host | smart-69d585a2-0a7a-43e9-a5d0-eb4b668fa236 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057342237 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multi ple_keys.2057342237 |
Directory | /workspace/43.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_partial_access.128443510 |
Short name | T672 |
Test name | |
Test status | |
Simulation time | 772785436 ps |
CPU time | 15.89 seconds |
Started | Jul 20 06:16:25 PM PDT 24 |
Finished | Jul 20 06:16:41 PM PDT 24 |
Peak memory | 243520 kb |
Host | smart-e0fa9b2e-ea7d-4ef0-951e-84ab3e06ec60 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128443510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.s ram_ctrl_partial_access.128443510 |
Directory | /workspace/43.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_ram_cfg.4080487779 |
Short name | T832 |
Test name | |
Test status | |
Simulation time | 706984057 ps |
CPU time | 3.31 seconds |
Started | Jul 20 06:16:39 PM PDT 24 |
Finished | Jul 20 06:16:43 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-4f9caa60-9c60-49f5-914b-33057d5b2d57 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080487779 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.4080487779 |
Directory | /workspace/43.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_regwen.487216715 |
Short name | T815 |
Test name | |
Test status | |
Simulation time | 5765981065 ps |
CPU time | 550.4 seconds |
Started | Jul 20 06:17:20 PM PDT 24 |
Finished | Jul 20 06:26:31 PM PDT 24 |
Peak memory | 366496 kb |
Host | smart-36248e76-eca8-465a-8a02-c36e3275c013 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487216715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.487216715 |
Directory | /workspace/43.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_smoke.1976931512 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 1917265038 ps |
CPU time | 123.78 seconds |
Started | Jul 20 06:16:28 PM PDT 24 |
Finished | Jul 20 06:18:32 PM PDT 24 |
Peak memory | 365384 kb |
Host | smart-15618abe-db3c-4c79-855b-093ef7c33a05 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976931512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.1976931512 |
Directory | /workspace/43.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1376614942 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 1848559219 ps |
CPU time | 48.41 seconds |
Started | Jul 20 06:16:35 PM PDT 24 |
Finished | Jul 20 06:17:24 PM PDT 24 |
Peak memory | 211868 kb |
Host | smart-56996362-59a8-437d-b684-ce8200775dd3 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1376614942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_stress_all_with_rand_reset.1376614942 |
Directory | /workspace/43.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_stress_pipeline.139097672 |
Short name | T596 |
Test name | |
Test status | |
Simulation time | 18037447730 ps |
CPU time | 199.94 seconds |
Started | Jul 20 06:16:27 PM PDT 24 |
Finished | Jul 20 06:19:48 PM PDT 24 |
Peak memory | 202836 kb |
Host | smart-c5caf07f-f415-4a94-8c8a-6d29c6a63e97 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139097672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43 .sram_ctrl_stress_pipeline.139097672 |
Directory | /workspace/43.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2847045492 |
Short name | T673 |
Test name | |
Test status | |
Simulation time | 2172386881 ps |
CPU time | 13.04 seconds |
Started | Jul 20 06:16:33 PM PDT 24 |
Finished | Jul 20 06:16:46 PM PDT 24 |
Peak memory | 239700 kb |
Host | smart-1ba536a6-991d-40e0-b28d-4c34eee7b750 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847045492 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.2847045492 |
Directory | /workspace/43.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_access_during_key_req.3349295707 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 35561820386 ps |
CPU time | 1030.52 seconds |
Started | Jul 20 06:16:43 PM PDT 24 |
Finished | Jul 20 06:33:54 PM PDT 24 |
Peak memory | 375644 kb |
Host | smart-bb1e2fa3-2986-436b-9253-99e660a06f71 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349295707 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 44.sram_ctrl_access_during_key_req.3349295707 |
Directory | /workspace/44.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_alert_test.2477219032 |
Short name | T669 |
Test name | |
Test status | |
Simulation time | 21199752 ps |
CPU time | 0.65 seconds |
Started | Jul 20 06:16:52 PM PDT 24 |
Finished | Jul 20 06:16:54 PM PDT 24 |
Peak memory | 202500 kb |
Host | smart-11576387-0fff-4ee5-bba9-445f81c39fb3 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477219032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_alert_test.2477219032 |
Directory | /workspace/44.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_bijection.1606889180 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 43521057589 ps |
CPU time | 1667.52 seconds |
Started | Jul 20 06:16:35 PM PDT 24 |
Finished | Jul 20 06:44:24 PM PDT 24 |
Peak memory | 203420 kb |
Host | smart-decdd147-51e1-4369-8688-c4a5a4d304b4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606889180 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection .1606889180 |
Directory | /workspace/44.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_executable.879381803 |
Short name | T766 |
Test name | |
Test status | |
Simulation time | 15593435185 ps |
CPU time | 433.94 seconds |
Started | Jul 20 06:16:42 PM PDT 24 |
Finished | Jul 20 06:23:56 PM PDT 24 |
Peak memory | 371212 kb |
Host | smart-22e216d2-41de-4967-a271-70cd439bd7e6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879381803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executabl e.879381803 |
Directory | /workspace/44.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_lc_escalation.2965674899 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 3427882727 ps |
CPU time | 22.81 seconds |
Started | Jul 20 06:16:43 PM PDT 24 |
Finished | Jul 20 06:17:07 PM PDT 24 |
Peak memory | 202820 kb |
Host | smart-e2a5f935-1399-4c63-b7fb-6989c0b73a84 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965674899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es calation.2965674899 |
Directory | /workspace/44.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_max_throughput.1599514269 |
Short name | T612 |
Test name | |
Test status | |
Simulation time | 3028698968 ps |
CPU time | 19.46 seconds |
Started | Jul 20 06:16:43 PM PDT 24 |
Finished | Jul 20 06:17:04 PM PDT 24 |
Peak memory | 252000 kb |
Host | smart-a893b4bb-a296-4a4d-9ce6-810af7765c68 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599514269 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 44.sram_ctrl_max_throughput.1599514269 |
Directory | /workspace/44.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_partial_access.2187662112 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 33643963623 ps |
CPU time | 79.28 seconds |
Started | Jul 20 06:16:52 PM PDT 24 |
Finished | Jul 20 06:18:12 PM PDT 24 |
Peak memory | 211180 kb |
Host | smart-ce1f1d85-0048-4f5f-ac1d-4bf2bfc0c8fd |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187662112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 4.sram_ctrl_mem_partial_access.2187662112 |
Directory | /workspace/44.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_mem_walk.3305898671 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 14257651517 ps |
CPU time | 334.09 seconds |
Started | Jul 20 06:17:01 PM PDT 24 |
Finished | Jul 20 06:22:36 PM PDT 24 |
Peak memory | 211936 kb |
Host | smart-9f7d3457-02c4-41aa-91ba-bb8f7ec7ca7d |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305898671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr l_mem_walk.3305898671 |
Directory | /workspace/44.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_multiple_keys.3101910617 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 38747853751 ps |
CPU time | 730.11 seconds |
Started | Jul 20 06:16:34 PM PDT 24 |
Finished | Jul 20 06:28:45 PM PDT 24 |
Peak memory | 367492 kb |
Host | smart-0482ab21-fd2a-4299-992f-70181cd11fea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101910617 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi ple_keys.3101910617 |
Directory | /workspace/44.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access.4127565750 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 892188683 ps |
CPU time | 197.27 seconds |
Started | Jul 20 06:16:35 PM PDT 24 |
Finished | Jul 20 06:19:53 PM PDT 24 |
Peak memory | 367376 kb |
Host | smart-41616282-7bf7-430e-9d2b-74f4af7fb357 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127565750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_partial_access.4127565750 |
Directory | /workspace/44.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3088486374 |
Short name | T835 |
Test name | |
Test status | |
Simulation time | 13016759020 ps |
CPU time | 348.69 seconds |
Started | Jul 20 06:16:44 PM PDT 24 |
Finished | Jul 20 06:22:33 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-fee98f88-3dee-40c5-9f45-879e82e2b994 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088486374 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 44.sram_ctrl_partial_access_b2b.3088486374 |
Directory | /workspace/44.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_ram_cfg.4129699656 |
Short name | T846 |
Test name | |
Test status | |
Simulation time | 706887655 ps |
CPU time | 3.24 seconds |
Started | Jul 20 06:16:43 PM PDT 24 |
Finished | Jul 20 06:16:48 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-af98d083-9199-4a24-ad70-0eedc0d71534 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129699656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.4129699656 |
Directory | /workspace/44.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_regwen.547028328 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 3301962811 ps |
CPU time | 642.4 seconds |
Started | Jul 20 06:16:43 PM PDT 24 |
Finished | Jul 20 06:27:26 PM PDT 24 |
Peak memory | 373676 kb |
Host | smart-7aee4e0b-487f-4d6c-92a7-f840f757b858 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547028328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.547028328 |
Directory | /workspace/44.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_smoke.1951396530 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 831600636 ps |
CPU time | 130.89 seconds |
Started | Jul 20 06:16:39 PM PDT 24 |
Finished | Jul 20 06:18:50 PM PDT 24 |
Peak memory | 370432 kb |
Host | smart-e752d274-d965-4bd5-b560-57a7377581f6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951396530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.1951396530 |
Directory | /workspace/44.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all.3774604378 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 193481543336 ps |
CPU time | 6929.96 seconds |
Started | Jul 20 06:16:54 PM PDT 24 |
Finished | Jul 20 08:12:26 PM PDT 24 |
Peak memory | 387976 kb |
Host | smart-5d9bf8e6-9123-4400-8fe0-c83892a3b80e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774604378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 44.sram_ctrl_stress_all.3774604378 |
Directory | /workspace/44.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.1388954153 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 662087770 ps |
CPU time | 9.55 seconds |
Started | Jul 20 06:16:55 PM PDT 24 |
Finished | Jul 20 06:17:05 PM PDT 24 |
Peak memory | 211096 kb |
Host | smart-6c32e249-4a21-4245-9102-27335eeac6ae |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1388954153 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_stress_all_with_rand_reset.1388954153 |
Directory | /workspace/44.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_stress_pipeline.28006804 |
Short name | T828 |
Test name | |
Test status | |
Simulation time | 16302095617 ps |
CPU time | 229.1 seconds |
Started | Jul 20 06:16:36 PM PDT 24 |
Finished | Jul 20 06:20:26 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-5b12d59c-b05c-46a6-a94a-1914c73879e8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28006804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44. sram_ctrl_stress_pipeline.28006804 |
Directory | /workspace/44.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.4226245685 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 774066687 ps |
CPU time | 104.54 seconds |
Started | Jul 20 06:16:42 PM PDT 24 |
Finished | Jul 20 06:18:28 PM PDT 24 |
Peak memory | 344928 kb |
Host | smart-17bdcaa2-9367-4fd9-9cbb-61e4393f6c1d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226245685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.4226245685 |
Directory | /workspace/44.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_access_during_key_req.3276623521 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 40778768688 ps |
CPU time | 393.3 seconds |
Started | Jul 20 06:17:02 PM PDT 24 |
Finished | Jul 20 06:23:36 PM PDT 24 |
Peak memory | 376688 kb |
Host | smart-14df2622-3da8-4c46-9c9e-65cf54c2b783 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276623521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 45.sram_ctrl_access_during_key_req.3276623521 |
Directory | /workspace/45.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_alert_test.2578715499 |
Short name | T910 |
Test name | |
Test status | |
Simulation time | 11604051 ps |
CPU time | 0.7 seconds |
Started | Jul 20 06:16:59 PM PDT 24 |
Finished | Jul 20 06:17:01 PM PDT 24 |
Peak memory | 202488 kb |
Host | smart-bcf75c88-bba2-4ed7-bb0e-a78cd60c4a1e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578715499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_alert_test.2578715499 |
Directory | /workspace/45.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_bijection.910446045 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 59965524569 ps |
CPU time | 1397.59 seconds |
Started | Jul 20 06:17:00 PM PDT 24 |
Finished | Jul 20 06:40:19 PM PDT 24 |
Peak memory | 203524 kb |
Host | smart-c4af4e0f-36b7-4d24-9c9b-b6c42cf6490b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910446045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection. 910446045 |
Directory | /workspace/45.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_executable.1308872680 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 75435664096 ps |
CPU time | 1291.59 seconds |
Started | Jul 20 06:17:02 PM PDT 24 |
Finished | Jul 20 06:38:34 PM PDT 24 |
Peak memory | 379792 kb |
Host | smart-934e035b-6e8e-4aa6-8bfe-8146f0b41442 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308872680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab le.1308872680 |
Directory | /workspace/45.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_lc_escalation.51809570 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 12354127420 ps |
CPU time | 37.09 seconds |
Started | Jul 20 06:17:01 PM PDT 24 |
Finished | Jul 20 06:17:39 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-affd8ffa-1a05-463a-800f-560db24fc4a7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51809570 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_esca lation.51809570 |
Directory | /workspace/45.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_max_throughput.3514120894 |
Short name | T707 |
Test name | |
Test status | |
Simulation time | 2680650172 ps |
CPU time | 6.29 seconds |
Started | Jul 20 06:17:01 PM PDT 24 |
Finished | Jul 20 06:17:07 PM PDT 24 |
Peak memory | 211104 kb |
Host | smart-3c8e0b38-2d11-4709-9daf-cd337180e601 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514120894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 45.sram_ctrl_max_throughput.3514120894 |
Directory | /workspace/45.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2251331566 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 1571158509 ps |
CPU time | 77.74 seconds |
Started | Jul 20 06:17:06 PM PDT 24 |
Finished | Jul 20 06:18:24 PM PDT 24 |
Peak memory | 219164 kb |
Host | smart-7512d433-d0c7-4c9d-9a1d-fff3c04b9f20 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251331566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_mem_partial_access.2251331566 |
Directory | /workspace/45.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_mem_walk.1291225119 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 4810347181 ps |
CPU time | 258.82 seconds |
Started | Jul 20 06:17:03 PM PDT 24 |
Finished | Jul 20 06:21:23 PM PDT 24 |
Peak memory | 211060 kb |
Host | smart-04180154-a2ff-49e0-8f73-b75fa6f4b858 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291225119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctr l_mem_walk.1291225119 |
Directory | /workspace/45.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_multiple_keys.4145078396 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 38648207922 ps |
CPU time | 1071.21 seconds |
Started | Jul 20 06:17:01 PM PDT 24 |
Finished | Jul 20 06:34:53 PM PDT 24 |
Peak memory | 379280 kb |
Host | smart-b5a7cd7e-a336-451e-96fe-d287cee072c7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145078396 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi ple_keys.4145078396 |
Directory | /workspace/45.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access.3219631103 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 4844689096 ps |
CPU time | 7.06 seconds |
Started | Jul 20 06:16:52 PM PDT 24 |
Finished | Jul 20 06:17:00 PM PDT 24 |
Peak memory | 202844 kb |
Host | smart-9bb92012-d820-4b02-8e66-cc1c11287fa5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219631103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45. sram_ctrl_partial_access.3219631103 |
Directory | /workspace/45.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.555150504 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 27041436498 ps |
CPU time | 330.7 seconds |
Started | Jul 20 06:16:51 PM PDT 24 |
Finished | Jul 20 06:22:22 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-eeab8a00-8a0d-465e-ae88-9033d1d48c28 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555150504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 45.sram_ctrl_partial_access_b2b.555150504 |
Directory | /workspace/45.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_ram_cfg.1769825792 |
Short name | T610 |
Test name | |
Test status | |
Simulation time | 366631331 ps |
CPU time | 3.32 seconds |
Started | Jul 20 06:16:53 PM PDT 24 |
Finished | Jul 20 06:16:57 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-3deecce3-abfd-44aa-8009-b230d35ecb82 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769825792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.1769825792 |
Directory | /workspace/45.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_regwen.3694966331 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 19145343262 ps |
CPU time | 1173.74 seconds |
Started | Jul 20 06:16:54 PM PDT 24 |
Finished | Jul 20 06:36:28 PM PDT 24 |
Peak memory | 369524 kb |
Host | smart-d66b1b4f-2ba9-4f77-9a5a-42c5158edc2a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694966331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.3694966331 |
Directory | /workspace/45.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_smoke.3129366680 |
Short name | T833 |
Test name | |
Test status | |
Simulation time | 533638251 ps |
CPU time | 36.82 seconds |
Started | Jul 20 06:16:53 PM PDT 24 |
Finished | Jul 20 06:17:30 PM PDT 24 |
Peak memory | 290788 kb |
Host | smart-ac6e8e3e-2492-4f20-bcd2-996b91a3d65b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129366680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.3129366680 |
Directory | /workspace/45.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all.2704654326 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 332939240314 ps |
CPU time | 5812.77 seconds |
Started | Jul 20 06:17:02 PM PDT 24 |
Finished | Jul 20 07:53:56 PM PDT 24 |
Peak memory | 382392 kb |
Host | smart-56d4df55-43e8-40fe-b74c-228155c789a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704654326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 45.sram_ctrl_stress_all.2704654326 |
Directory | /workspace/45.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.3671927005 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 324718977 ps |
CPU time | 8.13 seconds |
Started | Jul 20 06:16:59 PM PDT 24 |
Finished | Jul 20 06:17:08 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-e8e5d375-906e-40f7-b610-ce8f67f2b6c9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3671927005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_stress_all_with_rand_reset.3671927005 |
Directory | /workspace/45.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1213924069 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 7899543388 ps |
CPU time | 279.87 seconds |
Started | Jul 20 06:16:53 PM PDT 24 |
Finished | Jul 20 06:21:34 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-f514e74b-d020-4dad-af3d-47fd3d716209 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213924069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.sram_ctrl_stress_pipeline.1213924069 |
Directory | /workspace/45.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1881997564 |
Short name | T695 |
Test name | |
Test status | |
Simulation time | 1433369201 ps |
CPU time | 6.29 seconds |
Started | Jul 20 06:16:54 PM PDT 24 |
Finished | Jul 20 06:17:01 PM PDT 24 |
Peak memory | 210932 kb |
Host | smart-827f861a-5d63-42a7-b1d6-7210b384ac55 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881997564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.1881997564 |
Directory | /workspace/45.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3425328832 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 2506976589 ps |
CPU time | 105.15 seconds |
Started | Jul 20 06:17:01 PM PDT 24 |
Finished | Jul 20 06:18:47 PM PDT 24 |
Peak memory | 293948 kb |
Host | smart-117a75ba-c767-4885-892f-95ac732bc30e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425328832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 46.sram_ctrl_access_during_key_req.3425328832 |
Directory | /workspace/46.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_alert_test.1056272471 |
Short name | T797 |
Test name | |
Test status | |
Simulation time | 26138785 ps |
CPU time | 0.67 seconds |
Started | Jul 20 06:17:09 PM PDT 24 |
Finished | Jul 20 06:17:10 PM PDT 24 |
Peak memory | 202636 kb |
Host | smart-d4fb4ffe-877b-4c9c-88ee-74ab39d5ebc4 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056272471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_alert_test.1056272471 |
Directory | /workspace/46.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_bijection.2772000905 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 143237833315 ps |
CPU time | 2772.12 seconds |
Started | Jul 20 06:17:03 PM PDT 24 |
Finished | Jul 20 07:03:16 PM PDT 24 |
Peak memory | 203584 kb |
Host | smart-b62006ae-d7c4-42d5-a48d-5d26f4a5209a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772000905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection .2772000905 |
Directory | /workspace/46.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_executable.272938667 |
Short name | T909 |
Test name | |
Test status | |
Simulation time | 4950732010 ps |
CPU time | 740.2 seconds |
Started | Jul 20 06:16:59 PM PDT 24 |
Finished | Jul 20 06:29:21 PM PDT 24 |
Peak memory | 379776 kb |
Host | smart-7918e588-7309-47fc-9e57-0e48fda95ce7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272938667 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executabl e.272938667 |
Directory | /workspace/46.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_lc_escalation.1115333692 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 147221582110 ps |
CPU time | 110.29 seconds |
Started | Jul 20 06:17:00 PM PDT 24 |
Finished | Jul 20 06:18:51 PM PDT 24 |
Peak memory | 211152 kb |
Host | smart-c0a91a2e-1f24-4311-bb3b-d0272a335e85 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115333692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es calation.1115333692 |
Directory | /workspace/46.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_max_throughput.2512734619 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 4242659985 ps |
CPU time | 107.04 seconds |
Started | Jul 20 06:17:03 PM PDT 24 |
Finished | Jul 20 06:18:51 PM PDT 24 |
Peak memory | 370776 kb |
Host | smart-07de9dfa-ff87-438d-924a-3bb5504d2dc0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512734619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 46.sram_ctrl_max_throughput.2512734619 |
Directory | /workspace/46.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_partial_access.4026459866 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 13176747846 ps |
CPU time | 76.72 seconds |
Started | Jul 20 06:17:08 PM PDT 24 |
Finished | Jul 20 06:18:26 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-0e52bae2-4ee4-43ce-9f7e-bd69f8eef741 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026459866 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.sram_ctrl_mem_partial_access.4026459866 |
Directory | /workspace/46.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_mem_walk.1656800656 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 2061755440 ps |
CPU time | 127.02 seconds |
Started | Jul 20 06:17:08 PM PDT 24 |
Finished | Jul 20 06:19:16 PM PDT 24 |
Peak memory | 210960 kb |
Host | smart-06235329-24a4-4d4f-892c-e09c9a770c44 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656800656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr l_mem_walk.1656800656 |
Directory | /workspace/46.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_multiple_keys.1490935624 |
Short name | T790 |
Test name | |
Test status | |
Simulation time | 19644316175 ps |
CPU time | 1431.91 seconds |
Started | Jul 20 06:17:03 PM PDT 24 |
Finished | Jul 20 06:40:56 PM PDT 24 |
Peak memory | 379692 kb |
Host | smart-02bcbd59-80c3-41f9-ad8d-3d5b778a0679 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490935624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi ple_keys.1490935624 |
Directory | /workspace/46.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access.3565214795 |
Short name | T916 |
Test name | |
Test status | |
Simulation time | 1686977254 ps |
CPU time | 22.25 seconds |
Started | Jul 20 06:16:57 PM PDT 24 |
Finished | Jul 20 06:17:20 PM PDT 24 |
Peak memory | 202776 kb |
Host | smart-37a0e1d4-cbb0-409a-bb9a-2c7945640d9b |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565214795 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46. sram_ctrl_partial_access.3565214795 |
Directory | /workspace/46.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.910334177 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 29244172914 ps |
CPU time | 323.35 seconds |
Started | Jul 20 06:17:01 PM PDT 24 |
Finished | Jul 20 06:22:25 PM PDT 24 |
Peak memory | 202864 kb |
Host | smart-3ca291f6-1594-4ab4-9600-50cec1a32616 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910334177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 46.sram_ctrl_partial_access_b2b.910334177 |
Directory | /workspace/46.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_ram_cfg.3139261966 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 1866870516 ps |
CPU time | 3.68 seconds |
Started | Jul 20 06:17:09 PM PDT 24 |
Finished | Jul 20 06:17:13 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-6f0e558e-360d-4465-a848-1d90607563e8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139261966 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.3139261966 |
Directory | /workspace/46.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_regwen.3109106146 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 9196748572 ps |
CPU time | 852.6 seconds |
Started | Jul 20 06:17:03 PM PDT 24 |
Finished | Jul 20 06:31:17 PM PDT 24 |
Peak memory | 374772 kb |
Host | smart-4cf56f19-21f0-485e-b0a3-df60eb16aa1d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109106146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.3109106146 |
Directory | /workspace/46.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_smoke.2586832905 |
Short name | T807 |
Test name | |
Test status | |
Simulation time | 1476155161 ps |
CPU time | 14.23 seconds |
Started | Jul 20 06:17:01 PM PDT 24 |
Finished | Jul 20 06:17:16 PM PDT 24 |
Peak memory | 239836 kb |
Host | smart-c06ac130-8b77-4a0c-a2b6-6416c4f793ee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586832905 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2586832905 |
Directory | /workspace/46.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all.2715588878 |
Short name | T724 |
Test name | |
Test status | |
Simulation time | 269999838418 ps |
CPU time | 2278.24 seconds |
Started | Jul 20 06:17:06 PM PDT 24 |
Finished | Jul 20 06:55:05 PM PDT 24 |
Peak memory | 376680 kb |
Host | smart-6b43134b-ab40-4e39-afce-45cdca5226db |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715588878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 46.sram_ctrl_stress_all.2715588878 |
Directory | /workspace/46.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1084766987 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 4920840996 ps |
CPU time | 15.55 seconds |
Started | Jul 20 06:17:08 PM PDT 24 |
Finished | Jul 20 06:17:24 PM PDT 24 |
Peak memory | 214632 kb |
Host | smart-76c5ed8e-a05d-45d1-abea-91c965f0a9f6 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1084766987 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_stress_all_with_rand_reset.1084766987 |
Directory | /workspace/46.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_stress_pipeline.751360258 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 3377721172 ps |
CPU time | 219.88 seconds |
Started | Jul 20 06:17:04 PM PDT 24 |
Finished | Jul 20 06:20:44 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-b41d229a-1eab-4e96-b6bc-07fff8cd5958 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751360258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46 .sram_ctrl_stress_pipeline.751360258 |
Directory | /workspace/46.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1313645466 |
Short name | T924 |
Test name | |
Test status | |
Simulation time | 2873960438 ps |
CPU time | 11.88 seconds |
Started | Jul 20 06:17:01 PM PDT 24 |
Finished | Jul 20 06:17:14 PM PDT 24 |
Peak memory | 235620 kb |
Host | smart-0ed93a81-263b-4c5a-b335-1452b9d45c4d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313645466 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.1313645466 |
Directory | /workspace/46.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_access_during_key_req.1787237923 |
Short name | T880 |
Test name | |
Test status | |
Simulation time | 15603935450 ps |
CPU time | 940.29 seconds |
Started | Jul 20 06:17:15 PM PDT 24 |
Finished | Jul 20 06:32:56 PM PDT 24 |
Peak memory | 377324 kb |
Host | smart-bfd7cfe9-47f9-4661-bff0-1da893759f0f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787237923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 47.sram_ctrl_access_during_key_req.1787237923 |
Directory | /workspace/47.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_alert_test.3012322301 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 45310298 ps |
CPU time | 0.69 seconds |
Started | Jul 20 06:17:14 PM PDT 24 |
Finished | Jul 20 06:17:15 PM PDT 24 |
Peak memory | 202456 kb |
Host | smart-beee6e63-4f42-4766-8dec-13345d818b72 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012322301 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_alert_test.3012322301 |
Directory | /workspace/47.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_bijection.3521098351 |
Short name | T894 |
Test name | |
Test status | |
Simulation time | 288188549834 ps |
CPU time | 1701.31 seconds |
Started | Jul 20 06:17:07 PM PDT 24 |
Finished | Jul 20 06:45:29 PM PDT 24 |
Peak memory | 203468 kb |
Host | smart-145e7a26-3f79-4bd3-9afa-3efe728c6120 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521098351 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection .3521098351 |
Directory | /workspace/47.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_executable.3954529581 |
Short name | T722 |
Test name | |
Test status | |
Simulation time | 51832526210 ps |
CPU time | 1356.9 seconds |
Started | Jul 20 06:17:17 PM PDT 24 |
Finished | Jul 20 06:39:54 PM PDT 24 |
Peak memory | 373624 kb |
Host | smart-5348bdaa-db12-4341-bdc5-f4de29a33eda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954529581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab le.3954529581 |
Directory | /workspace/47.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_lc_escalation.2984513333 |
Short name | T585 |
Test name | |
Test status | |
Simulation time | 907605178 ps |
CPU time | 6.6 seconds |
Started | Jul 20 06:17:13 PM PDT 24 |
Finished | Jul 20 06:17:20 PM PDT 24 |
Peak memory | 214484 kb |
Host | smart-07bee6ac-f8a1-4548-85ea-00211e856468 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984513333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es calation.2984513333 |
Directory | /workspace/47.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_max_throughput.3061043339 |
Short name | T817 |
Test name | |
Test status | |
Simulation time | 750327176 ps |
CPU time | 38.42 seconds |
Started | Jul 20 06:17:15 PM PDT 24 |
Finished | Jul 20 06:17:55 PM PDT 24 |
Peak memory | 306604 kb |
Host | smart-b17625bd-7130-488e-bcef-740a5c07a43a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061043339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_max_throughput.3061043339 |
Directory | /workspace/47.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_partial_access.618531447 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 10925692609 ps |
CPU time | 91.63 seconds |
Started | Jul 20 06:17:13 PM PDT 24 |
Finished | Jul 20 06:18:46 PM PDT 24 |
Peak memory | 219288 kb |
Host | smart-3aed6c3f-88c9-4d15-8523-263ad8fe1101 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618531447 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47 .sram_ctrl_mem_partial_access.618531447 |
Directory | /workspace/47.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_mem_walk.1195977794 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 71849062998 ps |
CPU time | 370.58 seconds |
Started | Jul 20 06:17:14 PM PDT 24 |
Finished | Jul 20 06:23:25 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-692c8616-fcbd-4955-9cfa-a0e6cdb0ab6e |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195977794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr l_mem_walk.1195977794 |
Directory | /workspace/47.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_multiple_keys.1511735099 |
Short name | T726 |
Test name | |
Test status | |
Simulation time | 19037464163 ps |
CPU time | 1864.67 seconds |
Started | Jul 20 06:17:06 PM PDT 24 |
Finished | Jul 20 06:48:11 PM PDT 24 |
Peak memory | 380460 kb |
Host | smart-37558da4-0a55-4fdb-a507-fcae9d18c0ce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511735099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multi ple_keys.1511735099 |
Directory | /workspace/47.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access.1652290325 |
Short name | T725 |
Test name | |
Test status | |
Simulation time | 5069124484 ps |
CPU time | 55.54 seconds |
Started | Jul 20 06:17:08 PM PDT 24 |
Finished | Jul 20 06:18:05 PM PDT 24 |
Peak memory | 297976 kb |
Host | smart-3651faa9-7476-4565-bae5-bc559923ffbe |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652290325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47. sram_ctrl_partial_access.1652290325 |
Directory | /workspace/47.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.629659773 |
Short name | T597 |
Test name | |
Test status | |
Simulation time | 7440679848 ps |
CPU time | 374.29 seconds |
Started | Jul 20 06:17:14 PM PDT 24 |
Finished | Jul 20 06:23:29 PM PDT 24 |
Peak memory | 202840 kb |
Host | smart-3781e0b5-21a4-493c-9e9c-1813f2cdd769 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629659773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 47.sram_ctrl_partial_access_b2b.629659773 |
Directory | /workspace/47.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_ram_cfg.1403083980 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 348118933 ps |
CPU time | 3.13 seconds |
Started | Jul 20 06:17:15 PM PDT 24 |
Finished | Jul 20 06:17:19 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-0059a005-d876-40b8-a6d2-3ef02cc869fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403083980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.1403083980 |
Directory | /workspace/47.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_smoke.3815280657 |
Short name | T595 |
Test name | |
Test status | |
Simulation time | 2422050684 ps |
CPU time | 17.42 seconds |
Started | Jul 20 06:17:09 PM PDT 24 |
Finished | Jul 20 06:17:27 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-05a8cc2d-1d7e-4047-b811-c894aa30bf3c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815280657 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.3815280657 |
Directory | /workspace/47.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all.2928922609 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 116887540114 ps |
CPU time | 3996.96 seconds |
Started | Jul 20 06:17:13 PM PDT 24 |
Finished | Jul 20 07:23:51 PM PDT 24 |
Peak memory | 379820 kb |
Host | smart-ed3670d2-51da-4a68-9b06-72fcb3477367 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928922609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 47.sram_ctrl_stress_all.2928922609 |
Directory | /workspace/47.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1048671463 |
Short name | T730 |
Test name | |
Test status | |
Simulation time | 965881505 ps |
CPU time | 18.11 seconds |
Started | Jul 20 06:17:17 PM PDT 24 |
Finished | Jul 20 06:17:36 PM PDT 24 |
Peak memory | 211108 kb |
Host | smart-91525f0d-d68f-4acd-997c-2134dbf6e7d1 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1048671463 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_stress_all_with_rand_reset.1048671463 |
Directory | /workspace/47.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_stress_pipeline.3964974314 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 3996089655 ps |
CPU time | 275.39 seconds |
Started | Jul 20 06:17:08 PM PDT 24 |
Finished | Jul 20 06:21:44 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-837f0c72-597b-4196-a0dd-a073897b466c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964974314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 7.sram_ctrl_stress_pipeline.3964974314 |
Directory | /workspace/47.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.479211439 |
Short name | T938 |
Test name | |
Test status | |
Simulation time | 3013057008 ps |
CPU time | 71.71 seconds |
Started | Jul 20 06:17:15 PM PDT 24 |
Finished | Jul 20 06:18:28 PM PDT 24 |
Peak memory | 325536 kb |
Host | smart-82ac5a3d-5f87-40d7-b027-fce3ddc2a289 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479211439 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 47.sram_ctrl_throughput_w_partial_write.479211439 |
Directory | /workspace/47.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_access_during_key_req.4008749863 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 145719782208 ps |
CPU time | 1060.58 seconds |
Started | Jul 20 06:17:23 PM PDT 24 |
Finished | Jul 20 06:35:04 PM PDT 24 |
Peak memory | 372612 kb |
Host | smart-71dfc23a-a351-40b4-b6a6-a4c775fae3a3 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008749863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 48.sram_ctrl_access_during_key_req.4008749863 |
Directory | /workspace/48.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_alert_test.587818102 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 23160996 ps |
CPU time | 0.64 seconds |
Started | Jul 20 06:17:34 PM PDT 24 |
Finished | Jul 20 06:17:35 PM PDT 24 |
Peak memory | 202504 kb |
Host | smart-67f9b3b5-eee1-4f00-8f4e-1950302e5116 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587818102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_alert_test.587818102 |
Directory | /workspace/48.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_bijection.1398827609 |
Short name | T873 |
Test name | |
Test status | |
Simulation time | 40587342909 ps |
CPU time | 1759.63 seconds |
Started | Jul 20 06:17:16 PM PDT 24 |
Finished | Jul 20 06:46:36 PM PDT 24 |
Peak memory | 203680 kb |
Host | smart-3a352bef-ea07-4882-b1a9-532d2e2e5831 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398827609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection .1398827609 |
Directory | /workspace/48.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_executable.2717072727 |
Short name | T843 |
Test name | |
Test status | |
Simulation time | 103614202534 ps |
CPU time | 1482.12 seconds |
Started | Jul 20 06:17:23 PM PDT 24 |
Finished | Jul 20 06:42:05 PM PDT 24 |
Peak memory | 379808 kb |
Host | smart-c7601681-24d3-4208-9f53-c07d84ea0d3e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717072727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executab le.2717072727 |
Directory | /workspace/48.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_lc_escalation.768159283 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 24601086141 ps |
CPU time | 44.92 seconds |
Started | Jul 20 06:17:28 PM PDT 24 |
Finished | Jul 20 06:18:14 PM PDT 24 |
Peak memory | 202948 kb |
Host | smart-5f7b0ba3-0bad-4f54-ba6a-142c2f797077 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768159283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_esc alation.768159283 |
Directory | /workspace/48.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_max_throughput.1380347751 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 799489828 ps |
CPU time | 115.92 seconds |
Started | Jul 20 06:17:20 PM PDT 24 |
Finished | Jul 20 06:19:16 PM PDT 24 |
Peak memory | 356684 kb |
Host | smart-a49350a6-3b5f-4462-a4b2-2db96fba80d8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380347751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 48.sram_ctrl_max_throughput.1380347751 |
Directory | /workspace/48.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3747963728 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 1598819423 ps |
CPU time | 132.58 seconds |
Started | Jul 20 06:17:21 PM PDT 24 |
Finished | Jul 20 06:19:34 PM PDT 24 |
Peak memory | 211212 kb |
Host | smart-f8aa8264-b238-422c-96c6-e25465d4482f |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747963728 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_mem_partial_access.3747963728 |
Directory | /workspace/48.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_mem_walk.1481307500 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 16474001074 ps |
CPU time | 157.88 seconds |
Started | Jul 20 06:17:23 PM PDT 24 |
Finished | Jul 20 06:20:02 PM PDT 24 |
Peak memory | 211384 kb |
Host | smart-bbdc9a1b-3219-4934-931a-6647ff405f27 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481307500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr l_mem_walk.1481307500 |
Directory | /workspace/48.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_multiple_keys.2570184992 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 9334626640 ps |
CPU time | 37.16 seconds |
Started | Jul 20 06:17:14 PM PDT 24 |
Finished | Jul 20 06:17:52 PM PDT 24 |
Peak memory | 202944 kb |
Host | smart-4f045893-240e-4dc4-8ba0-7d5defc4d7f7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570184992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi ple_keys.2570184992 |
Directory | /workspace/48.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access.1288512138 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 2393846365 ps |
CPU time | 18.61 seconds |
Started | Jul 20 06:17:23 PM PDT 24 |
Finished | Jul 20 06:17:42 PM PDT 24 |
Peak memory | 202868 kb |
Host | smart-f03538f1-3869-4c69-932a-3d3e66e8d9e5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288512138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48. sram_ctrl_partial_access.1288512138 |
Directory | /workspace/48.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1565024595 |
Short name | T803 |
Test name | |
Test status | |
Simulation time | 38958395087 ps |
CPU time | 495.89 seconds |
Started | Jul 20 06:17:24 PM PDT 24 |
Finished | Jul 20 06:25:40 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-028420b3-9f48-44e3-a0e6-7aaa8a8202e8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565024595 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 48.sram_ctrl_partial_access_b2b.1565024595 |
Directory | /workspace/48.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_ram_cfg.683502407 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 1458630148 ps |
CPU time | 3.66 seconds |
Started | Jul 20 06:17:29 PM PDT 24 |
Finished | Jul 20 06:17:33 PM PDT 24 |
Peak memory | 202896 kb |
Host | smart-8c249a9c-d216-4a75-b8b7-75e27e179eb7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683502407 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.683502407 |
Directory | /workspace/48.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_regwen.640816451 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 2722662791 ps |
CPU time | 125.39 seconds |
Started | Jul 20 06:17:24 PM PDT 24 |
Finished | Jul 20 06:19:30 PM PDT 24 |
Peak memory | 336744 kb |
Host | smart-f78d67bb-09e6-42e0-8375-97b17f3b2cb1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640816451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.640816451 |
Directory | /workspace/48.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_smoke.3089213581 |
Short name | T650 |
Test name | |
Test status | |
Simulation time | 1558272227 ps |
CPU time | 14.59 seconds |
Started | Jul 20 06:17:15 PM PDT 24 |
Finished | Jul 20 06:17:31 PM PDT 24 |
Peak memory | 202856 kb |
Host | smart-195c5c1f-fb7b-44a8-be10-0f46625c1d42 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089213581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.3089213581 |
Directory | /workspace/48.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_all.25915772 |
Short name | T614 |
Test name | |
Test status | |
Simulation time | 311100505994 ps |
CPU time | 7253.99 seconds |
Started | Jul 20 06:17:35 PM PDT 24 |
Finished | Jul 20 08:18:30 PM PDT 24 |
Peak memory | 379844 kb |
Host | smart-c5e698f7-b3ed-46e6-8950-a573f82a1613 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25915772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test + UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 48.sram_ctrl_stress_all.25915772 |
Directory | /workspace/48.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1833339819 |
Short name | T708 |
Test name | |
Test status | |
Simulation time | 6559586332 ps |
CPU time | 353.1 seconds |
Started | Jul 20 06:17:28 PM PDT 24 |
Finished | Jul 20 06:23:22 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-93dcd20f-944b-4a42-a8ab-8ffd29eedb75 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833339819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.sram_ctrl_stress_pipeline.1833339819 |
Directory | /workspace/48.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1491486035 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 4895955433 ps |
CPU time | 131.26 seconds |
Started | Jul 20 06:17:23 PM PDT 24 |
Finished | Jul 20 06:19:35 PM PDT 24 |
Peak memory | 371848 kb |
Host | smart-b9b93a24-870f-4373-b7a0-1fa11ec5460f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491486035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.1491486035 |
Directory | /workspace/48.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_access_during_key_req.4157340359 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 8763234405 ps |
CPU time | 578.98 seconds |
Started | Jul 20 06:17:41 PM PDT 24 |
Finished | Jul 20 06:27:21 PM PDT 24 |
Peak memory | 369508 kb |
Host | smart-9c4efb61-5452-4c25-9ca8-f91e8a920a76 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157340359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 49.sram_ctrl_access_during_key_req.4157340359 |
Directory | /workspace/49.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_alert_test.2896214256 |
Short name | T898 |
Test name | |
Test status | |
Simulation time | 21036080 ps |
CPU time | 0.63 seconds |
Started | Jul 20 06:17:40 PM PDT 24 |
Finished | Jul 20 06:17:41 PM PDT 24 |
Peak memory | 202480 kb |
Host | smart-eadeb4a5-9977-4543-8bda-00472dc48f80 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896214256 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_alert_test.2896214256 |
Directory | /workspace/49.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_bijection.1446093813 |
Short name | T889 |
Test name | |
Test status | |
Simulation time | 190840462503 ps |
CPU time | 804.46 seconds |
Started | Jul 20 06:17:34 PM PDT 24 |
Finished | Jul 20 06:30:59 PM PDT 24 |
Peak memory | 203548 kb |
Host | smart-ebe5f62d-6cae-41c7-a882-df468dc72b4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446093813 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection .1446093813 |
Directory | /workspace/49.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_executable.886354103 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 28271490692 ps |
CPU time | 460.63 seconds |
Started | Jul 20 06:17:42 PM PDT 24 |
Finished | Jul 20 06:25:24 PM PDT 24 |
Peak memory | 366752 kb |
Host | smart-d43dd8e2-ec29-4f02-a77b-e7208e962737 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886354103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executabl e.886354103 |
Directory | /workspace/49.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_max_throughput.1211783830 |
Short name | T788 |
Test name | |
Test status | |
Simulation time | 2756956596 ps |
CPU time | 10.27 seconds |
Started | Jul 20 06:17:43 PM PDT 24 |
Finished | Jul 20 06:17:54 PM PDT 24 |
Peak memory | 235616 kb |
Host | smart-b48dcca3-fe79-4d4a-9e25-11e15ac6e369 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211783830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 49.sram_ctrl_max_throughput.1211783830 |
Directory | /workspace/49.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_partial_access.4085873610 |
Short name | T911 |
Test name | |
Test status | |
Simulation time | 5003178262 ps |
CPU time | 171.26 seconds |
Started | Jul 20 06:17:39 PM PDT 24 |
Finished | Jul 20 06:20:30 PM PDT 24 |
Peak memory | 211276 kb |
Host | smart-8c8a8f85-8043-46ac-87c3-629bff91fe62 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085873610 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 9.sram_ctrl_mem_partial_access.4085873610 |
Directory | /workspace/49.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_mem_walk.3390143528 |
Short name | T927 |
Test name | |
Test status | |
Simulation time | 28154693650 ps |
CPU time | 257.08 seconds |
Started | Jul 20 06:17:42 PM PDT 24 |
Finished | Jul 20 06:21:59 PM PDT 24 |
Peak memory | 211040 kb |
Host | smart-68b30eab-1d69-4f27-a948-4ac6d0db2e83 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390143528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr l_mem_walk.3390143528 |
Directory | /workspace/49.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_multiple_keys.9159394 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 9059111170 ps |
CPU time | 930.61 seconds |
Started | Jul 20 06:17:32 PM PDT 24 |
Finished | Jul 20 06:33:03 PM PDT 24 |
Peak memory | 358340 kb |
Host | smart-84956e21-b9fe-467c-8744-afcfba10222d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9159394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multipl e_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multiple _keys.9159394 |
Directory | /workspace/49.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access.1310728605 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 5967737718 ps |
CPU time | 16.52 seconds |
Started | Jul 20 06:17:42 PM PDT 24 |
Finished | Jul 20 06:17:59 PM PDT 24 |
Peak memory | 241484 kb |
Host | smart-32cfd6c4-0891-4431-b65d-b96d32b77b25 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310728605 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49. sram_ctrl_partial_access.1310728605 |
Directory | /workspace/49.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1816360112 |
Short name | T923 |
Test name | |
Test status | |
Simulation time | 23932275680 ps |
CPU time | 593.2 seconds |
Started | Jul 20 06:17:42 PM PDT 24 |
Finished | Jul 20 06:27:36 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-f13044b0-ed81-4aee-953c-1243b0019b95 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816360112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 49.sram_ctrl_partial_access_b2b.1816360112 |
Directory | /workspace/49.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_ram_cfg.2987568890 |
Short name | T874 |
Test name | |
Test status | |
Simulation time | 1358114705 ps |
CPU time | 3.57 seconds |
Started | Jul 20 06:17:40 PM PDT 24 |
Finished | Jul 20 06:17:44 PM PDT 24 |
Peak memory | 202940 kb |
Host | smart-0f2074e8-8b24-4498-8f81-526854a1142f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987568890 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.2987568890 |
Directory | /workspace/49.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_regwen.1738777430 |
Short name | T685 |
Test name | |
Test status | |
Simulation time | 40404147217 ps |
CPU time | 540.04 seconds |
Started | Jul 20 06:17:40 PM PDT 24 |
Finished | Jul 20 06:26:41 PM PDT 24 |
Peak memory | 376712 kb |
Host | smart-1cfa88df-4614-4b3c-8ec7-30e59449d8ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738777430 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.1738777430 |
Directory | /workspace/49.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_smoke.723144126 |
Short name | T781 |
Test name | |
Test status | |
Simulation time | 11732795396 ps |
CPU time | 13.33 seconds |
Started | Jul 20 06:17:32 PM PDT 24 |
Finished | Jul 20 06:17:46 PM PDT 24 |
Peak memory | 202884 kb |
Host | smart-b9d2a0ad-dd33-4beb-898a-a1d0dd4c2036 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723144126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.723144126 |
Directory | /workspace/49.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all.2954145736 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 214741210061 ps |
CPU time | 4293.99 seconds |
Started | Jul 20 06:17:40 PM PDT 24 |
Finished | Jul 20 07:29:15 PM PDT 24 |
Peak memory | 378756 kb |
Host | smart-e0d34929-aa9f-4e5b-af7b-2f8cc269ecce |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954145736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 49.sram_ctrl_stress_all.2954145736 |
Directory | /workspace/49.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1851292722 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 5171443090 ps |
CPU time | 67.06 seconds |
Started | Jul 20 06:17:43 PM PDT 24 |
Finished | Jul 20 06:18:51 PM PDT 24 |
Peak memory | 214668 kb |
Host | smart-5b507172-1ad6-401b-bc5b-4b6919deab9d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1851292722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_stress_all_with_rand_reset.1851292722 |
Directory | /workspace/49.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_stress_pipeline.278712801 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 41824273476 ps |
CPU time | 252.86 seconds |
Started | Jul 20 06:17:42 PM PDT 24 |
Finished | Jul 20 06:21:56 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-665c5899-2efc-4327-a757-24506f6163c0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278712801 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49 .sram_ctrl_stress_pipeline.278712801 |
Directory | /workspace/49.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2444070058 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 2205373076 ps |
CPU time | 93.48 seconds |
Started | Jul 20 06:17:42 PM PDT 24 |
Finished | Jul 20 06:19:17 PM PDT 24 |
Peak memory | 346140 kb |
Host | smart-e9294605-577c-4666-b42c-2fa8d78c5b63 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444070058 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sram_ctrl_throughput_w_partial_write.2444070058 |
Directory | /workspace/49.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1705319748 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 46615529653 ps |
CPU time | 308.5 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 06:17:54 PM PDT 24 |
Peak memory | 371944 kb |
Host | smart-fbcad100-347d-4003-b06b-1d4d43c5d3c6 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705319748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.sram_ctrl_access_during_key_req.1705319748 |
Directory | /workspace/5.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_alert_test.1277215695 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 20880261 ps |
CPU time | 0.65 seconds |
Started | Jul 20 06:12:42 PM PDT 24 |
Finished | Jul 20 06:12:44 PM PDT 24 |
Peak memory | 202520 kb |
Host | smart-e03761b1-650c-4774-a5c4-5a579a3b8a93 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277215695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_alert_test.1277215695 |
Directory | /workspace/5.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_bijection.2662105305 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 50550306554 ps |
CPU time | 840.1 seconds |
Started | Jul 20 06:12:47 PM PDT 24 |
Finished | Jul 20 06:26:49 PM PDT 24 |
Peak memory | 203604 kb |
Host | smart-1e0b9af4-e422-4208-aa65-3517bf42dbc8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662105305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection. 2662105305 |
Directory | /workspace/5.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_executable.4044549077 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 13539488359 ps |
CPU time | 188.44 seconds |
Started | Jul 20 06:12:39 PM PDT 24 |
Finished | Jul 20 06:15:48 PM PDT 24 |
Peak memory | 302032 kb |
Host | smart-09122809-54ec-4625-b68d-a5d860276389 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044549077 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl e.4044549077 |
Directory | /workspace/5.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_lc_escalation.755424836 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 3933179104 ps |
CPU time | 22.07 seconds |
Started | Jul 20 06:12:50 PM PDT 24 |
Finished | Jul 20 06:13:14 PM PDT 24 |
Peak memory | 202904 kb |
Host | smart-ec62ab14-23cc-4da4-bace-00a04f4294e7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755424836 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esca lation.755424836 |
Directory | /workspace/5.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_max_throughput.680706862 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 2895779151 ps |
CPU time | 14.59 seconds |
Started | Jul 20 06:12:45 PM PDT 24 |
Finished | Jul 20 06:13:01 PM PDT 24 |
Peak memory | 251916 kb |
Host | smart-362bf4a1-6d44-4e27-8ba3-cd4b79aa274c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680706862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.sram_ctrl_max_throughput.680706862 |
Directory | /workspace/5.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_partial_access.3881841258 |
Short name | T631 |
Test name | |
Test status | |
Simulation time | 4907202307 ps |
CPU time | 176.64 seconds |
Started | Jul 20 06:12:45 PM PDT 24 |
Finished | Jul 20 06:15:44 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-82c2ee98-6b77-4b13-84da-de0f00d8737c |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881841258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_mem_partial_access.3881841258 |
Directory | /workspace/5.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_mem_walk.3060828291 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 28263987787 ps |
CPU time | 328.98 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 06:18:14 PM PDT 24 |
Peak memory | 211932 kb |
Host | smart-db7e6153-2f7d-4d51-af1a-5be6b77d45af |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060828291 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl _mem_walk.3060828291 |
Directory | /workspace/5.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_multiple_keys.2874686750 |
Short name | T778 |
Test name | |
Test status | |
Simulation time | 35873490803 ps |
CPU time | 402.37 seconds |
Started | Jul 20 06:12:48 PM PDT 24 |
Finished | Jul 20 06:19:32 PM PDT 24 |
Peak memory | 350668 kb |
Host | smart-24044dbd-3622-4de2-be36-add8fbb32e66 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874686750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip le_keys.2874686750 |
Directory | /workspace/5.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access.1127613940 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 507483035 ps |
CPU time | 13.85 seconds |
Started | Jul 20 06:12:46 PM PDT 24 |
Finished | Jul 20 06:13:02 PM PDT 24 |
Peak memory | 202824 kb |
Host | smart-bcf9478f-100f-4c7d-b85b-0411ef329bb2 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127613940 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.s ram_ctrl_partial_access.1127613940 |
Directory | /workspace/5.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3610650891 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 24728083055 ps |
CPU time | 361.41 seconds |
Started | Jul 20 06:12:45 PM PDT 24 |
Finished | Jul 20 06:18:49 PM PDT 24 |
Peak memory | 202956 kb |
Host | smart-74293f7b-9dd2-4540-99a1-24ac945ad144 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610650891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.sram_ctrl_partial_access_b2b.3610650891 |
Directory | /workspace/5.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_ram_cfg.3025274902 |
Short name | T588 |
Test name | |
Test status | |
Simulation time | 353985662 ps |
CPU time | 3.17 seconds |
Started | Jul 20 06:12:42 PM PDT 24 |
Finished | Jul 20 06:12:46 PM PDT 24 |
Peak memory | 202880 kb |
Host | smart-9fe7dca7-f36e-4619-a80f-1d278d4fbceb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025274902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.3025274902 |
Directory | /workspace/5.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_regwen.2569855419 |
Short name | T747 |
Test name | |
Test status | |
Simulation time | 34865219436 ps |
CPU time | 1827.63 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:43:13 PM PDT 24 |
Peak memory | 379812 kb |
Host | smart-adb15a68-80ae-49e6-aa4f-22e984bc39ac |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569855419 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2569855419 |
Directory | /workspace/5.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_smoke.1280403257 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 786100047 ps |
CPU time | 55.03 seconds |
Started | Jul 20 06:12:46 PM PDT 24 |
Finished | Jul 20 06:13:43 PM PDT 24 |
Peak memory | 332732 kb |
Host | smart-f59132f3-cc7f-4da5-9bbc-d223b05176c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280403257 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.1280403257 |
Directory | /workspace/5.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all.3702282411 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 1145476581110 ps |
CPU time | 5847.99 seconds |
Started | Jul 20 06:12:46 PM PDT 24 |
Finished | Jul 20 07:50:17 PM PDT 24 |
Peak memory | 380328 kb |
Host | smart-df157f21-7012-4514-bd00-0a13b0d1e6e1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702282411 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 5.sram_ctrl_stress_all.3702282411 |
Directory | /workspace/5.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.531912359 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 1751926401 ps |
CPU time | 57.46 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:13:44 PM PDT 24 |
Peak memory | 268268 kb |
Host | smart-85c5b0be-7c19-4ec5-8894-846492ba50f4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=531912359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_stress_all_with_rand_reset.531912359 |
Directory | /workspace/5.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2597105740 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 15586232111 ps |
CPU time | 283.36 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 06:17:27 PM PDT 24 |
Peak memory | 202976 kb |
Host | smart-de3e57cc-f462-4c57-b9a9-766e02326730 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597105740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5 .sram_ctrl_stress_pipeline.2597105740 |
Directory | /workspace/5.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2839993286 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 3078966974 ps |
CPU time | 41.11 seconds |
Started | Jul 20 06:12:42 PM PDT 24 |
Finished | Jul 20 06:13:25 PM PDT 24 |
Peak memory | 302056 kb |
Host | smart-c6bca124-1b2c-44f9-8e12-1543c12e20f5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839993286 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sram_ctrl_throughput_w_partial_write.2839993286 |
Directory | /workspace/5.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_access_during_key_req.25804758 |
Short name | T703 |
Test name | |
Test status | |
Simulation time | 17989290580 ps |
CPU time | 1003.21 seconds |
Started | Jul 20 06:12:47 PM PDT 24 |
Finished | Jul 20 06:29:32 PM PDT 24 |
Peak memory | 377716 kb |
Host | smart-1605fae5-9f1f-4b32-86da-0f936e43a09d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25804758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 6.sram_ctrl_access_during_key_req.25804758 |
Directory | /workspace/6.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_alert_test.3615073877 |
Short name | T903 |
Test name | |
Test status | |
Simulation time | 33386428 ps |
CPU time | 0.65 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:12:47 PM PDT 24 |
Peak memory | 202648 kb |
Host | smart-7cc44d87-1c2b-47c2-a6b2-ac78d628a054 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615073877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_alert_test.3615073877 |
Directory | /workspace/6.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_bijection.2613387830 |
Short name | T710 |
Test name | |
Test status | |
Simulation time | 66245707908 ps |
CPU time | 2325.56 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 06:51:30 PM PDT 24 |
Peak memory | 203668 kb |
Host | smart-14ed4e5f-6f04-4ec0-a164-00b6dd2dd233 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613387830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection. 2613387830 |
Directory | /workspace/6.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_executable.3372200980 |
Short name | T647 |
Test name | |
Test status | |
Simulation time | 8601046963 ps |
CPU time | 739.38 seconds |
Started | Jul 20 06:12:41 PM PDT 24 |
Finished | Jul 20 06:25:01 PM PDT 24 |
Peak memory | 377736 kb |
Host | smart-68854c3e-8505-445a-94ce-a833b6d6896c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372200980 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl e.3372200980 |
Directory | /workspace/6.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_lc_escalation.792910681 |
Short name | T699 |
Test name | |
Test status | |
Simulation time | 11395034601 ps |
CPU time | 59.88 seconds |
Started | Jul 20 06:12:50 PM PDT 24 |
Finished | Jul 20 06:13:51 PM PDT 24 |
Peak memory | 202932 kb |
Host | smart-f134cb23-4652-44af-a2dd-cfce36e1cf6b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792910681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esca lation.792910681 |
Directory | /workspace/6.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_max_throughput.2733415970 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 735691941 ps |
CPU time | 45.67 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:13:31 PM PDT 24 |
Peak memory | 307708 kb |
Host | smart-bd426f58-af83-4483-bf20-4270945270fc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733415970 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_max_throughput.2733415970 |
Directory | /workspace/6.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_partial_access.785464524 |
Short name | T742 |
Test name | |
Test status | |
Simulation time | 7958273358 ps |
CPU time | 149.43 seconds |
Started | Jul 20 06:12:46 PM PDT 24 |
Finished | Jul 20 06:15:17 PM PDT 24 |
Peak memory | 219216 kb |
Host | smart-cb376cec-9b06-41b2-aec5-bf4fa84962be |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785464524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6. sram_ctrl_mem_partial_access.785464524 |
Directory | /workspace/6.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_mem_walk.925200004 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 7896086051 ps |
CPU time | 138.27 seconds |
Started | Jul 20 06:12:41 PM PDT 24 |
Finished | Jul 20 06:15:00 PM PDT 24 |
Peak memory | 211804 kb |
Host | smart-31c2b4f0-57da-459d-8a37-70084aa015e6 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925200004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ mem_walk.925200004 |
Directory | /workspace/6.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_multiple_keys.1020937900 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 16850236928 ps |
CPU time | 422.08 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:19:48 PM PDT 24 |
Peak memory | 338892 kb |
Host | smart-380556ae-4bc3-40f7-81c6-ada7ec2fd1b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020937900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multip le_keys.1020937900 |
Directory | /workspace/6.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access.1858008500 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 1416315752 ps |
CPU time | 24.45 seconds |
Started | Jul 20 06:12:46 PM PDT 24 |
Finished | Jul 20 06:13:12 PM PDT 24 |
Peak memory | 202832 kb |
Host | smart-79e9715e-b718-4825-9985-08f911d6f2b1 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858008500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s ram_ctrl_partial_access.1858008500 |
Directory | /workspace/6.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.342699772 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 9463999221 ps |
CPU time | 244.31 seconds |
Started | Jul 20 06:12:41 PM PDT 24 |
Finished | Jul 20 06:16:46 PM PDT 24 |
Peak memory | 202916 kb |
Host | smart-cd1f128d-31b1-4dcd-9e8e-682da1229ed8 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342699772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 6.sram_ctrl_partial_access_b2b.342699772 |
Directory | /workspace/6.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_ram_cfg.2140644053 |
Short name | T812 |
Test name | |
Test status | |
Simulation time | 676538067 ps |
CPU time | 3.33 seconds |
Started | Jul 20 06:12:47 PM PDT 24 |
Finished | Jul 20 06:12:52 PM PDT 24 |
Peak memory | 202900 kb |
Host | smart-885754c3-a512-41f5-ac98-db12c9e9770f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140644053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2140644053 |
Directory | /workspace/6.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_regwen.2937260809 |
Short name | T715 |
Test name | |
Test status | |
Simulation time | 4029381672 ps |
CPU time | 965.4 seconds |
Started | Jul 20 06:12:42 PM PDT 24 |
Finished | Jul 20 06:28:49 PM PDT 24 |
Peak memory | 378876 kb |
Host | smart-52334bde-a715-4bdf-8d36-da4e20ecf6cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937260809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.2937260809 |
Directory | /workspace/6.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_smoke.2166886299 |
Short name | T826 |
Test name | |
Test status | |
Simulation time | 1213296951 ps |
CPU time | 102.81 seconds |
Started | Jul 20 06:12:45 PM PDT 24 |
Finished | Jul 20 06:14:30 PM PDT 24 |
Peak memory | 369452 kb |
Host | smart-49e97196-c703-416a-b5ec-3913aa1897bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166886299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.2166886299 |
Directory | /workspace/6.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all.1420341612 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 42464953545 ps |
CPU time | 2507.67 seconds |
Started | Jul 20 06:12:40 PM PDT 24 |
Finished | Jul 20 06:54:28 PM PDT 24 |
Peak memory | 380984 kb |
Host | smart-ccdf392d-9087-481c-b83b-b67b8c5c0a8b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420341612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.sram_ctrl_stress_all.1420341612 |
Directory | /workspace/6.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3959057587 |
Short name | T863 |
Test name | |
Test status | |
Simulation time | 6272950180 ps |
CPU time | 44.91 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 06:13:30 PM PDT 24 |
Peak memory | 257424 kb |
Host | smart-4967326d-f3d1-4373-ad0b-7ef034ef44c7 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3959057587 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_stress_all_with_rand_reset.3959057587 |
Directory | /workspace/6.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_stress_pipeline.437763603 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 19005851077 ps |
CPU time | 307.11 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 06:17:52 PM PDT 24 |
Peak memory | 202812 kb |
Host | smart-ac5fa6de-2ea8-464a-ae8b-aaf207676e85 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437763603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6. sram_ctrl_stress_pipeline.437763603 |
Directory | /workspace/6.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.483046165 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 833773592 ps |
CPU time | 149.99 seconds |
Started | Jul 20 06:12:49 PM PDT 24 |
Finished | Jul 20 06:15:21 PM PDT 24 |
Peak memory | 370508 kb |
Host | smart-86910b9d-e07c-4394-a374-d83f4d601a65 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483046165 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.sram_ctrl_throughput_w_partial_write.483046165 |
Directory | /workspace/6.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_access_during_key_req.1463935235 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 8015588559 ps |
CPU time | 641.2 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:23:27 PM PDT 24 |
Peak memory | 378732 kb |
Host | smart-c564fc1d-f6ca-4e82-abdc-4b939b797c8d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463935235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.sram_ctrl_access_during_key_req.1463935235 |
Directory | /workspace/7.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_alert_test.2891646924 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 20499493 ps |
CPU time | 0.67 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 06:12:45 PM PDT 24 |
Peak memory | 202580 kb |
Host | smart-e3a07f8a-2caa-4ef7-9882-1c9043327f5e |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891646924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_alert_test.2891646924 |
Directory | /workspace/7.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_bijection.2156566371 |
Short name | T609 |
Test name | |
Test status | |
Simulation time | 692094621066 ps |
CPU time | 1276.21 seconds |
Started | Jul 20 06:12:40 PM PDT 24 |
Finished | Jul 20 06:33:57 PM PDT 24 |
Peak memory | 203544 kb |
Host | smart-7c9f2f0a-7bad-47f9-a579-4d5717ec1bb5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156566371 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection. 2156566371 |
Directory | /workspace/7.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_executable.3635380333 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 124790878257 ps |
CPU time | 1371.05 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:35:37 PM PDT 24 |
Peak memory | 379712 kb |
Host | smart-d4396adc-e46c-4e27-803e-559f658b5d9a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635380333 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executabl e.3635380333 |
Directory | /workspace/7.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_lc_escalation.2702377592 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 12765877435 ps |
CPU time | 76.74 seconds |
Started | Jul 20 06:12:47 PM PDT 24 |
Finished | Jul 20 06:14:05 PM PDT 24 |
Peak memory | 202936 kb |
Host | smart-8dadd83f-e66d-4a03-85d6-01df683176bc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702377592 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc alation.2702377592 |
Directory | /workspace/7.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_max_throughput.508622285 |
Short name | T711 |
Test name | |
Test status | |
Simulation time | 1588761135 ps |
CPU time | 48.45 seconds |
Started | Jul 20 06:12:41 PM PDT 24 |
Finished | Jul 20 06:13:30 PM PDT 24 |
Peak memory | 295920 kb |
Host | smart-5b108299-aedf-4468-919f-75bd9b303fd8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508622285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.sram_ctrl_max_throughput.508622285 |
Directory | /workspace/7.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1293181618 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 4220187215 ps |
CPU time | 86.47 seconds |
Started | Jul 20 06:12:40 PM PDT 24 |
Finished | Jul 20 06:14:07 PM PDT 24 |
Peak memory | 211140 kb |
Host | smart-7e5556d9-4f48-4b3e-82c2-8cb87b21bb2d |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293181618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_mem_partial_access.1293181618 |
Directory | /workspace/7.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_mem_walk.2368348635 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 79464232726 ps |
CPU time | 179.33 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 06:15:44 PM PDT 24 |
Peak memory | 211048 kb |
Host | smart-cab33c0e-e011-4c40-aeb7-c21a140f67f7 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368348635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl _mem_walk.2368348635 |
Directory | /workspace/7.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_multiple_keys.1798208993 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 15121231470 ps |
CPU time | 1133.78 seconds |
Started | Jul 20 06:12:47 PM PDT 24 |
Finished | Jul 20 06:31:42 PM PDT 24 |
Peak memory | 380848 kb |
Host | smart-446cfe81-ef4c-4d9d-9b86-423edf967406 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798208993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip le_keys.1798208993 |
Directory | /workspace/7.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access.341134541 |
Short name | T836 |
Test name | |
Test status | |
Simulation time | 3128745799 ps |
CPU time | 46.37 seconds |
Started | Jul 20 06:12:42 PM PDT 24 |
Finished | Jul 20 06:13:30 PM PDT 24 |
Peak memory | 293936 kb |
Host | smart-58d715e0-fd86-4fb7-9afb-eb296ad64746 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341134541 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sr am_ctrl_partial_access.341134541 |
Directory | /workspace/7.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1251904877 |
Short name | T772 |
Test name | |
Test status | |
Simulation time | 19053392046 ps |
CPU time | 478.29 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:20:45 PM PDT 24 |
Peak memory | 202860 kb |
Host | smart-763ee665-5f0f-4d6f-b8c8-3586be9d9bac |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251904877 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_partial_access_b2b.1251904877 |
Directory | /workspace/7.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_ram_cfg.1285743603 |
Short name | T606 |
Test name | |
Test status | |
Simulation time | 381320331 ps |
CPU time | 3.32 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:12:49 PM PDT 24 |
Peak memory | 202888 kb |
Host | smart-eca86bd8-7167-473b-9167-1a3b30d465b9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285743603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.1285743603 |
Directory | /workspace/7.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_regwen.2582710800 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 5939128882 ps |
CPU time | 370.46 seconds |
Started | Jul 20 06:12:42 PM PDT 24 |
Finished | Jul 20 06:18:54 PM PDT 24 |
Peak memory | 366444 kb |
Host | smart-90d43d0f-0135-4b13-920a-3d2bc25b0d8e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582710800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.2582710800 |
Directory | /workspace/7.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_smoke.2120286420 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 1476784844 ps |
CPU time | 40.56 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 06:13:25 PM PDT 24 |
Peak memory | 286040 kb |
Host | smart-d244ea07-ee78-444f-86fb-e53ff145e14c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120286420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.2120286420 |
Directory | /workspace/7.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all.750499902 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 1397659936816 ps |
CPU time | 4974.65 seconds |
Started | Jul 20 06:12:46 PM PDT 24 |
Finished | Jul 20 07:35:43 PM PDT 24 |
Peak memory | 380380 kb |
Host | smart-48c3b45c-3aaf-4bb9-9656-43c6e3f93bba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750499902 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 7.sram_ctrl_stress_all.750499902 |
Directory | /workspace/7.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3698022761 |
Short name | T733 |
Test name | |
Test status | |
Simulation time | 804747386 ps |
CPU time | 24.36 seconds |
Started | Jul 20 06:12:45 PM PDT 24 |
Finished | Jul 20 06:13:12 PM PDT 24 |
Peak memory | 211132 kb |
Host | smart-66b46567-4c78-4bf4-87cf-598d5ffd34f9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3698022761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_stress_all_with_rand_reset.3698022761 |
Directory | /workspace/7.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_stress_pipeline.3111256060 |
Short name | T774 |
Test name | |
Test status | |
Simulation time | 5894229066 ps |
CPU time | 93.86 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 06:14:18 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-43ccef52-6593-48f7-863c-b734d17999b7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111256060 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7 .sram_ctrl_stress_pipeline.3111256060 |
Directory | /workspace/7.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1130508900 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 821639710 ps |
CPU time | 156.56 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:15:22 PM PDT 24 |
Peak memory | 369464 kb |
Host | smart-2bf4ef0f-a259-4f47-970f-ddf4c682fc41 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130508900 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sram_ctrl_throughput_w_partial_write.1130508900 |
Directory | /workspace/7.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_access_during_key_req.1661591295 |
Short name | T913 |
Test name | |
Test status | |
Simulation time | 6759731621 ps |
CPU time | 495.21 seconds |
Started | Jul 20 06:12:47 PM PDT 24 |
Finished | Jul 20 06:21:04 PM PDT 24 |
Peak memory | 378808 kb |
Host | smart-c8dfc737-d1c8-4c2b-966b-82f731d4ac6b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661591295 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.sram_ctrl_access_during_key_req.1661591295 |
Directory | /workspace/8.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_alert_test.1233311949 |
Short name | T622 |
Test name | |
Test status | |
Simulation time | 14296755 ps |
CPU time | 0.64 seconds |
Started | Jul 20 06:12:49 PM PDT 24 |
Finished | Jul 20 06:12:51 PM PDT 24 |
Peak memory | 202652 kb |
Host | smart-0b7f0f90-2f78-49ae-b850-4cead9f0b5e5 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233311949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_alert_test.1233311949 |
Directory | /workspace/8.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_bijection.1548423106 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 468258269536 ps |
CPU time | 2394.77 seconds |
Started | Jul 20 06:12:42 PM PDT 24 |
Finished | Jul 20 06:52:39 PM PDT 24 |
Peak memory | 203480 kb |
Host | smart-5d12f0c4-aad0-4126-9c8c-6c6b0e4d4858 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548423106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection. 1548423106 |
Directory | /workspace/8.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_executable.972371494 |
Short name | T629 |
Test name | |
Test status | |
Simulation time | 32003594363 ps |
CPU time | 477.1 seconds |
Started | Jul 20 06:12:49 PM PDT 24 |
Finished | Jul 20 06:20:48 PM PDT 24 |
Peak memory | 349264 kb |
Host | smart-2e7595d9-2c41-44db-903a-7075ad04619b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972371494 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executable .972371494 |
Directory | /workspace/8.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_lc_escalation.2031563211 |
Short name | T830 |
Test name | |
Test status | |
Simulation time | 20240247701 ps |
CPU time | 32.13 seconds |
Started | Jul 20 06:12:48 PM PDT 24 |
Finished | Jul 20 06:13:22 PM PDT 24 |
Peak memory | 210180 kb |
Host | smart-f6615dae-358a-47b0-bb7f-d8403aeda031 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031563211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_lc_esc alation.2031563211 |
Directory | /workspace/8.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_max_throughput.1626007851 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 738906030 ps |
CPU time | 13 seconds |
Started | Jul 20 06:12:47 PM PDT 24 |
Finished | Jul 20 06:13:02 PM PDT 24 |
Peak memory | 241204 kb |
Host | smart-e0dab203-e322-4346-bc88-247b5e0f9b72 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626007851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 8.sram_ctrl_max_throughput.1626007851 |
Directory | /workspace/8.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3003432140 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 12353819689 ps |
CPU time | 176.84 seconds |
Started | Jul 20 06:12:50 PM PDT 24 |
Finished | Jul 20 06:15:48 PM PDT 24 |
Peak memory | 218892 kb |
Host | smart-060f903f-edc6-4458-bf7b-010fa5a2c1bd |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003432140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM _TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_mem_partial_access.3003432140 |
Directory | /workspace/8.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_mem_walk.4089574988 |
Short name | T865 |
Test name | |
Test status | |
Simulation time | 17130074398 ps |
CPU time | 256.9 seconds |
Started | Jul 20 06:12:48 PM PDT 24 |
Finished | Jul 20 06:17:07 PM PDT 24 |
Peak memory | 211072 kb |
Host | smart-a90e1982-580f-4d93-8f71-b80d32cff546 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089574988 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ= sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl _mem_walk.4089574988 |
Directory | /workspace/8.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_multiple_keys.352213757 |
Short name | T862 |
Test name | |
Test status | |
Simulation time | 16970676448 ps |
CPU time | 569.1 seconds |
Started | Jul 20 06:12:41 PM PDT 24 |
Finished | Jul 20 06:22:11 PM PDT 24 |
Peak memory | 366544 kb |
Host | smart-49281773-93ba-4abe-8a54-fc77f143ecd6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352213757 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multipl e_keys.352213757 |
Directory | /workspace/8.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access.3485364387 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 571761547 ps |
CPU time | 18.27 seconds |
Started | Jul 20 06:12:42 PM PDT 24 |
Finished | Jul 20 06:13:01 PM PDT 24 |
Peak memory | 255120 kb |
Host | smart-36f3eb35-3f11-4496-8d5d-cd42a79ed735 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485364387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s ram_ctrl_partial_access.3485364387 |
Directory | /workspace/8.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.320696217 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 8767633931 ps |
CPU time | 299.84 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:17:46 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-76af75f1-248c-4e31-b73c-db0b11c3e8b5 |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320696217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 8.sram_ctrl_partial_access_b2b.320696217 |
Directory | /workspace/8.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_ram_cfg.2238768503 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 682628087 ps |
CPU time | 3.41 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:12:50 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-d4da059d-547d-4241-9700-54938e63d679 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238768503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.2238768503 |
Directory | /workspace/8.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_regwen.463342512 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 112565759556 ps |
CPU time | 1061.36 seconds |
Started | Jul 20 06:12:48 PM PDT 24 |
Finished | Jul 20 06:30:31 PM PDT 24 |
Peak memory | 376752 kb |
Host | smart-30c46ee2-390b-47bc-b24c-7f91c06fd780 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463342512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.463342512 |
Directory | /workspace/8.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_smoke.107796686 |
Short name | T793 |
Test name | |
Test status | |
Simulation time | 412673503 ps |
CPU time | 34.55 seconds |
Started | Jul 20 06:12:46 PM PDT 24 |
Finished | Jul 20 06:13:22 PM PDT 24 |
Peak memory | 292896 kb |
Host | smart-d2aba0a2-9dd9-468a-ba4f-63aa0b155f98 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107796686 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.107796686 |
Directory | /workspace/8.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all.1172687249 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 42664665254 ps |
CPU time | 3371.32 seconds |
Started | Jul 20 06:12:48 PM PDT 24 |
Finished | Jul 20 07:09:02 PM PDT 24 |
Peak memory | 373712 kb |
Host | smart-942a8d4e-35f2-4cf1-b216-a327e2e5ef4d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172687249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.sram_ctrl_stress_all.1172687249 |
Directory | /workspace/8.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1551807207 |
Short name | T813 |
Test name | |
Test status | |
Simulation time | 3695287430 ps |
CPU time | 32.87 seconds |
Started | Jul 20 06:12:48 PM PDT 24 |
Finished | Jul 20 06:13:23 PM PDT 24 |
Peak memory | 211212 kb |
Host | smart-ee2e7e3c-e39f-4967-be28-1b1ab7f54a8a |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1551807207 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_stress_all_with_rand_reset.1551807207 |
Directory | /workspace/8.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_stress_pipeline.2876963305 |
Short name | T881 |
Test name | |
Test status | |
Simulation time | 4145393821 ps |
CPU time | 294.68 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 06:17:40 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-9d37a6f4-9d41-4e79-9076-479fdaaa84df |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876963305 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8 .sram_ctrl_stress_pipeline.2876963305 |
Directory | /workspace/8.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.1414598579 |
Short name | T782 |
Test name | |
Test status | |
Simulation time | 6979640329 ps |
CPU time | 112.68 seconds |
Started | Jul 20 06:12:46 PM PDT 24 |
Finished | Jul 20 06:14:41 PM PDT 24 |
Peak memory | 351108 kb |
Host | smart-903822df-0e38-4cd9-a673-4c79766b6727 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414598579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.1414598579 |
Directory | /workspace/8.sram_ctrl_throughput_w_partial_write/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1559456852 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 38738675889 ps |
CPU time | 848.84 seconds |
Started | Jul 20 06:12:52 PM PDT 24 |
Finished | Jul 20 06:27:03 PM PDT 24 |
Peak memory | 361368 kb |
Host | smart-ae92f0a0-aba7-4426-bf62-9cdb91f65204 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559456852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.sram_ctrl_access_during_key_req.1559456852 |
Directory | /workspace/9.sram_ctrl_access_during_key_req/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_alert_test.927489263 |
Short name | T684 |
Test name | |
Test status | |
Simulation time | 94468161 ps |
CPU time | 0.72 seconds |
Started | Jul 20 06:12:55 PM PDT 24 |
Finished | Jul 20 06:12:57 PM PDT 24 |
Peak memory | 202660 kb |
Host | smart-8f4f524f-043e-440f-b6b2-c95b3a4a1606 |
User | root |
Command | /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927489263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_alert_test.927489263 |
Directory | /workspace/9.sram_ctrl_alert_test/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_bijection.3132234078 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 138246007369 ps |
CPU time | 1717.52 seconds |
Started | Jul 20 06:12:50 PM PDT 24 |
Finished | Jul 20 06:41:29 PM PDT 24 |
Peak memory | 202724 kb |
Host | smart-6103c7dd-3da3-4523-a666-c11cd4ab0870 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132234078 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection. 3132234078 |
Directory | /workspace/9.sram_ctrl_bijection/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_executable.3918134834 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 35847947435 ps |
CPU time | 1315.58 seconds |
Started | Jul 20 06:12:41 PM PDT 24 |
Finished | Jul 20 06:34:38 PM PDT 24 |
Peak memory | 377696 kb |
Host | smart-0f228840-1ba9-41f3-a30f-53e60b0a7fc1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918134834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl e.3918134834 |
Directory | /workspace/9.sram_ctrl_executable/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_lc_escalation.2425824809 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 305023917827 ps |
CPU time | 142 seconds |
Started | Jul 20 06:12:50 PM PDT 24 |
Finished | Jul 20 06:15:14 PM PDT 24 |
Peak memory | 211128 kb |
Host | smart-43bd547c-1137-4fa4-8bcb-0cc1b41d6e2c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425824809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esc alation.2425824809 |
Directory | /workspace/9.sram_ctrl_lc_escalation/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_max_throughput.1724044708 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 898468676 ps |
CPU time | 146.23 seconds |
Started | Jul 20 06:12:50 PM PDT 24 |
Finished | Jul 20 06:15:18 PM PDT 24 |
Peak memory | 370516 kb |
Host | smart-9e13b33c-f4d5-450a-8306-2af7f5719583 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724044708 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.sram_ctrl_max_throughput.1724044708 |
Directory | /workspace/9.sram_ctrl_max_throughput/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_partial_access.295913375 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 2510046542 ps |
CPU time | 148.28 seconds |
Started | Jul 20 06:12:55 PM PDT 24 |
Finished | Jul 20 06:15:25 PM PDT 24 |
Peak memory | 211092 kb |
Host | smart-83559923-5410-443d-8910-13b781047ae3 |
User | root |
Command | /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295913375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9. sram_ctrl_mem_partial_access.295913375 |
Directory | /workspace/9.sram_ctrl_mem_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_mem_walk.404251215 |
Short name | T613 |
Test name | |
Test status | |
Simulation time | 9878139978 ps |
CPU time | 132.9 seconds |
Started | Jul 20 06:12:47 PM PDT 24 |
Finished | Jul 20 06:15:02 PM PDT 24 |
Peak memory | 211012 kb |
Host | smart-3ccaf932-285f-4b0c-afdf-aaf07837e671 |
User | root |
Command | /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404251215 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ mem_walk.404251215 |
Directory | /workspace/9.sram_ctrl_mem_walk/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_multiple_keys.1487469522 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 40273839804 ps |
CPU time | 1370.37 seconds |
Started | Jul 20 06:12:43 PM PDT 24 |
Finished | Jul 20 06:35:35 PM PDT 24 |
Peak memory | 378812 kb |
Host | smart-2e37b92d-f758-4751-9b76-6afcdeb73303 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487469522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip le_keys.1487469522 |
Directory | /workspace/9.sram_ctrl_multiple_keys/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access.2521214789 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 2302869721 ps |
CPU time | 17.6 seconds |
Started | Jul 20 06:12:51 PM PDT 24 |
Finished | Jul 20 06:13:10 PM PDT 24 |
Peak memory | 202872 kb |
Host | smart-2dd8a1b3-feba-4664-9241-f455c0e5a9de |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521214789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.s ram_ctrl_partial_access.2521214789 |
Directory | /workspace/9.sram_ctrl_partial_access/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.4086139746 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 115372723161 ps |
CPU time | 611.65 seconds |
Started | Jul 20 06:12:50 PM PDT 24 |
Finished | Jul 20 06:23:03 PM PDT 24 |
Peak memory | 202920 kb |
Host | smart-7c4b8ddd-5e10-4f44-9307-8022ddee9a8e |
User | root |
Command | /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086139746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_ TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 9.sram_ctrl_partial_access_b2b.4086139746 |
Directory | /workspace/9.sram_ctrl_partial_access_b2b/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_ram_cfg.4244406765 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 1170495706 ps |
CPU time | 3.66 seconds |
Started | Jul 20 06:12:47 PM PDT 24 |
Finished | Jul 20 06:12:52 PM PDT 24 |
Peak memory | 202908 kb |
Host | smart-27068e6b-4be9-49f2-a33b-5c2160924222 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244406765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_ cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.4244406765 |
Directory | /workspace/9.sram_ctrl_ram_cfg/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_regwen.3293914488 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 10694409855 ps |
CPU time | 869.18 seconds |
Started | Jul 20 06:12:44 PM PDT 24 |
Finished | Jul 20 06:27:16 PM PDT 24 |
Peak memory | 376760 kb |
Host | smart-5ad4cc43-278e-40a3-834a-62d4a45e43be |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293914488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.3293914488 |
Directory | /workspace/9.sram_ctrl_regwen/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_smoke.1529524095 |
Short name | T784 |
Test name | |
Test status | |
Simulation time | 427657513 ps |
CPU time | 56.39 seconds |
Started | Jul 20 06:12:48 PM PDT 24 |
Finished | Jul 20 06:13:46 PM PDT 24 |
Peak memory | 329620 kb |
Host | smart-5236fdf8-1b18-48a6-8bf3-646982dd0293 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529524095 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.1529524095 |
Directory | /workspace/9.sram_ctrl_smoke/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all.3658782065 |
Short name | T809 |
Test name | |
Test status | |
Simulation time | 732922869520 ps |
CPU time | 4669.19 seconds |
Started | Jul 20 06:12:54 PM PDT 24 |
Finished | Jul 20 07:30:45 PM PDT 24 |
Peak memory | 379204 kb |
Host | smart-a4981e4a-67c9-4c41-b2c2-f5bc357435f0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658782065 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.sram_ctrl_stress_all.3658782065 |
Directory | /workspace/9.sram_ctrl_stress_all/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1422076954 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 770345328 ps |
CPU time | 21.72 seconds |
Started | Jul 20 06:12:53 PM PDT 24 |
Finished | Jul 20 06:13:17 PM PDT 24 |
Peak memory | 212772 kb |
Host | smart-e107dd6a-ff5f-462c-8fb5-c97aa549ba3b |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1422076954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_stress_all_with_rand_reset.1422076954 |
Directory | /workspace/9.sram_ctrl_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_stress_pipeline.1739636536 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 26096201154 ps |
CPU time | 255.15 seconds |
Started | Jul 20 06:12:46 PM PDT 24 |
Finished | Jul 20 06:17:03 PM PDT 24 |
Peak memory | 202892 kb |
Host | smart-5d7be0b7-51c9-45df-80cc-e23d75880a24 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739636536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ =sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .sram_ctrl_stress_pipeline.1739636536 |
Directory | /workspace/9.sram_ctrl_stress_pipeline/latest |
Test location | /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1913343416 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 3197001984 ps |
CPU time | 7.78 seconds |
Started | Jul 20 06:12:50 PM PDT 24 |
Finished | Jul 20 06:12:59 PM PDT 24 |
Peak memory | 211148 kb |
Host | smart-698e2d22-cedd-4cc9-80e7-dd81a23e9059 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913343416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.1913343416 |
Directory | /workspace/9.sram_ctrl_throughput_w_partial_write/latest |
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