Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16417283	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

156709045

1

T1

257784

T2

164000

T3

126

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	85222931	1			T1	141653		T2	90364		T3	74
values[0x0]	42313819	1			T1	68287		T2	43242		T3	29
values[0x1]	45589578	1			T1	73666		T2	46909		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8331500	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

164794828

1

T1

270619

T2

172415

T3

126

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	539158	1			T1	1119		T2	733		T4	940
valid_sources[0x01]	535214	1			T1	1095		T2	670		T4	856
valid_sources[0x02]	551436	1			T1	1005		T2	734		T4	879
valid_sources[0x03]	539319	1			T1	1122		T2	667		T4	960
valid_sources[0x04]	605451	1			T1	1060		T2	768		T4	1047
valid_sources[0x05]	549545	1			T1	1163		T2	681		T4	853
valid_sources[0x06]	524204	1			T1	1033		T2	689		T4	906
valid_sources[0x07]	604070	1			T1	1013		T2	670		T4	914
valid_sources[0x08]	1893633	1			T1	1075		T2	759		T4	964
valid_sources[0x09]	1072993	1			T1	1117		T2	745		T4	891
valid_sources[0x0a]	569653	1			T1	1111		T2	669		T4	948
valid_sources[0x0b]	578937	1			T1	1028		T2	702		T4	869
valid_sources[0x0c]	685986	1			T1	1205		T2	716		T4	952
valid_sources[0x0d]	584309	1			T1	1015		T2	691		T4	887
valid_sources[0x0e]	529934	1			T1	1147		T2	773		T4	946
valid_sources[0x0f]	522706	1			T1	1047		T2	691		T4	952
valid_sources[0x10]	517638	1			T1	1073		T2	727		T4	939
valid_sources[0x11]	2197854	1			T1	1095		T2	732		T4	942
valid_sources[0x12]	540583	1			T1	1142		T2	725		T4	904
valid_sources[0x13]	522704	1			T1	1104		T2	773		T4	996
valid_sources[0x14]	543063	1			T1	1104		T2	745		T4	866
valid_sources[0x15]	557270	1			T1	1123		T2	698		T4	899
valid_sources[0x16]	524656	1			T1	1108		T2	730		T4	930
valid_sources[0x17]	568073	1			T1	1124		T2	736		T4	954
valid_sources[0x18]	546022	1			T1	1089		T2	670		T4	942
valid_sources[0x19]	539962	1			T1	1043		T2	669		T4	898
valid_sources[0x1a]	520654	1			T1	1081		T2	613		T4	953
valid_sources[0x1b]	581450	1			T1	1081		T2	731		T4	954
valid_sources[0x1c]	547868	1			T1	1114		T2	734		T3	63
valid_sources[0x1d]	525715	1			T1	1139		T2	677		T4	963
valid_sources[0x1e]	618888	1			T1	1214		T2	738		T4	949
valid_sources[0x1f]	541557	1			T1	1170		T2	705		T4	885
valid_sources[0x20]	555480	1			T1	1157		T2	746		T4	892
valid_sources[0x21]	515231	1			T1	1100		T2	730		T4	837
valid_sources[0x22]	525845	1			T1	1158		T2	673		T4	896
valid_sources[0x23]	541734	1			T1	1113		T2	688		T4	938
valid_sources[0x24]	851301	1			T1	1022		T2	607		T4	938
valid_sources[0x25]	526884	1			T1	1071		T2	678		T4	964
valid_sources[0x26]	537570	1			T1	1043		T2	765		T4	927
valid_sources[0x27]	525007	1			T1	1124		T2	709		T4	868
valid_sources[0x28]	531571	1			T1	1054		T2	742		T4	975
valid_sources[0x29]	2082179	1			T1	1072		T2	660		T4	943
valid_sources[0x2a]	569160	1			T1	1172		T2	687		T4	910
valid_sources[0x2b]	528096	1			T1	1169		T2	674		T4	925
valid_sources[0x2c]	531826	1			T1	1198		T2	680		T4	881
valid_sources[0x2d]	548771	1			T1	1143		T2	740		T4	954
valid_sources[0x2e]	547705	1			T1	1068		T2	719		T4	906
valid_sources[0x2f]	523625	1			T1	1169		T2	591		T4	909
valid_sources[0x30]	576038	1			T1	1161		T2	803		T4	931
valid_sources[0x31]	537937	1			T1	1066		T2	751		T4	945
valid_sources[0x32]	579726	1			T1	1147		T2	706		T4	925
valid_sources[0x33]	527019	1			T1	994		T2	701		T4	944
valid_sources[0x34]	525128	1			T1	1145		T2	667		T4	988
valid_sources[0x35]	546636	1			T1	1012		T2	687		T4	851
valid_sources[0x36]	526580	1			T1	1111		T2	695		T4	957
valid_sources[0x37]	526047	1			T1	1082		T2	685		T4	932
valid_sources[0x38]	572483	1			T1	1156		T2	716		T4	903
valid_sources[0x39]	542545	1			T1	1194		T2	729		T4	922
valid_sources[0x3a]	1763270	1			T1	1046		T2	738		T4	882
valid_sources[0x3b]	579048	1			T1	1022		T2	697		T4	874
valid_sources[0x3c]	535138	1			T1	1113		T2	750		T4	938
valid_sources[0x3d]	528539	1			T1	1082		T2	760		T4	935
valid_sources[0x3e]	629655	1			T1	1193		T2	697		T4	874
valid_sources[0x3f]	555309	1			T1	1118		T2	745		T4	906
valid_sources[0x40]	910017	1			T1	1047		T2	648		T4	903
valid_sources[0x41]	543938	1			T1	1139		T2	642		T4	913
valid_sources[0x42]	559443	1			T1	1242		T2	728		T4	962
valid_sources[0x43]	529618	1			T1	1096		T2	716		T4	918
valid_sources[0x44]	594821	1			T1	1125		T2	751		T4	876
valid_sources[0x45]	564789	1			T1	1136		T2	705		T4	934
valid_sources[0x46]	532739	1			T1	1081		T2	741		T4	976
valid_sources[0x47]	552474	1			T1	1060		T2	731		T4	884
valid_sources[0x48]	546511	1			T1	1067		T2	650		T4	899
valid_sources[0x49]	1259438	1			T1	1175		T2	700		T4	967
valid_sources[0x4a]	522466	1			T1	1058		T2	665		T4	841
valid_sources[0x4b]	561088	1			T1	1050		T2	638		T4	980
valid_sources[0x4c]	585849	1			T1	1070		T2	668		T4	899
valid_sources[0x4d]	549440	1			T1	1204		T2	744		T4	896
valid_sources[0x4e]	581632	1			T1	1129		T2	712		T4	896
valid_sources[0x4f]	546305	1			T1	1152		T2	734		T4	938
valid_sources[0x50]	540082	1			T1	1008		T2	653		T4	895
valid_sources[0x51]	653136	1			T1	1055		T2	700		T4	934
valid_sources[0x52]	1518145	1			T1	1092		T2	768		T4	898
valid_sources[0x53]	534289	1			T1	1094		T2	701		T4	911
valid_sources[0x54]	553940	1			T1	1098		T2	750		T4	905
valid_sources[0x55]	542694	1			T1	1117		T2	800		T4	912
valid_sources[0x56]	554573	1			T1	1122		T2	757		T4	908
valid_sources[0x57]	537547	1			T1	1026		T2	729		T4	886
valid_sources[0x58]	551350	1			T1	1128		T2	744		T4	952
valid_sources[0x59]	519694	1			T1	1186		T2	713		T4	963
valid_sources[0x5a]	1296437	1			T1	1116		T2	659		T4	852
valid_sources[0x5b]	576877	1			T1	1103		T2	727		T4	932
valid_sources[0x5c]	527230	1			T1	1097		T2	782		T4	973
valid_sources[0x5d]	761953	1			T1	1106		T2	727		T4	877
valid_sources[0x5e]	608703	1			T1	1181		T2	673		T4	934
valid_sources[0x5f]	540726	1			T1	1068		T2	695		T4	1005
valid_sources[0x60]	523942	1			T1	1108		T2	709		T4	835
valid_sources[0x61]	545758	1			T1	1061		T2	734		T4	927
valid_sources[0x62]	528235	1			T1	1077		T2	742		T4	931
valid_sources[0x63]	565370	1			T1	1160		T2	677		T4	914
valid_sources[0x64]	1900765	1			T1	1062		T2	687		T4	942
valid_sources[0x65]	542527	1			T1	1173		T2	574		T4	932
valid_sources[0x66]	573170	1			T1	1132		T2	749		T4	983
valid_sources[0x67]	570399	1			T1	1175		T2	663		T4	923
valid_sources[0x68]	544890	1			T1	1132		T2	635		T4	928
valid_sources[0x69]	773500	1			T1	1135		T2	731		T4	900
valid_sources[0x6a]	524110	1			T1	1078		T2	675		T4	907
valid_sources[0x6b]	545320	1			T1	1158		T2	695		T4	875
valid_sources[0x6c]	556740	1			T1	1154		T2	610		T4	907
valid_sources[0x6d]	549399	1			T1	1133		T2	686		T4	920
valid_sources[0x6e]	532023	1			T1	1128		T2	719		T4	890
valid_sources[0x6f]	605296	1			T1	1095		T2	696		T4	930
valid_sources[0x70]	516771	1			T1	1006		T2	652		T4	893
valid_sources[0x71]	533913	1			T1	1030		T2	728		T4	917
valid_sources[0x72]	530594	1			T1	1180		T2	762		T4	984
valid_sources[0x73]	1975765	1			T1	1039		T2	641		T4	908
valid_sources[0x74]	1525294	1			T1	1049		T2	711		T4	925
valid_sources[0x75]	514575	1			T1	1188		T2	688		T4	977
valid_sources[0x76]	518242	1			T1	1094		T2	600		T4	966
valid_sources[0x77]	978398	1			T1	1045		T2	707		T4	878
valid_sources[0x78]	881721	1			T1	1075		T2	654		T4	886
valid_sources[0x79]	632359	1			T1	1067		T2	765		T4	900
valid_sources[0x7a]	525860	1			T1	1145		T2	642		T4	948
valid_sources[0x7b]	554153	1			T1	1070		T2	695		T4	898
valid_sources[0x7c]	1914045	1			T1	1053		T2	761		T4	960
valid_sources[0x7d]	1743028	1			T1	1218		T2	657		T4	879
valid_sources[0x7e]	567222	1			T1	1031		T2	695		T4	883
valid_sources[0x7f]	538905	1			T1	1206		T2	744		T4	914
valid_sources[0x80]	542955	1			T1	1020		T2	713		T4	925

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

76972186

1

T1

128793

T2

82104

T3

74

values[0x0]

all_enables

biggest_size

39864972

1

T1

64373

T2

40848

T3

29

values[0x1]

all_enables

biggest_size

39871887

1

T1

64618

T2

41048

T3

23

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45188	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

152702

1

T2

13

T3

1

T4

33

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53319	1			T4	21		T6	7		T7	86
values[0x0]	69528	1			T1	2		T2	21		T3	2
values[0x1]	75043	1			T1	3		T2	19		T4	46

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34992	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

162898

1

T1

3

T2

14

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1208	1			T58	1		T151	3		T25	14
valid_sources[0x01]	817	1			T20	1		T24	93		T73	2
valid_sources[0x02]	870	1			T4	3		T151	1		T25	23
valid_sources[0x03]	560	1			T4	1		T6	1		T40	6
valid_sources[0x04]	671	1			T70	1		T20	1		T73	2
valid_sources[0x05]	783	1			T73	1		T25	14		T35	2
valid_sources[0x06]	814	1			T4	1		T6	1		T21	3
valid_sources[0x07]	801	1			T2	2		T73	2		T25	10
valid_sources[0x08]	840	1			T25	15		T152	1		T56	3
valid_sources[0x09]	698	1			T6	1		T73	1		T25	21
valid_sources[0x0a]	784	1			T6	1		T50	5		T73	3
valid_sources[0x0b]	787	1			T1	5		T4	2		T20	1
valid_sources[0x0c]	667	1			T4	3		T6	2		T73	1
valid_sources[0x0d]	790	1			T4	1		T6	1		T20	1
valid_sources[0x0e]	604	1			T6	1		T50	6		T73	1
valid_sources[0x0f]	881	1			T10	105		T25	15		T158	1
valid_sources[0x10]	769	1			T2	1		T4	1		T25	16
valid_sources[0x11]	724	1			T4	1		T6	1		T20	3
valid_sources[0x12]	710	1			T2	1		T23	1		T25	22
valid_sources[0x13]	650	1			T6	1		T50	14		T25	11
valid_sources[0x14]	708	1			T4	1		T25	22		T27	1
valid_sources[0x15]	623	1			T11	2		T25	22		T152	2
valid_sources[0x16]	647	1			T70	1		T73	1		T25	28
valid_sources[0x17]	710	1			T4	1		T6	1		T20	1
valid_sources[0x18]	694	1			T21	2		T50	6		T25	27
valid_sources[0x19]	581	1			T50	3		T25	29		T150	6
valid_sources[0x1a]	668	1			T20	1		T73	1		T25	25
valid_sources[0x1b]	715	1			T50	6		T73	1		T25	40
valid_sources[0x1c]	595	1			T25	27		T152	1		T26	9
valid_sources[0x1d]	722	1			T2	3		T6	2		T25	14
valid_sources[0x1e]	623	1			T20	2		T21	1		T25	15
valid_sources[0x1f]	733	1			T2	1		T6	1		T25	27
valid_sources[0x20]	736	1			T25	20		T152	1		T26	7
valid_sources[0x21]	608	1			T6	1		T58	2		T151	1
valid_sources[0x22]	561	1			T4	1		T73	2		T25	28
valid_sources[0x23]	827	1			T4	1		T6	1		T21	2
valid_sources[0x24]	812	1			T6	1		T25	23		T158	1
valid_sources[0x25]	1012	1			T20	2		T25	23		T152	2
valid_sources[0x26]	718	1			T50	8		T25	23		T158	1
valid_sources[0x27]	608	1			T4	1		T6	1		T20	1
valid_sources[0x28]	1032	1			T6	2		T25	24		T152	2
valid_sources[0x29]	627	1			T42	1		T21	4		T73	3
valid_sources[0x2a]	645	1			T20	1		T73	1		T25	29
valid_sources[0x2b]	600	1			T4	2		T6	1		T66	2
valid_sources[0x2c]	745	1			T22	64		T23	4		T73	1
valid_sources[0x2d]	893	1			T2	1		T4	1		T6	1
valid_sources[0x2e]	687	1			T50	4		T25	15		T56	1
valid_sources[0x2f]	662	1			T20	1		T25	27		T152	1
valid_sources[0x30]	671	1			T4	2		T70	1		T73	1
valid_sources[0x31]	711	1			T2	1		T25	29		T115	1
valid_sources[0x32]	650	1			T4	1		T6	1		T20	1
valid_sources[0x33]	860	1			T21	1		T25	21		T35	1
valid_sources[0x34]	970	1			T4	1		T21	3		T50	1
valid_sources[0x35]	645	1			T4	1		T6	1		T19	1
valid_sources[0x36]	579	1			T151	2		T25	16		T159	1
valid_sources[0x37]	655	1			T20	1		T25	14		T135	1
valid_sources[0x38]	679	1			T20	1		T25	29		T44	12
valid_sources[0x39]	762	1			T70	1		T25	33		T158	3
valid_sources[0x3a]	772	1			T70	1		T25	19		T152	1
valid_sources[0x3b]	849	1			T2	1		T25	29		T160	1
valid_sources[0x3c]	768	1			T4	2		T21	2		T73	1
valid_sources[0x3d]	603	1			T73	1		T25	18		T35	1
valid_sources[0x3e]	615	1			T70	1		T73	1		T25	20
valid_sources[0x3f]	778	1			T25	20		T35	1		T26	6
valid_sources[0x40]	959	1			T58	1		T25	23		T152	1
valid_sources[0x41]	976	1			T46	187		T24	102		T25	15
valid_sources[0x42]	835	1			T42	1		T25	27		T13	5
valid_sources[0x43]	1086	1			T4	1		T24	3		T73	1
valid_sources[0x44]	756	1			T4	1		T25	25		T152	1
valid_sources[0x45]	1470	1			T4	1		T6	1		T23	1
valid_sources[0x46]	710	1			T4	1		T58	1		T73	1
valid_sources[0x47]	883	1			T41	2		T79	1		T25	24
valid_sources[0x48]	695	1			T59	1		T73	1		T25	18
valid_sources[0x49]	1045	1			T78	1		T73	1		T43	3
valid_sources[0x4a]	641	1			T2	1		T6	2		T73	1
valid_sources[0x4b]	841	1			T42	2		T73	2		T25	25
valid_sources[0x4c]	657	1			T6	1		T19	1		T25	23
valid_sources[0x4d]	585	1			T2	2		T3	1		T25	21
valid_sources[0x4e]	698	1			T4	2		T6	1		T23	10
valid_sources[0x4f]	797	1			T25	9		T152	1		T56	1
valid_sources[0x50]	896	1			T58	1		T42	1		T50	13
valid_sources[0x51]	621	1			T4	1		T92	1		T73	2
valid_sources[0x52]	803	1			T4	1		T19	1		T58	1
valid_sources[0x53]	603	1			T50	1		T25	14		T158	2
valid_sources[0x54]	675	1			T2	2		T6	1		T24	3
valid_sources[0x55]	879	1			T20	1		T25	12		T26	14
valid_sources[0x56]	779	1			T2	1		T25	21		T26	7
valid_sources[0x57]	634	1			T6	1		T64	6		T73	1
valid_sources[0x58]	666	1			T6	1		T25	26		T161	1
valid_sources[0x59]	777	1			T151	3		T24	1		T25	21
valid_sources[0x5a]	913	1			T2	1		T4	1		T25	33
valid_sources[0x5b]	585	1			T42	2		T20	2		T73	1
valid_sources[0x5c]	797	1			T73	1		T25	28		T26	13
valid_sources[0x5d]	754	1			T2	1		T6	2		T19	1
valid_sources[0x5e]	590	1			T4	1		T151	1		T73	2
valid_sources[0x5f]	904	1			T25	28		T152	2		T118	1
valid_sources[0x60]	583	1			T6	1		T73	1		T25	16
valid_sources[0x61]	668	1			T20	1		T50	24		T73	2
valid_sources[0x62]	698	1			T6	1		T21	1		T25	17
valid_sources[0x63]	680	1			T41	2		T73	2		T25	14
valid_sources[0x64]	691	1			T42	1		T21	2		T23	6
valid_sources[0x65]	667	1			T8	20		T50	5		T25	22
valid_sources[0x66]	931	1			T6	1		T20	2		T25	18
valid_sources[0x67]	637	1			T6	1		T20	1		T25	24
valid_sources[0x68]	729	1			T6	1		T20	1		T23	6
valid_sources[0x69]	707	1			T2	1		T6	1		T20	1
valid_sources[0x6a]	699	1			T73	1		T80	11		T25	14
valid_sources[0x6b]	710	1			T2	1		T6	1		T58	2
valid_sources[0x6c]	1313	1			T6	1		T23	10		T24	3
valid_sources[0x6d]	929	1			T4	1		T42	1		T20	1
valid_sources[0x6e]	634	1			T20	1		T25	16		T162	1
valid_sources[0x6f]	670	1			T6	1		T25	19		T26	9
valid_sources[0x70]	718	1			T2	1		T4	1		T21	2
valid_sources[0x71]	795	1			T4	2		T6	1		T58	1
valid_sources[0x72]	832	1			T19	1		T83	3		T25	13
valid_sources[0x73]	907	1			T6	1		T73	1		T25	10
valid_sources[0x74]	797	1			T73	1		T25	28		T38	1
valid_sources[0x75]	799	1			T23	7		T25	20		T152	1
valid_sources[0x76]	745	1			T4	1		T73	2		T25	16
valid_sources[0x77]	803	1			T4	1		T6	1		T19	1
valid_sources[0x78]	1292	1			T73	1		T81	172		T25	26
valid_sources[0x79]	809	1			T23	1		T25	23		T152	1
valid_sources[0x7a]	717	1			T6	1		T20	1		T25	22
valid_sources[0x7b]	637	1			T4	1		T6	1		T25	20
valid_sources[0x7c]	912	1			T2	1		T73	1		T25	21
valid_sources[0x7d]	838	1			T4	1		T6	1		T25	12
valid_sources[0x7e]	803	1			T58	1		T20	1		T73	1
valid_sources[0x7f]	1262	1			T4	1		T50	7		T25	26
valid_sources[0x80]	664	1			T4	1		T25	23		T35	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40549

1

T4

10

T6

2

T7

39

values[0x0]

all_enables

biggest_size

57445

1

T2

9

T3

1

T4

16

values[0x1]

all_enables

biggest_size

54708

1

T2

4

T4

7

T10

10