Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16311341

1

T1

25822

T2

14422

T4

17769

full_word

153483001

1

T1

257784

T2

143779

T3

126

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	169794082	1			T1	283606		T2	158201		T3	126
auto[TlIntgErrCmd]	86	1			T67	1		T68	6		T69	4
auto[TlIntgErrData]	78	1			T67	6		T68	3		T69	4
auto[TlIntgErrBoth]	96	1			T67	3		T68	11		T69	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81795430

1

T1

141653

T2

68050

T3

74

auto[1]

87998912

1

T1

141953

T2

90151

T3

52

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7978764	1			T1	12860		T2	6167		T4	6961
auto[TlIntgErrNone]	partial	auto[1]	8332341	1			T1	12962		T2	8255		T4	10808
auto[TlIntgErrNone]	full_word	auto[0]	73816551	1			T1	128793		T2	61883		T3	74
auto[TlIntgErrNone]	full_word	auto[1]	79666426	1			T1	128991		T2	81896		T3	52
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T68	2		T69	2		T137	2
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T67	1		T68	4		T69	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T147	1		T143	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T137	1		T145	1		T143	1
auto[TlIntgErrData]	partial	auto[0]	40	1			T68	1		T69	2		T137	2
auto[TlIntgErrData]	partial	auto[1]	34	1			T67	6		T68	2		T69	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T137	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T144	1		T148	1		T149	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T67	1		T68	2		T69	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T67	2		T68	7		T137	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T69	1		T145	1		T146	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T68	2		T137	2		T139	1