Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1125585	1			T2	4445		T4	1275		T11	106
auto[1]	10728970	1			T1	117993		T2	700		T3	72
auto[2]	876551	1			T2	2634		T4	1153		T11	44
auto[3]	10411289	1			T1	118264		T2	318		T3	51

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15031318	1			T1	196824		T2	6488		T3	123
auto[1]	2139344	1			T1	18894		T2	798		T4	331
auto[2]	2167919	1			T1	18652		T2	722		T4	271
auto[3]	3803814	1			T1	1887		T2	89		T4	34

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9888184

1

T2

8097

T3

123

T4

2906

auto[1]

13254211

1

T1

236257

T41

3

T7

6

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	458799	1			T2	3672		T4	1053		T11	91
auto[0]	auto[0]	auto[1]	47318	1			T2	346		T4	94		T11	5
auto[0]	auto[0]	auto[2]	47616	1			T2	392		T4	117		T11	10
auto[0]	auto[0]	auto[3]	69987	1			T2	35		T4	11		T6	1
auto[0]	auto[1]	auto[0]	3501468	1			T2	404		T3	72		T4	167
auto[0]	auto[1]	auto[1]	370940	1			T2	235		T4	121		T5	386
auto[0]	auto[1]	auto[2]	368330	1			T2	38		T4	17		T5	342
auto[0]	auto[1]	auto[3]	267116	1			T2	23		T4	10		T5	1637
auto[0]	auto[2]	auto[0]	342805	1			T2	2241		T4	965		T40	636
auto[0]	auto[2]	auto[1]	39517	1			T2	204		T4	106		T40	58
auto[0]	auto[2]	auto[2]	36481	1			T2	175		T4	75		T11	41
auto[0]	auto[2]	auto[3]	50927	1			T2	14		T4	7		T11	3
auto[0]	auto[3]	auto[0]	3332862	1			T2	171		T3	51		T4	85
auto[0]	auto[3]	auto[1]	347975	1			T2	13		T4	10		T5	369
auto[0]	auto[3]	auto[2]	369065	1			T2	117		T4	62		T5	336
auto[0]	auto[3]	auto[3]	236978	1			T2	17		T4	6		T5	1599
auto[1]	auto[0]	auto[0]	16546	1			T64	157		T115	112		T153	107
auto[1]	auto[0]	auto[1]	74573	1			T64	653		T115	581		T153	489
auto[1]	auto[0]	auto[2]	74552	1			T64	702		T115	568		T153	466
auto[1]	auto[0]	auto[3]	336194	1			T64	2873		T115	2652		T153	2122
auto[1]	auto[1]	auto[0]	3686776	1			T1	98235		T41	2		T7	3
auto[1]	auto[1]	auto[1]	628418	1			T1	9029		T58	1		T64	2234
auto[1]	auto[1]	auto[2]	594049	1			T1	9767		T64	1107		T65	7065
auto[1]	auto[1]	auto[3]	1311873	1			T1	962		T64	9931		T65	596
auto[1]	auto[2]	auto[0]	12276	1			T154	668		T155	528		T156	1
auto[1]	auto[2]	auto[1]	55929	1			T154	3143		T155	2499		T157	2812
auto[1]	auto[2]	auto[2]	61641	1			T64	606		T22	1		T115	522
auto[1]	auto[2]	auto[3]	276975	1			T64	2546		T115	2533		T153	1934
auto[1]	auto[3]	auto[0]	3679786	1			T1	98589		T41	1		T7	1
auto[1]	auto[3]	auto[1]	574674	1			T1	9865		T7	1		T64	529
auto[1]	auto[3]	auto[2]	616185	1			T1	8885		T7	1		T64	2144
auto[1]	auto[3]	auto[3]	1253764	1			T1	925		T64	9662		T65	619