Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1195167339	229596	0	0
ctrl_regwen_rd_A	1195167339	4881	0	0
exec_rd_A	1195167339	4465	0	0
exec_regwen_rd_A	1195167339	4551	0	0
readback_rd_A	1195167339	3656	0	0
readback_regwen_rd_A	1195167339	3149	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195167339	229596	0	0
T24	23886	1712	0	0
T25	0	8656	0	0
T26	0	2568	0	0
T43	100416	0	0	0
T50	103586	0	0	0
T60	0	5816	0	0
T61	0	5498	0	0
T62	0	9680	0	0
T73	209989	0	0	0
T74	0	1421	0	0
T75	0	3603	0	0
T76	0	2858	0	0
T77	0	4374	0	0
T78	67280	0	0	0
T79	177623	0	0	0
T80	507580	0	0	0
T81	815945	0	0	0
T82	300429	0	0	0
T83	760588	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195167339	4881	0	0
T48	0	156	0	0
T74	29086	75	0	0
T75	0	140	0	0
T76	0	255	0	0
T98	845594	0	0	0
T121	0	98	0	0
T122	0	600	0	0
T123	0	70	0	0
T124	0	463	0	0
T125	0	125	0	0
T126	0	270	0	0
T127	331200	0	0	0
T128	71657	0	0	0
T129	70056	0	0	0
T130	443925	0	0	0
T131	77627	0	0	0
T132	81828	0	0	0
T133	173765	0	0	0
T134	78091	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195167339	4465	0	0
T48	0	197	0	0
T74	29086	92	0	0
T75	0	111	0	0
T76	0	180	0	0
T98	845594	0	0	0
T121	0	69	0	0
T122	0	629	0	0
T123	0	120	0	0
T124	0	383	0	0
T125	0	134	0	0
T126	0	149	0	0
T127	331200	0	0	0
T128	71657	0	0	0
T129	70056	0	0	0
T130	443925	0	0	0
T131	77627	0	0	0
T132	81828	0	0	0
T133	173765	0	0	0
T134	78091	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195167339	4551	0	0
T48	0	147	0	0
T74	29086	56	0	0
T75	0	154	0	0
T76	0	206	0	0
T98	845594	0	0	0
T121	0	88	0	0
T122	0	605	0	0
T123	0	113	0	0
T124	0	349	0	0
T125	0	163	0	0
T126	0	172	0	0
T127	331200	0	0	0
T128	71657	0	0	0
T129	70056	0	0	0
T130	443925	0	0	0
T131	77627	0	0	0
T132	81828	0	0	0
T133	173765	0	0	0
T134	78091	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195167339	3656	0	0
T48	0	254	0	0
T74	29086	119	0	0
T75	0	81	0	0
T76	0	139	0	0
T98	845594	0	0	0
T121	0	52	0	0
T122	0	611	0	0
T123	0	83	0	0
T124	0	453	0	0
T125	0	137	0	0
T126	0	216	0	0
T127	331200	0	0	0
T128	71657	0	0	0
T129	70056	0	0	0
T130	443925	0	0	0
T131	77627	0	0	0
T132	81828	0	0	0
T133	173765	0	0	0
T134	78091	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195167339	3149	0	0
T48	0	138	0	0
T74	29086	86	0	0
T75	0	144	0	0
T76	0	180	0	0
T98	845594	0	0	0
T121	0	30	0	0
T122	0	571	0	0
T123	0	77	0	0
T124	0	391	0	0
T125	0	116	0	0
T126	0	205	0	0
T127	331200	0	0	0
T128	71657	0	0	0
T129	70056	0	0	0
T130	443925	0	0	0
T131	77627	0	0	0
T132	81828	0	0	0
T133	173765	0	0	0
T134	78091	0	0	0