Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16451278

1

T1

128

T2

11095

T3

10774

full_word

151117269

1

T1

1289

T2

110375

T3

357927

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	167568287	1			T1	1417		T2	121470		T3	359005
auto[TlIntgErrCmd]	85	1			T66	2		T67	8		T68	4
auto[TlIntgErrData]	93	1			T66	6		T67	7		T68	3
auto[TlIntgErrBoth]	82	1			T66	2		T67	5		T68	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80676257

1

T1

736

T2

60520

T3

178535

auto[1]

86892290

1

T1

681

T2

60950

T3

180469

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8054612	1			T1	55		T2	5575		T3	4494
auto[TlIntgErrNone]	partial	auto[1]	8396426	1			T1	73		T2	5520		T3	6280
auto[TlIntgErrNone]	full_word	auto[0]	72621528	1			T1	681		T2	54945		T3	178086
auto[TlIntgErrNone]	full_word	auto[1]	78495721	1			T1	608		T2	55430		T3	179841
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T67	2		T68	2		T134	5
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T66	1		T67	6		T68	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T66	1		T135	1		T136	1
auto[TlIntgErrData]	partial	auto[0]	46	1			T66	5		T67	4		T68	1
auto[TlIntgErrData]	partial	auto[1]	41	1			T67	3		T68	2		T134	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T66	1		T137	1		T138	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T138	1		T139	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T66	1		T67	2		T68	1
auto[TlIntgErrBoth]	partial	auto[1]	38	1			T66	1		T67	3		T68	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T134	1		T140	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T139	1		T135	2		T141	1