Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	883539	1			T1	227		T2	196		T3	16
auto[1]	10402953	1			T1	51		T2	1582		T3	200
auto[2]	667376	1			T1	158		T2	107		T3	21
auto[3]	10108047	1			T1	35		T2	1453		T3	177

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13831329	1			T1	356		T2	2372		T3	304
auto[1]	2106408	1			T1	54		T2	374		T3	44
auto[2]	2126215	1			T1	52		T2	545		T3	54
auto[3]	3997963	1			T1	9		T2	47		T3	12

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8503977

1

T1

471

T2

3338

T3

414

auto[1]

13557938

1

T8

4

T41

143834

T42

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	313150	1			T1	192		T2	162		T3	11
auto[0]	auto[0]	auto[1]	32189	1			T1	17		T2	18		T76	36
auto[0]	auto[0]	auto[2]	32121	1			T1	15		T2	14		T3	4
auto[0]	auto[0]	auto[3]	40180	1			T1	3		T2	2		T3	1
auto[0]	auto[1]	auto[0]	3177284	1			T1	26		T2	1187		T3	152
auto[0]	auto[1]	auto[1]	329071	1			T1	22		T2	254		T3	35
auto[0]	auto[1]	auto[2]	324689	1			T1	2		T2	124		T3	11
auto[0]	auto[1]	auto[3]	164385	1			T1	1		T2	17		T3	2
auto[0]	auto[2]	auto[0]	218519	1			T1	127		T3	1		T9	1
auto[0]	auto[2]	auto[1]	24159	1			T1	14		T5	1		T21	119
auto[0]	auto[2]	auto[2]	27496	1			T1	13		T2	98		T3	15
auto[0]	auto[2]	auto[3]	28494	1			T1	4		T2	9		T3	5
auto[0]	auto[3]	auto[0]	3013009	1			T1	11		T2	1023		T3	140
auto[0]	auto[3]	auto[1]	306698	1			T1	1		T2	102		T3	9
auto[0]	auto[3]	auto[2]	324461	1			T1	22		T2	309		T3	24
auto[0]	auto[3]	auto[3]	148072	1			T1	1		T2	19		T3	4
auto[1]	auto[0]	auto[0]	15267	1			T65	1377		T112	156		T149	229
auto[1]	auto[0]	auto[1]	69537	1			T65	6332		T112	768		T150	1
auto[1]	auto[0]	auto[2]	69459	1			T65	6256		T112	765		T148	1
auto[1]	auto[0]	auto[3]	311636	1			T65	28006		T112	3308		T149	5322
auto[1]	auto[1]	auto[0]	3541455	1			T8	2		T41	2315		T65	226
auto[1]	auto[1]	auto[1]	674949	1			T41	10722		T65	6173		T111	8694
auto[1]	auto[1]	auto[2]	631758	1			T41	10780		T65	962		T111	9826
auto[1]	auto[1]	auto[3]	1559362	1			T41	47849		T65	28086		T111	905
auto[1]	auto[2]	auto[0]	11986	1			T65	1237		T147	1		T149	183
auto[1]	auto[2]	auto[1]	53287	1			T65	5694		T149	680		T151	3015
auto[1]	auto[2]	auto[2]	55343	1			T65	5344		T112	699		T149	1094
auto[1]	auto[2]	auto[3]	248092	1			T65	23397		T112	3043		T149	5031
auto[1]	auto[3]	auto[0]	3540659	1			T8	2		T41	2354		T65	99
auto[1]	auto[3]	auto[1]	616518	1			T41	10883		T65	487		T111	9759
auto[1]	auto[3]	auto[2]	660888	1			T41	10955		T42	1		T65	5371
auto[1]	auto[3]	auto[3]	1497742	1			T41	47976		T65	23777		T111	909