Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1141036372	214155	0	0
ctrl_regwen_rd_A	1141036372	5788	0	0
exec_rd_A	1141036372	5166	0	0
exec_regwen_rd_A	1141036372	5604	0	0
readback_rd_A	1141036372	3392	0	0
readback_regwen_rd_A	1141036372	3039	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1141036372	214155	0	0
T4	501087	0	0	0
T5	107289	0	0	0
T9	164647	5912	0	0
T10	2642	0	0	0
T11	68598	0	0	0
T23	0	2735	0	0
T24	0	4773	0	0
T40	77618	0	0	0
T41	459815	0	0	0
T42	827955	0	0	0
T50	0	3772	0	0
T57	0	4917	0	0
T71	0	1308	0	0
T72	0	2263	0	0
T73	0	1666	0	0
T74	0	2082	0	0
T75	0	2999	0	0
T76	87321	0	0	0
T77	75211	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1141036372	5788	0	0
T47	0	379	0	0
T52	502992	0	0	0
T117	34317	177	0	0
T118	0	184	0	0
T119	0	231	0	0
T120	0	71	0	0
T121	0	106	0	0
T122	0	69	0	0
T123	0	324	0	0
T124	0	96	0	0
T125	0	156	0	0
T126	240561	0	0	0
T127	97730	0	0	0
T128	599948	0	0	0
T129	93320	0	0	0
T130	143295	0	0	0
T131	455822	0	0	0
T132	104377	0	0	0
T133	43372	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1141036372	5166	0	0
T47	0	308	0	0
T52	502992	0	0	0
T117	34317	109	0	0
T118	0	193	0	0
T119	0	316	0	0
T120	0	60	0	0
T121	0	103	0	0
T122	0	34	0	0
T123	0	304	0	0
T124	0	84	0	0
T125	0	117	0	0
T126	240561	0	0	0
T127	97730	0	0	0
T128	599948	0	0	0
T129	93320	0	0	0
T130	143295	0	0	0
T131	455822	0	0	0
T132	104377	0	0	0
T133	43372	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1141036372	5604	0	0
T47	0	345	0	0
T52	502992	0	0	0
T117	34317	140	0	0
T118	0	116	0	0
T119	0	275	0	0
T120	0	41	0	0
T121	0	136	0	0
T122	0	67	0	0
T123	0	328	0	0
T124	0	109	0	0
T125	0	98	0	0
T126	240561	0	0	0
T127	97730	0	0	0
T128	599948	0	0	0
T129	93320	0	0	0
T130	143295	0	0	0
T131	455822	0	0	0
T132	104377	0	0	0
T133	43372	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1141036372	3392	0	0
T47	0	388	0	0
T52	502992	0	0	0
T117	34317	140	0	0
T118	0	143	0	0
T119	0	293	0	0
T120	0	76	0	0
T121	0	108	0	0
T122	0	52	0	0
T123	0	361	0	0
T124	0	44	0	0
T125	0	116	0	0
T126	240561	0	0	0
T127	97730	0	0	0
T128	599948	0	0	0
T129	93320	0	0	0
T130	143295	0	0	0
T131	455822	0	0	0
T132	104377	0	0	0
T133	43372	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1141036372	3039	0	0
T47	0	250	0	0
T52	502992	0	0	0
T117	34317	121	0	0
T118	0	173	0	0
T119	0	165	0	0
T120	0	56	0	0
T121	0	119	0	0
T122	0	44	0	0
T123	0	320	0	0
T124	0	59	0	0
T125	0	131	0	0
T126	240561	0	0	0
T127	97730	0	0	0
T128	599948	0	0	0
T129	93320	0	0	0
T130	143295	0	0	0
T131	455822	0	0	0
T132	104377	0	0	0
T133	43372	0	0	0