SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 9 | 0 | 9 | 100.00 |
Crosses | 16 | 0 | 16 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
csr_exec_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
en_sram_ifetch_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 | |
lc_hw_debug_en_cp | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
executable_cross | 16 | 0 | 16 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
instr_invalid_dis | 353075228 | 1 | T1 | 88128 | T3 | 563894 | T4 | 7638 | ||||
instr_valid_dis | 315300652 | 1 | T1 | 69256 | T3 | 563894 | T4 | 7638 | ||||
instr_en | 27297910 | 1 | T1 | 18872 | T18 | 398292 | T19 | 256486 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
sram_ifetch_invalid_disable | 13705119 | 1 | T1 | 47574 | T18 | 109498 | T19 | 68368 | ||||
sram_ifetch_valid_disable | 317563701 | 1 | T1 | 40554 | T3 | 563894 | T4 | 7638 | ||||
sram_ifetch_enable | 21806408 | 1 | T18 | 168756 | T19 | 113790 | T43 | 137564 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
hw_debug_en_invalid_off | 353075228 | 1 | T1 | 88128 | T3 | 563894 | T4 | 7638 | ||||
hw_debug_en_valid_off | 314666526 | 1 | T3 | 563894 | T4 | 7638 | T10 | 4396 | ||||
hw_debug_en_on | 25582846 | 1 | T1 | 21682 | T18 | 63974 | T19 | 86750 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 16 | 0 | 16 | 100.00 | |
Automatically Generated Cross Bins | 12 | 0 | 12 | 100.00 | |
User Defined Cross Bins | 4 | 0 | 4 | 100.00 |
lc_hw_debug_en_cp | en_sram_ifetch_cp | csr_exec_cp | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_invalid_dis | 317563701 | 1 | T1 | 40554 | T3 | 563894 | T4 | 7638 | ||||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_valid_dis | 302521642 | 1 | T1 | 21682 | T3 | 563894 | T4 | 7638 | ||||
hw_debug_en_invalid_off | sram_ifetch_valid_disable | instr_en | 10924013 | 1 | T1 | 18872 | T18 | 123914 | T19 | 74328 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_invalid_dis | 7614513 | 1 | T18 | 15786 | T19 | 35616 | T70 | 43226 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_valid_dis | 1467816 | 1 | T70 | 43226 | T79 | 5034 | T126 | 7854 | ||||
hw_debug_en_valid_off | sram_ifetch_invalid_disable | instr_en | 5374293 | 1 | T18 | 15786 | T19 | 35616 | T55 | 37359 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_invalid_dis | 4012844 | 1 | T18 | 3876 | T19 | 32752 | T43 | 18780 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_valid_dis | 1749820 | 1 | T18 | 3876 | T126 | 13836 | T128 | 11876 | ||||
hw_debug_en_on | sram_ifetch_invalid_disable | instr_en | 1745314 | 1 | T19 | 32752 | T43 | 18780 | T133 | 46996 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_invalid_dis | 13491502 | 1 | T1 | 21682 | T18 | 54084 | T19 | 43464 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_valid_dis | 5874740 | 1 | T1 | 21682 | T70 | 57338 | T79 | 31518 | ||||
hw_debug_en_on | sram_ifetch_valid_disable | instr_en | 6018016 | 1 | T18 | 54084 | T19 | 43464 | T43 | 21846 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
csr_exec_en | 8517770 | 1 | T18 | 168756 | T19 | 113790 | T43 | 137500 | ||||
lc_exec_en | 8078500 | 1 | T18 | 6014 | T19 | 10534 | T43 | 39538 | ||||
valid_exec_dis | 305998275 | 1 | T3 | 563894 | T4 | 7638 | T10 | 4396 | ||||
invalid_exec_dis | 35511527 | 1 | T1 | 47574 | T18 | 278254 | T19 | 182158 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |