Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	148601927	1			T1	18063		T3	51446		T4	3465
triple_byte_access	2732063	1			T1	343		T3	45984		T4	91
halfword_access	4193541	1			T1	510		T3	69388		T4	111
byte_access	5868782	1			T1	691		T3	92017		T4	129
zero_access	1782487	1			T1	165		T3	23112		T4	23

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81330042

1

T1

10988

T3

141081

T4

1882

auto[1]

81848758

1

T1

8784

T3

140866

T4

1937

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	73904454	1			T1	10060		T3	25766		T4	1707
auto[0]	triple_byte_access	1301260	1			T1	183		T3	22763		T4	44
auto[0]	halfword_access	2047721	1			T1	285		T3	34765		T4	52
auto[0]	byte_access	3009948	1			T1	366		T3	46215		T4	63
auto[0]	zero_access	1066659	1			T1	94		T3	11572		T4	16
auto[1]	word_access	74697473	1			T1	8003		T3	25680		T4	1758
auto[1]	triple_byte_access	1430803	1			T1	160		T3	23221		T4	47
auto[1]	halfword_access	2145820	1			T1	225		T3	34623		T4	59
auto[1]	byte_access	2858834	1			T1	325		T3	45802		T4	66
auto[1]	zero_access	715828	1			T1	71		T3	11540		T4	7