| T791 |
/workspace/coverage/default/19.sram_ctrl_smoke.2593714442 |
|
|
Jul 24 07:20:48 PM PDT 24 |
Jul 24 07:20:59 PM PDT 24 |
474217585 ps |
| T792 |
/workspace/coverage/default/40.sram_ctrl_executable.1150582262 |
|
|
Jul 24 07:30:40 PM PDT 24 |
Jul 24 07:31:03 PM PDT 24 |
5300460552 ps |
| T793 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.3159230295 |
|
|
Jul 24 07:24:11 PM PDT 24 |
Jul 24 07:29:23 PM PDT 24 |
28806415675 ps |
| T794 |
/workspace/coverage/default/18.sram_ctrl_bijection.3017130586 |
|
|
Jul 24 07:20:43 PM PDT 24 |
Jul 24 07:59:09 PM PDT 24 |
547090510230 ps |
| T795 |
/workspace/coverage/default/23.sram_ctrl_access_during_key_req.1133631271 |
|
|
Jul 24 07:21:44 PM PDT 24 |
Jul 24 07:30:46 PM PDT 24 |
26659937639 ps |
| T796 |
/workspace/coverage/default/39.sram_ctrl_smoke.2916646332 |
|
|
Jul 24 07:30:18 PM PDT 24 |
Jul 24 07:30:29 PM PDT 24 |
710755126 ps |
| T797 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3955387944 |
|
|
Jul 24 07:20:16 PM PDT 24 |
Jul 24 07:22:00 PM PDT 24 |
3060155229 ps |
| T798 |
/workspace/coverage/default/21.sram_ctrl_bijection.3587957474 |
|
|
Jul 24 07:21:17 PM PDT 24 |
Jul 24 07:42:33 PM PDT 24 |
57667789003 ps |
| T111 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3721404430 |
|
|
Jul 24 07:18:04 PM PDT 24 |
Jul 24 07:18:28 PM PDT 24 |
3388429791 ps |
| T799 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.715255178 |
|
|
Jul 24 07:18:34 PM PDT 24 |
Jul 24 07:22:33 PM PDT 24 |
3328034282 ps |
| T800 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.51609398 |
|
|
Jul 24 07:19:39 PM PDT 24 |
Jul 24 07:19:43 PM PDT 24 |
360576319 ps |
| T801 |
/workspace/coverage/default/6.sram_ctrl_regwen.3765746575 |
|
|
Jul 24 07:18:37 PM PDT 24 |
Jul 24 07:21:20 PM PDT 24 |
2985210221 ps |
| T802 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.457196418 |
|
|
Jul 24 07:24:29 PM PDT 24 |
Jul 24 07:26:53 PM PDT 24 |
2502139219 ps |
| T803 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.979795189 |
|
|
Jul 24 07:24:21 PM PDT 24 |
Jul 24 07:24:24 PM PDT 24 |
4808090975 ps |
| T804 |
/workspace/coverage/default/15.sram_ctrl_executable.1490636886 |
|
|
Jul 24 07:20:10 PM PDT 24 |
Jul 24 07:39:51 PM PDT 24 |
12661352103 ps |
| T805 |
/workspace/coverage/default/18.sram_ctrl_executable.3585015889 |
|
|
Jul 24 07:20:42 PM PDT 24 |
Jul 24 07:32:21 PM PDT 24 |
12885147468 ps |
| T806 |
/workspace/coverage/default/45.sram_ctrl_bijection.357716626 |
|
|
Jul 24 07:31:18 PM PDT 24 |
Jul 24 07:59:29 PM PDT 24 |
108810562088 ps |
| T807 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.578838889 |
|
|
Jul 24 07:23:21 PM PDT 24 |
Jul 24 07:25:42 PM PDT 24 |
175849995929 ps |
| T808 |
/workspace/coverage/default/45.sram_ctrl_executable.1383236020 |
|
|
Jul 24 07:31:19 PM PDT 24 |
Jul 24 07:37:19 PM PDT 24 |
22781246197 ps |
| T809 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.2663035628 |
|
|
Jul 24 07:24:22 PM PDT 24 |
Jul 24 07:28:17 PM PDT 24 |
7108025880 ps |
| T810 |
/workspace/coverage/default/31.sram_ctrl_bijection.1470914537 |
|
|
Jul 24 07:23:22 PM PDT 24 |
Jul 24 07:42:21 PM PDT 24 |
295102423896 ps |
| T811 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2084214475 |
|
|
Jul 24 07:18:50 PM PDT 24 |
Jul 24 07:24:23 PM PDT 24 |
24417881487 ps |
| T812 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.4165694878 |
|
|
Jul 24 07:24:01 PM PDT 24 |
Jul 24 07:28:04 PM PDT 24 |
4551668328 ps |
| T813 |
/workspace/coverage/default/19.sram_ctrl_regwen.2696704438 |
|
|
Jul 24 07:20:58 PM PDT 24 |
Jul 24 07:21:29 PM PDT 24 |
1653274027 ps |
| T814 |
/workspace/coverage/default/29.sram_ctrl_lc_escalation.3627039562 |
|
|
Jul 24 07:23:03 PM PDT 24 |
Jul 24 07:23:22 PM PDT 24 |
3403997158 ps |
| T815 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.448271885 |
|
|
Jul 24 07:23:04 PM PDT 24 |
Jul 24 07:24:24 PM PDT 24 |
9801072760 ps |
| T816 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.1106142468 |
|
|
Jul 24 07:24:30 PM PDT 24 |
Jul 24 07:30:52 PM PDT 24 |
74310496153 ps |
| T817 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.67606424 |
|
|
Jul 24 07:30:39 PM PDT 24 |
Jul 24 07:36:35 PM PDT 24 |
22284196458 ps |
| T818 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3959015113 |
|
|
Jul 24 07:31:12 PM PDT 24 |
Jul 24 07:34:02 PM PDT 24 |
5788633302 ps |
| T819 |
/workspace/coverage/default/7.sram_ctrl_partial_access.164884062 |
|
|
Jul 24 07:18:41 PM PDT 24 |
Jul 24 07:18:57 PM PDT 24 |
596137672 ps |
| T820 |
/workspace/coverage/default/7.sram_ctrl_bijection.2774530367 |
|
|
Jul 24 07:18:50 PM PDT 24 |
Jul 24 07:33:16 PM PDT 24 |
148209744567 ps |
| T821 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.2662981862 |
|
|
Jul 24 07:23:12 PM PDT 24 |
Jul 24 07:24:45 PM PDT 24 |
785921154 ps |
| T822 |
/workspace/coverage/default/8.sram_ctrl_executable.1488674119 |
|
|
Jul 24 07:18:49 PM PDT 24 |
Jul 24 07:31:41 PM PDT 24 |
40308830288 ps |
| T823 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1461412786 |
|
|
Jul 24 07:18:57 PM PDT 24 |
Jul 24 07:18:58 PM PDT 24 |
58901295 ps |
| T824 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.713605184 |
|
|
Jul 24 07:17:59 PM PDT 24 |
Jul 24 07:20:04 PM PDT 24 |
11125017134 ps |
| T825 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.3444973578 |
|
|
Jul 24 07:24:23 PM PDT 24 |
Jul 24 07:25:34 PM PDT 24 |
3048229800 ps |
| T112 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2560745650 |
|
|
Jul 24 07:18:46 PM PDT 24 |
Jul 24 07:19:14 PM PDT 24 |
3937960741 ps |
| T826 |
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2655266899 |
|
|
Jul 24 07:19:21 PM PDT 24 |
Jul 24 07:43:47 PM PDT 24 |
29711949657 ps |
| T827 |
/workspace/coverage/default/10.sram_ctrl_alert_test.3441746229 |
|
|
Jul 24 07:19:22 PM PDT 24 |
Jul 24 07:19:23 PM PDT 24 |
12585820 ps |
| T828 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.1302571557 |
|
|
Jul 24 07:20:16 PM PDT 24 |
Jul 24 07:22:07 PM PDT 24 |
33690536864 ps |
| T829 |
/workspace/coverage/default/22.sram_ctrl_bijection.813084641 |
|
|
Jul 24 07:21:24 PM PDT 24 |
Jul 24 07:39:52 PM PDT 24 |
113596260750 ps |
| T830 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.4008897824 |
|
|
Jul 24 07:22:51 PM PDT 24 |
Jul 24 07:29:08 PM PDT 24 |
30003865080 ps |
| T831 |
/workspace/coverage/default/6.sram_ctrl_stress_all.780111247 |
|
|
Jul 24 07:18:36 PM PDT 24 |
Jul 24 08:47:20 PM PDT 24 |
165668867678 ps |
| T832 |
/workspace/coverage/default/48.sram_ctrl_bijection.20951608 |
|
|
Jul 24 07:31:29 PM PDT 24 |
Jul 24 07:59:51 PM PDT 24 |
59566392657 ps |
| T833 |
/workspace/coverage/default/10.sram_ctrl_smoke.1352416260 |
|
|
Jul 24 07:19:02 PM PDT 24 |
Jul 24 07:19:07 PM PDT 24 |
802162513 ps |
| T834 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.3205712740 |
|
|
Jul 24 07:23:11 PM PDT 24 |
Jul 24 07:30:19 PM PDT 24 |
26027894296 ps |
| T835 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.314940740 |
|
|
Jul 24 07:20:06 PM PDT 24 |
Jul 24 07:21:35 PM PDT 24 |
58899659436 ps |
| T836 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.2986183554 |
|
|
Jul 24 07:30:19 PM PDT 24 |
Jul 24 07:33:26 PM PDT 24 |
18780158462 ps |
| T837 |
/workspace/coverage/default/47.sram_ctrl_alert_test.2788768458 |
|
|
Jul 24 07:31:33 PM PDT 24 |
Jul 24 07:31:34 PM PDT 24 |
12393848 ps |
| T838 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.286781733 |
|
|
Jul 24 07:23:01 PM PDT 24 |
Jul 24 07:28:38 PM PDT 24 |
18696306670 ps |
| T839 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.2760780599 |
|
|
Jul 24 07:22:00 PM PDT 24 |
Jul 24 07:22:03 PM PDT 24 |
683247998 ps |
| T840 |
/workspace/coverage/default/5.sram_ctrl_alert_test.3447067786 |
|
|
Jul 24 07:18:37 PM PDT 24 |
Jul 24 07:18:38 PM PDT 24 |
22253776 ps |
| T841 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.248376229 |
|
|
Jul 24 07:31:26 PM PDT 24 |
Jul 24 07:32:40 PM PDT 24 |
4824837345 ps |
| T842 |
/workspace/coverage/default/45.sram_ctrl_alert_test.935475616 |
|
|
Jul 24 07:31:23 PM PDT 24 |
Jul 24 07:31:23 PM PDT 24 |
36876817 ps |
| T843 |
/workspace/coverage/default/30.sram_ctrl_partial_access.1624676903 |
|
|
Jul 24 07:23:10 PM PDT 24 |
Jul 24 07:23:28 PM PDT 24 |
1143067832 ps |
| T844 |
/workspace/coverage/default/3.sram_ctrl_regwen.3813631844 |
|
|
Jul 24 07:18:19 PM PDT 24 |
Jul 24 07:32:27 PM PDT 24 |
12290891343 ps |
| T845 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.242188757 |
|
|
Jul 24 07:31:28 PM PDT 24 |
Jul 24 07:33:04 PM PDT 24 |
12786141301 ps |
| T846 |
/workspace/coverage/default/16.sram_ctrl_partial_access.1371089151 |
|
|
Jul 24 07:20:17 PM PDT 24 |
Jul 24 07:22:49 PM PDT 24 |
660314797 ps |
| T847 |
/workspace/coverage/default/8.sram_ctrl_smoke.4082645420 |
|
|
Jul 24 07:18:42 PM PDT 24 |
Jul 24 07:19:01 PM PDT 24 |
1093371100 ps |
| T848 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3821681345 |
|
|
Jul 24 07:19:35 PM PDT 24 |
Jul 24 07:27:20 PM PDT 24 |
23558270003 ps |
| T849 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.3392804715 |
|
|
Jul 24 07:30:52 PM PDT 24 |
Jul 24 07:33:31 PM PDT 24 |
13181739894 ps |
| T850 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.4185093775 |
|
|
Jul 24 07:30:19 PM PDT 24 |
Jul 24 07:33:13 PM PDT 24 |
26612240889 ps |
| T851 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2396185119 |
|
|
Jul 24 07:19:21 PM PDT 24 |
Jul 24 07:22:18 PM PDT 24 |
3729606464 ps |
| T852 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.113511298 |
|
|
Jul 24 07:21:25 PM PDT 24 |
Jul 24 07:21:31 PM PDT 24 |
708050734 ps |
| T853 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1039022522 |
|
|
Jul 24 07:18:31 PM PDT 24 |
Jul 24 07:19:23 PM PDT 24 |
8661155330 ps |
| T854 |
/workspace/coverage/default/1.sram_ctrl_bijection.3473081767 |
|
|
Jul 24 07:18:03 PM PDT 24 |
Jul 24 07:43:13 PM PDT 24 |
249826115065 ps |
| T855 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.3163776865 |
|
|
Jul 24 07:24:02 PM PDT 24 |
Jul 24 07:48:03 PM PDT 24 |
18406234871 ps |
| T856 |
/workspace/coverage/default/11.sram_ctrl_executable.1957613934 |
|
|
Jul 24 07:19:28 PM PDT 24 |
Jul 24 07:25:17 PM PDT 24 |
9202002804 ps |
| T857 |
/workspace/coverage/default/21.sram_ctrl_partial_access.2145414570 |
|
|
Jul 24 07:21:26 PM PDT 24 |
Jul 24 07:21:45 PM PDT 24 |
610571783 ps |
| T858 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3902875349 |
|
|
Jul 24 07:21:38 PM PDT 24 |
Jul 24 07:29:26 PM PDT 24 |
31041494910 ps |
| T859 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.3070530409 |
|
|
Jul 24 07:19:28 PM PDT 24 |
Jul 24 07:22:08 PM PDT 24 |
6921728686 ps |
| T860 |
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.239204541 |
|
|
Jul 24 07:18:36 PM PDT 24 |
Jul 24 07:26:44 PM PDT 24 |
7426920500 ps |
| T861 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.1855029238 |
|
|
Jul 24 07:23:34 PM PDT 24 |
Jul 24 07:27:12 PM PDT 24 |
13229173589 ps |
| T862 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.29751944 |
|
|
Jul 24 07:31:26 PM PDT 24 |
Jul 24 07:31:34 PM PDT 24 |
700294105 ps |
| T113 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3812819128 |
|
|
Jul 24 07:25:03 PM PDT 24 |
Jul 24 07:25:12 PM PDT 24 |
279570326 ps |
| T863 |
/workspace/coverage/default/2.sram_ctrl_smoke.762996186 |
|
|
Jul 24 07:18:08 PM PDT 24 |
Jul 24 07:18:26 PM PDT 24 |
5414362637 ps |
| T864 |
/workspace/coverage/default/3.sram_ctrl_executable.309002324 |
|
|
Jul 24 07:18:16 PM PDT 24 |
Jul 24 07:36:58 PM PDT 24 |
59232434487 ps |
| T865 |
/workspace/coverage/default/8.sram_ctrl_regwen.1077744431 |
|
|
Jul 24 07:18:48 PM PDT 24 |
Jul 24 07:20:51 PM PDT 24 |
3514780648 ps |
| T866 |
/workspace/coverage/default/7.sram_ctrl_max_throughput.1110904527 |
|
|
Jul 24 07:18:51 PM PDT 24 |
Jul 24 07:19:06 PM PDT 24 |
2767412628 ps |
| T867 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.1970531876 |
|
|
Jul 24 07:23:10 PM PDT 24 |
Jul 24 07:23:36 PM PDT 24 |
3205533218 ps |
| T868 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.4023015371 |
|
|
Jul 24 07:21:02 PM PDT 24 |
Jul 24 07:24:49 PM PDT 24 |
3574262825 ps |
| T869 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.595795371 |
|
|
Jul 24 07:31:08 PM PDT 24 |
Jul 24 07:31:41 PM PDT 24 |
5306003516 ps |
| T870 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2215562794 |
|
|
Jul 24 07:31:12 PM PDT 24 |
Jul 24 07:36:44 PM PDT 24 |
18734119735 ps |
| T871 |
/workspace/coverage/default/36.sram_ctrl_regwen.2343410148 |
|
|
Jul 24 07:24:38 PM PDT 24 |
Jul 24 07:43:32 PM PDT 24 |
93801689382 ps |
| T872 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.950060162 |
|
|
Jul 24 07:18:35 PM PDT 24 |
Jul 24 07:19:12 PM PDT 24 |
734579031 ps |
| T873 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.18386080 |
|
|
Jul 24 07:20:44 PM PDT 24 |
Jul 24 07:22:49 PM PDT 24 |
1937935873 ps |
| T874 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.1287390432 |
|
|
Jul 24 07:22:17 PM PDT 24 |
Jul 24 07:23:28 PM PDT 24 |
3852211914 ps |
| T875 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.2729027803 |
|
|
Jul 24 07:20:29 PM PDT 24 |
Jul 24 07:31:11 PM PDT 24 |
33352907439 ps |
| T876 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.2088644057 |
|
|
Jul 24 07:22:33 PM PDT 24 |
Jul 24 07:49:08 PM PDT 24 |
94508421419 ps |
| T877 |
/workspace/coverage/default/8.sram_ctrl_partial_access.3116617253 |
|
|
Jul 24 07:18:50 PM PDT 24 |
Jul 24 07:20:02 PM PDT 24 |
11124072960 ps |
| T878 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.2608188274 |
|
|
Jul 24 07:20:31 PM PDT 24 |
Jul 24 07:27:52 PM PDT 24 |
7295626813 ps |
| T879 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3286241628 |
|
|
Jul 24 07:19:22 PM PDT 24 |
Jul 24 07:22:44 PM PDT 24 |
5775212468 ps |
| T880 |
/workspace/coverage/default/14.sram_ctrl_regwen.1469712403 |
|
|
Jul 24 07:20:00 PM PDT 24 |
Jul 24 07:24:28 PM PDT 24 |
21589517989 ps |
| T881 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1171787767 |
|
|
Jul 24 07:30:52 PM PDT 24 |
Jul 24 07:32:16 PM PDT 24 |
2998614260 ps |
| T882 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1454004505 |
|
|
Jul 24 07:18:16 PM PDT 24 |
Jul 24 07:20:47 PM PDT 24 |
8960094199 ps |
| T883 |
/workspace/coverage/default/39.sram_ctrl_executable.1948526537 |
|
|
Jul 24 07:30:29 PM PDT 24 |
Jul 24 07:41:30 PM PDT 24 |
35697121153 ps |
| T884 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1110431235 |
|
|
Jul 24 07:23:53 PM PDT 24 |
Jul 24 07:25:06 PM PDT 24 |
28815076682 ps |
| T885 |
/workspace/coverage/default/43.sram_ctrl_alert_test.3398412836 |
|
|
Jul 24 07:32:03 PM PDT 24 |
Jul 24 07:32:03 PM PDT 24 |
105472733 ps |
| T886 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2059994698 |
|
|
Jul 24 07:18:34 PM PDT 24 |
Jul 24 07:20:41 PM PDT 24 |
68265659131 ps |
| T887 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.3089984361 |
|
|
Jul 24 07:20:29 PM PDT 24 |
Jul 24 07:21:36 PM PDT 24 |
36717180645 ps |
| T888 |
/workspace/coverage/default/12.sram_ctrl_stress_all.1674727148 |
|
|
Jul 24 07:19:40 PM PDT 24 |
Jul 24 08:34:30 PM PDT 24 |
65339081914 ps |
| T889 |
/workspace/coverage/default/40.sram_ctrl_bijection.3722801944 |
|
|
Jul 24 07:30:37 PM PDT 24 |
Jul 24 07:44:58 PM PDT 24 |
37405552782 ps |
| T890 |
/workspace/coverage/default/38.sram_ctrl_smoke.2860794449 |
|
|
Jul 24 07:30:17 PM PDT 24 |
Jul 24 07:30:36 PM PDT 24 |
1102995114 ps |
| T891 |
/workspace/coverage/default/35.sram_ctrl_partial_access.2041424455 |
|
|
Jul 24 07:24:00 PM PDT 24 |
Jul 24 07:24:17 PM PDT 24 |
3565558256 ps |
| T892 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.25143733 |
|
|
Jul 24 07:20:43 PM PDT 24 |
Jul 24 07:23:46 PM PDT 24 |
41393981208 ps |
| T893 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.4027491602 |
|
|
Jul 24 07:21:26 PM PDT 24 |
Jul 24 07:22:51 PM PDT 24 |
5361191470 ps |
| T894 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.135811058 |
|
|
Jul 24 07:31:26 PM PDT 24 |
Jul 24 07:31:56 PM PDT 24 |
21737136497 ps |
| T895 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.815625873 |
|
|
Jul 24 07:18:19 PM PDT 24 |
Jul 24 07:22:34 PM PDT 24 |
17912341160 ps |
| T896 |
/workspace/coverage/default/14.sram_ctrl_executable.3337757156 |
|
|
Jul 24 07:20:00 PM PDT 24 |
Jul 24 07:44:50 PM PDT 24 |
70858637442 ps |
| T897 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.1688416589 |
|
|
Jul 24 07:18:31 PM PDT 24 |
Jul 24 07:20:04 PM PDT 24 |
793445608 ps |
| T898 |
/workspace/coverage/default/24.sram_ctrl_partial_access.4231017514 |
|
|
Jul 24 07:21:51 PM PDT 24 |
Jul 24 07:22:26 PM PDT 24 |
1533235433 ps |
| T899 |
/workspace/coverage/default/25.sram_ctrl_partial_access.1111868097 |
|
|
Jul 24 07:22:07 PM PDT 24 |
Jul 24 07:22:21 PM PDT 24 |
796275367 ps |
| T900 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.3581174669 |
|
|
Jul 24 07:24:01 PM PDT 24 |
Jul 24 07:24:13 PM PDT 24 |
6852157310 ps |
| T901 |
/workspace/coverage/default/37.sram_ctrl_partial_access.2601628089 |
|
|
Jul 24 07:24:30 PM PDT 24 |
Jul 24 07:24:39 PM PDT 24 |
722063455 ps |
| T902 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.1257266120 |
|
|
Jul 24 07:22:52 PM PDT 24 |
Jul 24 07:37:24 PM PDT 24 |
10500567904 ps |
| T903 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.1400257352 |
|
|
Jul 24 07:23:03 PM PDT 24 |
Jul 24 07:42:23 PM PDT 24 |
164651645684 ps |
| T904 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.37973538 |
|
|
Jul 24 07:31:38 PM PDT 24 |
Jul 24 07:31:56 PM PDT 24 |
1929690400 ps |
| T905 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.629587546 |
|
|
Jul 24 07:21:40 PM PDT 24 |
Jul 24 07:24:32 PM PDT 24 |
43077225794 ps |
| T906 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2751073433 |
|
|
Jul 24 07:22:18 PM PDT 24 |
Jul 24 07:22:45 PM PDT 24 |
18897285508 ps |
| T907 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.578053372 |
|
|
Jul 24 07:22:15 PM PDT 24 |
Jul 24 07:28:59 PM PDT 24 |
13703218257 ps |
| T908 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.2785067634 |
|
|
Jul 24 07:23:12 PM PDT 24 |
Jul 24 07:23:16 PM PDT 24 |
1358184448 ps |
| T909 |
/workspace/coverage/default/6.sram_ctrl_partial_access.3771166857 |
|
|
Jul 24 07:18:37 PM PDT 24 |
Jul 24 07:19:12 PM PDT 24 |
1397790391 ps |
| T910 |
/workspace/coverage/default/35.sram_ctrl_smoke.3494442542 |
|
|
Jul 24 07:24:03 PM PDT 24 |
Jul 24 07:24:23 PM PDT 24 |
1103138453 ps |
| T911 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2684576717 |
|
|
Jul 24 07:23:02 PM PDT 24 |
Jul 24 07:24:28 PM PDT 24 |
3057250129 ps |
| T912 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.3059830264 |
|
|
Jul 24 07:21:17 PM PDT 24 |
Jul 24 07:26:20 PM PDT 24 |
74974172902 ps |
| T913 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3499217132 |
|
|
Jul 24 07:22:56 PM PDT 24 |
Jul 24 07:33:30 PM PDT 24 |
24700403055 ps |
| T914 |
/workspace/coverage/default/5.sram_ctrl_smoke.4074783993 |
|
|
Jul 24 07:18:22 PM PDT 24 |
Jul 24 07:19:54 PM PDT 24 |
971786639 ps |
| T915 |
/workspace/coverage/default/18.sram_ctrl_stress_all.4142253546 |
|
|
Jul 24 07:20:47 PM PDT 24 |
Jul 24 08:08:13 PM PDT 24 |
242423816817 ps |
| T916 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.3051866879 |
|
|
Jul 24 07:18:49 PM PDT 24 |
Jul 24 07:20:01 PM PDT 24 |
7336950246 ps |
| T917 |
/workspace/coverage/default/27.sram_ctrl_bijection.4114678329 |
|
|
Jul 24 07:22:31 PM PDT 24 |
Jul 24 07:43:53 PM PDT 24 |
36224407574 ps |
| T918 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.4055058752 |
|
|
Jul 24 07:19:01 PM PDT 24 |
Jul 24 07:21:33 PM PDT 24 |
2714946579 ps |
| T919 |
/workspace/coverage/default/5.sram_ctrl_stress_all.2181612437 |
|
|
Jul 24 07:18:38 PM PDT 24 |
Jul 24 08:02:53 PM PDT 24 |
1012836856186 ps |
| T920 |
/workspace/coverage/default/24.sram_ctrl_stress_all.1409177466 |
|
|
Jul 24 07:21:57 PM PDT 24 |
Jul 24 08:23:00 PM PDT 24 |
415828688085 ps |
| T921 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.3689390392 |
|
|
Jul 24 07:19:47 PM PDT 24 |
Jul 24 07:21:20 PM PDT 24 |
16234492522 ps |
| T922 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2822469526 |
|
|
Jul 24 07:18:32 PM PDT 24 |
Jul 24 07:50:24 PM PDT 24 |
17799426261 ps |
| T923 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.3451356637 |
|
|
Jul 24 07:22:08 PM PDT 24 |
Jul 24 07:26:08 PM PDT 24 |
37197528593 ps |
| T924 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2736331372 |
|
|
Jul 24 07:23:59 PM PDT 24 |
Jul 24 07:30:20 PM PDT 24 |
106019555024 ps |
| T925 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.572427551 |
|
|
Jul 24 07:20:42 PM PDT 24 |
Jul 24 07:20:48 PM PDT 24 |
6739408137 ps |
| T926 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3907314251 |
|
|
Jul 24 07:21:35 PM PDT 24 |
Jul 24 07:21:48 PM PDT 24 |
4567507382 ps |
| T927 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.3645515254 |
|
|
Jul 24 07:22:41 PM PDT 24 |
Jul 24 07:25:12 PM PDT 24 |
9100530026 ps |
| T928 |
/workspace/coverage/default/16.sram_ctrl_stress_all.2546992384 |
|
|
Jul 24 07:20:24 PM PDT 24 |
Jul 24 08:35:47 PM PDT 24 |
193466236935 ps |
| T929 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2580328807 |
|
|
Jul 24 07:30:37 PM PDT 24 |
Jul 24 07:31:21 PM PDT 24 |
13095302078 ps |
| T930 |
/workspace/coverage/default/17.sram_ctrl_bijection.1704839334 |
|
|
Jul 24 07:20:22 PM PDT 24 |
Jul 24 07:47:30 PM PDT 24 |
49878783825 ps |
| T931 |
/workspace/coverage/default/21.sram_ctrl_alert_test.1280911713 |
|
|
Jul 24 07:21:25 PM PDT 24 |
Jul 24 07:21:26 PM PDT 24 |
47758978 ps |
| T932 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2153416166 |
|
|
Jul 24 07:31:32 PM PDT 24 |
Jul 24 07:36:57 PM PDT 24 |
17245561456 ps |
| T933 |
/workspace/coverage/default/26.sram_ctrl_mem_walk.1330859588 |
|
|
Jul 24 07:22:25 PM PDT 24 |
Jul 24 07:28:29 PM PDT 24 |
41345379471 ps |
| T934 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.3117532518 |
|
|
Jul 24 07:24:23 PM PDT 24 |
Jul 24 07:24:26 PM PDT 24 |
676473823 ps |
| T935 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.4045566126 |
|
|
Jul 24 07:19:46 PM PDT 24 |
Jul 24 07:19:57 PM PDT 24 |
400287671 ps |
| T67 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2534023163 |
|
|
Jul 24 07:01:56 PM PDT 24 |
Jul 24 07:01:56 PM PDT 24 |
25807482 ps |
| T936 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2303779218 |
|
|
Jul 24 07:02:14 PM PDT 24 |
Jul 24 07:02:16 PM PDT 24 |
214244388 ps |
| T68 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2222626365 |
|
|
Jul 24 07:02:08 PM PDT 24 |
Jul 24 07:03:02 PM PDT 24 |
28175861201 ps |
| T69 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1504577865 |
|
|
Jul 24 07:02:22 PM PDT 24 |
Jul 24 07:02:23 PM PDT 24 |
87402190 ps |
| T937 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3577587332 |
|
|
Jul 24 07:02:21 PM PDT 24 |
Jul 24 07:02:23 PM PDT 24 |
30036252 ps |
| T80 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2544890206 |
|
|
Jul 24 07:02:22 PM PDT 24 |
Jul 24 07:03:13 PM PDT 24 |
29356116379 ps |
| T938 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3045928168 |
|
|
Jul 24 07:02:07 PM PDT 24 |
Jul 24 07:02:11 PM PDT 24 |
2844694238 ps |
| T81 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.864252802 |
|
|
Jul 24 07:02:02 PM PDT 24 |
Jul 24 07:02:55 PM PDT 24 |
28279503398 ps |
| T107 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.670391321 |
|
|
Jul 24 07:01:56 PM PDT 24 |
Jul 24 07:01:57 PM PDT 24 |
11428192 ps |
| T82 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1224272820 |
|
|
Jul 24 07:02:21 PM PDT 24 |
Jul 24 07:02:22 PM PDT 24 |
37629419 ps |
| T83 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.4057577215 |
|
|
Jul 24 07:02:05 PM PDT 24 |
Jul 24 07:02:06 PM PDT 24 |
46664728 ps |
| T63 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2006136648 |
|
|
Jul 24 07:02:01 PM PDT 24 |
Jul 24 07:02:03 PM PDT 24 |
971474307 ps |
| T939 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2128806706 |
|
|
Jul 24 07:02:16 PM PDT 24 |
Jul 24 07:02:18 PM PDT 24 |
141521076 ps |
| T940 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3310046227 |
|
|
Jul 24 07:02:23 PM PDT 24 |
Jul 24 07:02:27 PM PDT 24 |
3391010525 ps |
| T64 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3960937739 |
|
|
Jul 24 07:01:58 PM PDT 24 |
Jul 24 07:02:00 PM PDT 24 |
394961159 ps |
| T84 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2130988049 |
|
|
Jul 24 07:02:09 PM PDT 24 |
Jul 24 07:02:10 PM PDT 24 |
28978994 ps |
| T941 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3287310339 |
|
|
Jul 24 07:02:08 PM PDT 24 |
Jul 24 07:02:12 PM PDT 24 |
1458302814 ps |
| T942 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1657906497 |
|
|
Jul 24 07:01:53 PM PDT 24 |
Jul 24 07:01:57 PM PDT 24 |
368334294 ps |
| T65 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3846580773 |
|
|
Jul 24 07:02:22 PM PDT 24 |
Jul 24 07:02:24 PM PDT 24 |
80271645 ps |
| T85 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4085062246 |
|
|
Jul 24 07:01:53 PM PDT 24 |
Jul 24 07:01:54 PM PDT 24 |
48747479 ps |
| T943 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.4200853182 |
|
|
Jul 24 07:02:11 PM PDT 24 |
Jul 24 07:02:15 PM PDT 24 |
1895677503 ps |
| T86 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.483705188 |
|
|
Jul 24 07:02:03 PM PDT 24 |
Jul 24 07:02:04 PM PDT 24 |
45723484 ps |
| T88 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1881235569 |
|
|
Jul 24 07:02:10 PM PDT 24 |
Jul 24 07:02:40 PM PDT 24 |
7417289713 ps |
| T944 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1703943701 |
|
|
Jul 24 07:02:14 PM PDT 24 |
Jul 24 07:02:19 PM PDT 24 |
553451427 ps |
| T102 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.321746295 |
|
|
Jul 24 07:02:27 PM PDT 24 |
Jul 24 07:02:59 PM PDT 24 |
14757782966 ps |
| T103 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4042925868 |
|
|
Jul 24 07:02:29 PM PDT 24 |
Jul 24 07:02:30 PM PDT 24 |
51235584 ps |
| T945 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3960615225 |
|
|
Jul 24 07:02:29 PM PDT 24 |
Jul 24 07:02:29 PM PDT 24 |
14832127 ps |
| T946 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1028710528 |
|
|
Jul 24 07:02:23 PM PDT 24 |
Jul 24 07:02:24 PM PDT 24 |
40438568 ps |
| T89 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3423592720 |
|
|
Jul 24 07:02:08 PM PDT 24 |
Jul 24 07:02:09 PM PDT 24 |
33460988 ps |
| T115 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2866814531 |
|
|
Jul 24 07:02:09 PM PDT 24 |
Jul 24 07:02:11 PM PDT 24 |
398707776 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1923343489 |
|
|
Jul 24 07:01:53 PM PDT 24 |
Jul 24 07:01:55 PM PDT 24 |
162272232 ps |
| T947 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1685863702 |
|
|
Jul 24 07:01:58 PM PDT 24 |
Jul 24 07:02:00 PM PDT 24 |
157730180 ps |
| T119 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.969384879 |
|
|
Jul 24 07:01:54 PM PDT 24 |
Jul 24 07:01:55 PM PDT 24 |
583347564 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2921561341 |
|
|
Jul 24 07:01:54 PM PDT 24 |
Jul 24 07:01:57 PM PDT 24 |
130914283 ps |
| T120 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2600746021 |
|
|
Jul 24 07:02:00 PM PDT 24 |
Jul 24 07:02:02 PM PDT 24 |
626575083 ps |
| T949 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2402869000 |
|
|
Jul 24 07:02:01 PM PDT 24 |
Jul 24 07:02:02 PM PDT 24 |
15828328 ps |
| T950 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1412499397 |
|
|
Jul 24 07:02:15 PM PDT 24 |
Jul 24 07:02:16 PM PDT 24 |
25264963 ps |
| T951 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2278953113 |
|
|
Jul 24 07:01:55 PM PDT 24 |
Jul 24 07:01:56 PM PDT 24 |
15322137 ps |
| T952 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.991715754 |
|
|
Jul 24 07:02:16 PM PDT 24 |
Jul 24 07:02:20 PM PDT 24 |
1366223128 ps |
| T953 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2499908520 |
|
|
Jul 24 07:02:00 PM PDT 24 |
Jul 24 07:02:04 PM PDT 24 |
706844395 ps |
| T954 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2372815423 |
|
|
Jul 24 07:02:08 PM PDT 24 |
Jul 24 07:02:09 PM PDT 24 |
25123549 ps |
| T91 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2733914150 |
|
|
Jul 24 07:02:22 PM PDT 24 |
Jul 24 07:03:13 PM PDT 24 |
14662211172 ps |
| T92 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1492915313 |
|
|
Jul 24 07:02:08 PM PDT 24 |
Jul 24 07:03:03 PM PDT 24 |
14391546524 ps |
| T955 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.318876864 |
|
|
Jul 24 07:02:14 PM PDT 24 |
Jul 24 07:02:18 PM PDT 24 |
1416904402 ps |
| T956 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2879016402 |
|
|
Jul 24 07:02:22 PM PDT 24 |
Jul 24 07:02:27 PM PDT 24 |
557079963 ps |
| T957 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.758582446 |
|
|
Jul 24 07:02:11 PM PDT 24 |
Jul 24 07:02:15 PM PDT 24 |
409531039 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3072384861 |
|
|
Jul 24 07:01:54 PM PDT 24 |
Jul 24 07:02:23 PM PDT 24 |
3875741602 ps |
| T959 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.868848602 |
|
|
Jul 24 07:02:24 PM PDT 24 |
Jul 24 07:02:25 PM PDT 24 |
50765974 ps |
| T117 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3987527831 |
|
|
Jul 24 07:02:14 PM PDT 24 |
Jul 24 07:02:17 PM PDT 24 |
846606179 ps |
| T124 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3932952588 |
|
|
Jul 24 07:02:22 PM PDT 24 |
Jul 24 07:02:23 PM PDT 24 |
408356311 ps |
| T960 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.806080253 |
|
|
Jul 24 07:02:07 PM PDT 24 |
Jul 24 07:02:08 PM PDT 24 |
98285408 ps |
| T961 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1339643422 |
|
|
Jul 24 07:02:15 PM PDT 24 |
Jul 24 07:02:16 PM PDT 24 |
70792109 ps |
| T962 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3918432828 |
|
|
Jul 24 07:01:55 PM PDT 24 |
Jul 24 07:02:00 PM PDT 24 |
1000220973 ps |
| T963 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2225192632 |
|
|
Jul 24 07:01:54 PM PDT 24 |
Jul 24 07:01:55 PM PDT 24 |
34025506 ps |
| T964 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2415976754 |
|
|
Jul 24 07:02:22 PM PDT 24 |
Jul 24 07:02:25 PM PDT 24 |
364468918 ps |
| T97 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3805035563 |
|
|
Jul 24 07:02:21 PM PDT 24 |
Jul 24 07:03:10 PM PDT 24 |
73540973733 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1049775443 |
|
|
Jul 24 07:02:00 PM PDT 24 |
Jul 24 07:02:00 PM PDT 24 |
24675129 ps |
| T966 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2181298824 |
|
|
Jul 24 07:02:02 PM PDT 24 |
Jul 24 07:02:07 PM PDT 24 |
324923403 ps |
| T967 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2095985317 |
|
|
Jul 24 07:02:07 PM PDT 24 |
Jul 24 07:02:08 PM PDT 24 |
13893598 ps |
| T968 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.4285598829 |
|
|
Jul 24 07:02:08 PM PDT 24 |
Jul 24 07:02:12 PM PDT 24 |
772837829 ps |
| T969 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2272652855 |
|
|
Jul 24 07:02:11 PM PDT 24 |
Jul 24 07:02:12 PM PDT 24 |
212761725 ps |
| T970 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3027449217 |
|
|
Jul 24 07:02:27 PM PDT 24 |
Jul 24 07:02:31 PM PDT 24 |
39429073 ps |
| T971 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2755708318 |
|
|
Jul 24 07:02:04 PM PDT 24 |
Jul 24 07:02:07 PM PDT 24 |
353099989 ps |
| T98 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3804395692 |
|
|
Jul 24 07:02:01 PM PDT 24 |
Jul 24 07:02:54 PM PDT 24 |
7100676341 ps |
| T972 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3107851370 |
|
|
Jul 24 07:02:21 PM PDT 24 |
Jul 24 07:02:25 PM PDT 24 |
1445884196 ps |
| T973 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1070609687 |
|
|
Jul 24 07:01:53 PM PDT 24 |
Jul 24 07:01:57 PM PDT 24 |
115766069 ps |
| T974 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4015552028 |
|
|
Jul 24 07:01:55 PM PDT 24 |
Jul 24 07:01:56 PM PDT 24 |
22826004 ps |
| T975 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.285181954 |
|
|
Jul 24 07:02:21 PM PDT 24 |
Jul 24 07:02:25 PM PDT 24 |
100707588 ps |
| T976 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2057421773 |
|
|
Jul 24 07:02:14 PM PDT 24 |
Jul 24 07:02:16 PM PDT 24 |
149049034 ps |
| T122 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1972044837 |
|
|
Jul 24 07:02:07 PM PDT 24 |
Jul 24 07:02:10 PM PDT 24 |
139889356 ps |
| T977 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2799880172 |
|
|
Jul 24 07:01:55 PM PDT 24 |
Jul 24 07:01:59 PM PDT 24 |
366390148 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1912160348 |
|
|
Jul 24 07:02:08 PM PDT 24 |
Jul 24 07:02:14 PM PDT 24 |
149586793 ps |
| T979 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1638955112 |
|
|
Jul 24 07:02:08 PM PDT 24 |
Jul 24 07:02:09 PM PDT 24 |
240221302 ps |
| T101 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1934411871 |
|
|
Jul 24 07:01:57 PM PDT 24 |
Jul 24 07:02:51 PM PDT 24 |
7216668864 ps |
| T980 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2416452903 |
|
|
Jul 24 07:01:55 PM PDT 24 |
Jul 24 07:01:57 PM PDT 24 |
23324487 ps |
| T981 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4006161542 |
|
|
Jul 24 07:02:03 PM PDT 24 |
Jul 24 07:02:04 PM PDT 24 |
322109511 ps |
| T982 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.376696154 |
|
|
Jul 24 07:01:53 PM PDT 24 |
Jul 24 07:01:55 PM PDT 24 |
137043387 ps |
| T983 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2182622008 |
|
|
Jul 24 07:02:09 PM PDT 24 |
Jul 24 07:02:10 PM PDT 24 |
12153448 ps |
| T984 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2131987286 |
|
|
Jul 24 07:02:08 PM PDT 24 |
Jul 24 07:02:09 PM PDT 24 |
41711799 ps |
| T985 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.420470169 |
|
|
Jul 24 07:01:54 PM PDT 24 |
Jul 24 07:01:56 PM PDT 24 |
284455763 ps |
| T986 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2564933415 |
|
|
Jul 24 07:02:00 PM PDT 24 |
Jul 24 07:02:03 PM PDT 24 |
213259244 ps |
| T987 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3655597647 |
|
|
Jul 24 07:02:27 PM PDT 24 |
Jul 24 07:02:28 PM PDT 24 |
18631346 ps |
| T988 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.443083175 |
|
|
Jul 24 07:01:57 PM PDT 24 |
Jul 24 07:01:58 PM PDT 24 |
13539706 ps |
| T99 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2147144296 |
|
|
Jul 24 07:02:02 PM PDT 24 |
Jul 24 07:02:03 PM PDT 24 |
154429934 ps |
| T118 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.339144631 |
|
|
Jul 24 07:02:17 PM PDT 24 |
Jul 24 07:02:20 PM PDT 24 |
310964316 ps |
| T989 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1513945685 |
|
|
Jul 24 07:02:27 PM PDT 24 |
Jul 24 07:03:17 PM PDT 24 |
15194813961 ps |
| T990 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1471990737 |
|
|
Jul 24 07:02:24 PM PDT 24 |
Jul 24 07:02:24 PM PDT 24 |
15293852 ps |
| T991 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.406519306 |
|
|
Jul 24 07:02:15 PM PDT 24 |
Jul 24 07:02:17 PM PDT 24 |
45820629 ps |
| T100 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.754003815 |
|
|
Jul 24 07:01:55 PM PDT 24 |
Jul 24 07:01:55 PM PDT 24 |
58189705 ps |
| T992 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2621710220 |
|
|
Jul 24 07:01:55 PM PDT 24 |
Jul 24 07:01:55 PM PDT 24 |
91802234 ps |
| T993 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2315458435 |
|
|
Jul 24 07:01:57 PM PDT 24 |
Jul 24 07:01:58 PM PDT 24 |
30871501 ps |
| T994 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3205997634 |
|
|
Jul 24 07:02:27 PM PDT 24 |
Jul 24 07:02:31 PM PDT 24 |
1356263250 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1521921945 |
|
|
Jul 24 07:01:55 PM PDT 24 |
Jul 24 07:01:55 PM PDT 24 |
15094303 ps |
| T996 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3772875506 |
|
|
Jul 24 07:02:13 PM PDT 24 |
Jul 24 07:02:14 PM PDT 24 |
27440032 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4279963871 |
|
|
Jul 24 07:02:14 PM PDT 24 |
Jul 24 07:02:15 PM PDT 24 |
13615820 ps |
| T998 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.954848092 |
|
|
Jul 24 07:01:55 PM PDT 24 |
Jul 24 07:02:46 PM PDT 24 |
7298042611 ps |
| T999 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1745011513 |
|
|
Jul 24 07:02:22 PM PDT 24 |
Jul 24 07:02:26 PM PDT 24 |
128991672 ps |
| T121 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2644734656 |
|
|
Jul 24 07:02:21 PM PDT 24 |
Jul 24 07:02:24 PM PDT 24 |
240315679 ps |
| T1000 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.556863535 |
|
|
Jul 24 07:02:09 PM PDT 24 |
Jul 24 07:02:10 PM PDT 24 |
30980216 ps |
| T1001 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.4205094634 |
|
|
Jul 24 07:02:00 PM PDT 24 |
Jul 24 07:02:01 PM PDT 24 |
15573642 ps |
| T1002 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.988925793 |
|
|
Jul 24 07:02:03 PM PDT 24 |
Jul 24 07:02:04 PM PDT 24 |
13278935 ps |
| T1003 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.861574566 |
|
|
Jul 24 07:02:04 PM PDT 24 |
Jul 24 07:02:08 PM PDT 24 |
110541790 ps |