Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16369343	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

158586874

1

T3

214941

T4

339496

T5

94563

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	86160796	1			T3	117908		T4	186661		T5	51935
values[0x0]	42767974	1			T3	57113		T4	90195		T5	25024
values[0x1]	46027447	1			T3	61475		T4	96378		T5	27175

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8316968	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

166639249

1

T3

225665

T4

356280

T5

99422

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	528550	1			T3	861		T4	1440		T5	369
valid_sources[0x01]	520938	1			T3	755		T4	1371		T5	427
valid_sources[0x02]	539624	1			T3	1625		T4	1583		T5	361
valid_sources[0x03]	528330	1			T3	1643		T4	1536		T5	404
valid_sources[0x04]	541849	1			T3	985		T4	1399		T5	395
valid_sources[0x05]	530142	1			T3	1232		T4	1444		T5	413
valid_sources[0x06]	582703	1			T3	1130		T4	1430		T5	395
valid_sources[0x07]	524588	1			T3	1107		T4	1394		T5	437
valid_sources[0x08]	531533	1			T3	886		T4	1403		T5	381
valid_sources[0x09]	500053	1			T3	682		T4	1523		T5	400
valid_sources[0x0a]	617612	1			T3	737		T4	1416		T5	423
valid_sources[0x0b]	577039	1			T3	664		T4	1556		T5	398
valid_sources[0x0c]	515332	1			T3	824		T4	1425		T5	412
valid_sources[0x0d]	657315	1			T3	980		T4	1439		T5	422
valid_sources[0x0e]	574924	1			T3	1349		T4	1454		T5	405
valid_sources[0x0f]	499965	1			T3	996		T4	1403		T5	406
valid_sources[0x10]	508884	1			T3	1159		T4	1446		T5	389
valid_sources[0x11]	501945	1			T3	858		T4	1292		T5	368
valid_sources[0x12]	511065	1			T3	678		T4	1443		T5	374
valid_sources[0x13]	504632	1			T3	655		T4	1502		T5	408
valid_sources[0x14]	572873	1			T3	807		T4	1356		T5	404
valid_sources[0x15]	525258	1			T3	716		T4	1426		T5	429
valid_sources[0x16]	529597	1			T3	928		T4	1454		T5	418
valid_sources[0x17]	1795164	1			T3	942		T4	1557		T5	397
valid_sources[0x18]	1859802	1			T3	778		T4	1593		T5	414
valid_sources[0x19]	507860	1			T3	791		T4	1516		T5	414
valid_sources[0x1a]	532100	1			T3	1868		T4	1404		T5	439
valid_sources[0x1b]	531278	1			T3	743		T4	1484		T5	373
valid_sources[0x1c]	827540	1			T3	610		T4	1585		T5	355
valid_sources[0x1d]	622029	1			T3	698		T4	1497		T5	432
valid_sources[0x1e]	553156	1			T3	796		T4	1463		T5	418
valid_sources[0x1f]	535219	1			T3	525		T4	1290		T5	362
valid_sources[0x20]	515170	1			T3	1343		T4	1365		T5	422
valid_sources[0x21]	513110	1			T3	795		T4	1381		T5	392
valid_sources[0x22]	522106	1			T3	624		T4	1538		T5	415
valid_sources[0x23]	526969	1			T3	702		T4	1334		T5	387
valid_sources[0x24]	533877	1			T3	851		T4	1461		T5	384
valid_sources[0x25]	510286	1			T3	888		T4	1511		T5	430
valid_sources[0x26]	517676	1			T3	1185		T4	1472		T5	429
valid_sources[0x27]	526035	1			T3	876		T4	1640		T5	364
valid_sources[0x28]	555607	1			T3	1122		T4	1437		T5	398
valid_sources[0x29]	553557	1			T3	977		T4	1451		T5	403
valid_sources[0x2a]	498082	1			T3	734		T4	1591		T5	363
valid_sources[0x2b]	606666	1			T3	590		T4	1473		T5	398
valid_sources[0x2c]	538644	1			T3	842		T4	1546		T5	413
valid_sources[0x2d]	597348	1			T3	956		T4	1510		T5	380
valid_sources[0x2e]	631206	1			T3	965		T4	1376		T5	374
valid_sources[0x2f]	547948	1			T3	947		T4	1457		T5	400
valid_sources[0x30]	507771	1			T3	697		T4	1630		T5	457
valid_sources[0x31]	536004	1			T3	840		T4	1455		T5	454
valid_sources[0x32]	1959038	1			T3	753		T4	1460		T5	403
valid_sources[0x33]	535313	1			T3	783		T4	1524		T5	414
valid_sources[0x34]	504692	1			T3	876		T4	1403		T5	363
valid_sources[0x35]	517028	1			T3	1222		T4	1438		T5	373
valid_sources[0x36]	1799955	1			T3	938		T4	1399		T5	396
valid_sources[0x37]	560331	1			T3	470		T4	1382		T5	413
valid_sources[0x38]	721813	1			T3	1549		T4	1500		T5	381
valid_sources[0x39]	559353	1			T3	871		T4	1469		T5	406
valid_sources[0x3a]	544908	1			T3	600		T4	1467		T5	398
valid_sources[0x3b]	533174	1			T3	828		T4	1348		T5	362
valid_sources[0x3c]	510435	1			T3	589		T4	1536		T5	491
valid_sources[0x3d]	1420456	1			T3	718		T4	1388		T5	429
valid_sources[0x3e]	563483	1			T3	499		T4	1527		T5	454
valid_sources[0x3f]	512091	1			T3	1046		T4	1505		T5	498
valid_sources[0x40]	502271	1			T3	775		T4	1391		T5	413
valid_sources[0x41]	606020	1			T3	600		T4	1445		T5	368
valid_sources[0x42]	553268	1			T3	672		T4	1594		T5	363
valid_sources[0x43]	527742	1			T3	1024		T4	1463		T5	414
valid_sources[0x44]	585808	1			T3	1339		T4	1426		T5	363
valid_sources[0x45]	572957	1			T3	1369		T4	1415		T5	402
valid_sources[0x46]	517054	1			T3	1104		T4	1512		T5	371
valid_sources[0x47]	500377	1			T3	682		T4	1469		T5	432
valid_sources[0x48]	531295	1			T3	761		T4	1669		T5	412
valid_sources[0x49]	552173	1			T3	1726		T4	1530		T5	402
valid_sources[0x4a]	514059	1			T3	677		T4	1379		T5	399
valid_sources[0x4b]	2049448	1			T3	1086		T4	1393		T5	370
valid_sources[0x4c]	505208	1			T3	837		T4	1544		T5	399
valid_sources[0x4d]	575248	1			T3	809		T4	1512		T5	394
valid_sources[0x4e]	513003	1			T3	1150		T4	1437		T5	441
valid_sources[0x4f]	514860	1			T3	1465		T4	1449		T5	380
valid_sources[0x50]	511003	1			T3	1145		T4	1495		T5	413
valid_sources[0x51]	516757	1			T3	955		T4	1457		T5	385
valid_sources[0x52]	516477	1			T3	1196		T4	1557		T5	447
valid_sources[0x53]	510139	1			T3	777		T4	1573		T5	399
valid_sources[0x54]	504157	1			T3	602		T4	1472		T5	437
valid_sources[0x55]	554256	1			T3	924		T4	1462		T5	365
valid_sources[0x56]	623983	1			T3	865		T4	1358		T5	427
valid_sources[0x57]	504428	1			T3	1039		T4	1467		T5	414
valid_sources[0x58]	1208501	1			T3	951		T4	1483		T5	462
valid_sources[0x59]	536232	1			T3	854		T4	1442		T5	369
valid_sources[0x5a]	523111	1			T3	1076		T4	1505		T5	434
valid_sources[0x5b]	530149	1			T3	865		T4	1478		T5	381
valid_sources[0x5c]	1072169	1			T3	727		T4	1276		T5	426
valid_sources[0x5d]	2134184	1			T3	1060		T4	1383		T5	413
valid_sources[0x5e]	538754	1			T3	708		T4	1524		T5	371
valid_sources[0x5f]	526104	1			T3	716		T4	1452		T5	374
valid_sources[0x60]	578333	1			T3	766		T4	1303		T5	438
valid_sources[0x61]	1041687	1			T3	587		T4	1413		T5	403
valid_sources[0x62]	515450	1			T3	743		T4	1550		T5	444
valid_sources[0x63]	509226	1			T3	815		T4	1572		T5	384
valid_sources[0x64]	507930	1			T3	1361		T4	1455		T5	452
valid_sources[0x65]	522073	1			T3	510		T4	1349		T5	393
valid_sources[0x66]	546977	1			T3	1045		T4	1513		T5	409
valid_sources[0x67]	551389	1			T3	787		T4	1465		T5	412
valid_sources[0x68]	541831	1			T3	595		T4	1471		T5	405
valid_sources[0x69]	505869	1			T3	996		T4	1447		T5	394
valid_sources[0x6a]	774695	1			T3	843		T4	1298		T5	374
valid_sources[0x6b]	534699	1			T3	1023		T4	1557		T5	388
valid_sources[0x6c]	528577	1			T3	566		T4	1457		T5	359
valid_sources[0x6d]	534151	1			T3	1136		T4	1451		T5	374
valid_sources[0x6e]	631960	1			T3	639		T4	1315		T5	368
valid_sources[0x6f]	1378257	1			T3	565		T4	1486		T5	393
valid_sources[0x70]	519668	1			T3	789		T4	1405		T5	401
valid_sources[0x71]	502027	1			T3	1097		T4	1436		T5	383
valid_sources[0x72]	554880	1			T3	952		T4	1562		T5	396
valid_sources[0x73]	513350	1			T3	788		T4	1560		T5	444
valid_sources[0x74]	537978	1			T3	890		T4	1379		T5	406
valid_sources[0x75]	1844283	1			T3	668		T4	1420		T5	404
valid_sources[0x76]	881848	1			T3	750		T4	1570		T5	442
valid_sources[0x77]	549131	1			T3	1246		T4	1481		T5	382
valid_sources[0x78]	529653	1			T3	812		T4	1547		T5	417
valid_sources[0x79]	3347988	1			T3	1482		T4	1473		T5	363
valid_sources[0x7a]	530182	1			T3	978		T4	1538		T5	415
valid_sources[0x7b]	533913	1			T3	1043		T4	1359		T5	405
valid_sources[0x7c]	561349	1			T3	1244		T4	1385		T5	422
valid_sources[0x7d]	507695	1			T3	553		T4	1401		T5	303
valid_sources[0x7e]	531915	1			T3	1029		T4	1445		T5	365
valid_sources[0x7f]	522074	1			T3	691		T4	1401		T5	380
valid_sources[0x80]	536141	1			T3	1159		T4	1473		T5	423

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

77938900

1

T3

107133

T4

169740

T5

47192

values[0x0]

all_enables

biggest_size

40324876

1

T3

53795

T4

85010

T5

23597

values[0x1]

all_enables

biggest_size

40323098

1

T3

54013

T4

84746

T5

23774

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43650	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

134106

1

T1

5

T3

29

T5

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	48538	1			T3	39		T6	8		T23	1126
values[0x0]	62437	1			T1	8		T3	46		T4	2
values[0x1]	66781	1			T1	8		T2	1		T3	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34064	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

143692

1

T1

5

T2

1

T3

40

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	883	1			T40	3		T24	4		T25	121
valid_sources[0x01]	477	1			T24	22		T70	6		T51	7
valid_sources[0x02]	565	1			T6	2		T12	1		T24	8
valid_sources[0x03]	679	1			T24	3		T25	2		T55	1
valid_sources[0x04]	619	1			T24	3		T70	3		T123	1
valid_sources[0x05]	675	1			T6	2		T23	2		T24	8
valid_sources[0x06]	773	1			T24	3		T25	60		T20	2
valid_sources[0x07]	695	1			T4	1		T24	11		T25	86
valid_sources[0x08]	737	1			T40	2		T24	16		T26	5
valid_sources[0x09]	772	1			T24	7		T25	2		T70	5
valid_sources[0x0a]	595	1			T3	2		T24	15		T25	1
valid_sources[0x0b]	506	1			T3	1		T12	1		T24	10
valid_sources[0x0c]	606	1			T24	12		T49	1		T25	1
valid_sources[0x0d]	1051	1			T3	3		T23	194		T24	5
valid_sources[0x0e]	824	1			T3	1		T24	9		T70	1
valid_sources[0x0f]	751	1			T6	1		T24	13		T64	1
valid_sources[0x10]	543	1			T23	3		T24	7		T145	1
valid_sources[0x11]	862	1			T3	1		T6	1		T24	13
valid_sources[0x12]	908	1			T3	2		T24	16		T25	100
valid_sources[0x13]	845	1			T2	1		T40	1		T24	9
valid_sources[0x14]	530	1			T40	1		T24	7		T70	1
valid_sources[0x15]	988	1			T23	206		T24	6		T25	1
valid_sources[0x16]	704	1			T6	2		T24	4		T25	141
valid_sources[0x17]	438	1			T24	5		T70	2		T46	14
valid_sources[0x18]	580	1			T3	2		T24	11		T70	2
valid_sources[0x19]	1027	1			T23	502		T24	5		T25	2
valid_sources[0x1a]	671	1			T24	5		T25	48		T70	2
valid_sources[0x1b]	755	1			T3	1		T24	22		T25	1
valid_sources[0x1c]	967	1			T24	9		T25	5		T146	5
valid_sources[0x1d]	619	1			T24	15		T64	1		T20	1
valid_sources[0x1e]	644	1			T24	10		T19	8		T43	37
valid_sources[0x1f]	691	1			T24	1		T25	206		T147	1
valid_sources[0x20]	654	1			T3	2		T24	10		T25	14
valid_sources[0x21]	637	1			T23	81		T40	1		T24	13
valid_sources[0x22]	863	1			T6	1		T24	10		T8	3
valid_sources[0x23]	629	1			T23	1		T24	11		T70	3
valid_sources[0x24]	753	1			T24	4		T25	168		T20	3
valid_sources[0x25]	531	1			T24	5		T54	1		T19	2
valid_sources[0x26]	518	1			T3	1		T24	3		T25	80
valid_sources[0x27]	858	1			T24	8		T70	1		T50	2
valid_sources[0x28]	628	1			T3	2		T23	95		T24	1
valid_sources[0x29]	804	1			T6	2		T24	4		T25	242
valid_sources[0x2a]	488	1			T24	13		T70	5		T51	3
valid_sources[0x2b]	544	1			T6	4		T24	3		T70	3
valid_sources[0x2c]	1088	1			T24	10		T70	3		T76	216
valid_sources[0x2d]	896	1			T3	1		T24	7		T25	1
valid_sources[0x2e]	503	1			T3	1		T24	16		T25	1
valid_sources[0x2f]	584	1			T24	1		T25	5		T20	2
valid_sources[0x30]	1073	1			T24	17		T19	2		T70	2
valid_sources[0x31]	714	1			T3	1		T40	2		T24	5
valid_sources[0x32]	682	1			T6	1		T24	1		T8	1
valid_sources[0x33]	706	1			T24	10		T25	1		T70	1
valid_sources[0x34]	756	1			T23	122		T24	6		T25	3
valid_sources[0x35]	664	1			T3	2		T24	10		T25	2
valid_sources[0x36]	746	1			T3	1		T24	9		T70	4
valid_sources[0x37]	499	1			T3	1		T24	2		T25	3
valid_sources[0x38]	635	1			T24	12		T70	3		T50	2
valid_sources[0x39]	587	1			T3	1		T40	2		T24	11
valid_sources[0x3a]	721	1			T24	11		T25	105		T70	2
valid_sources[0x3b]	531	1			T3	1		T24	4		T8	2
valid_sources[0x3c]	635	1			T24	6		T19	1		T70	3
valid_sources[0x3d]	781	1			T3	1		T24	3		T25	1
valid_sources[0x3e]	812	1			T24	13		T8	1		T70	3
valid_sources[0x3f]	1000	1			T24	8		T25	55		T64	1
valid_sources[0x40]	763	1			T24	21		T25	111		T7	5
valid_sources[0x41]	799	1			T24	1		T25	1		T20	2
valid_sources[0x42]	571	1			T3	1		T24	4		T70	4
valid_sources[0x43]	567	1			T24	2		T70	3		T46	14
valid_sources[0x44]	523	1			T24	28		T70	4		T46	9
valid_sources[0x45]	609	1			T3	4		T24	9		T70	3
valid_sources[0x46]	847	1			T24	16		T49	1		T70	2
valid_sources[0x47]	641	1			T24	6		T25	141		T8	1
valid_sources[0x48]	680	1			T24	9		T70	1		T46	17
valid_sources[0x49]	875	1			T3	1		T24	9		T63	6
valid_sources[0x4a]	644	1			T6	2		T24	9		T25	1
valid_sources[0x4b]	808	1			T24	4		T20	1		T70	1
valid_sources[0x4c]	1009	1			T23	257		T24	3		T8	1
valid_sources[0x4d]	880	1			T23	252		T24	5		T8	1
valid_sources[0x4e]	556	1			T3	2		T24	9		T64	1
valid_sources[0x4f]	712	1			T40	1		T24	15		T25	1
valid_sources[0x50]	697	1			T3	1		T40	1		T24	6
valid_sources[0x51]	732	1			T24	6		T25	1		T70	1
valid_sources[0x52]	534	1			T11	15		T24	10		T25	2
valid_sources[0x53]	543	1			T24	3		T27	1		T70	4
valid_sources[0x54]	583	1			T6	2		T24	11		T20	1
valid_sources[0x55]	638	1			T12	2		T24	1		T8	1
valid_sources[0x56]	488	1			T24	11		T25	1		T70	8
valid_sources[0x57]	587	1			T24	3		T25	2		T70	4
valid_sources[0x58]	1037	1			T23	381		T24	5		T25	5
valid_sources[0x59]	768	1			T24	11		T49	2		T25	2
valid_sources[0x5a]	690	1			T24	13		T25	3		T70	6
valid_sources[0x5b]	561	1			T24	5		T70	5		T46	17
valid_sources[0x5c]	522	1			T3	2		T24	8		T70	2
valid_sources[0x5d]	938	1			T3	2		T6	1		T9	1
valid_sources[0x5e]	720	1			T24	5		T49	1		T25	157
valid_sources[0x5f]	572	1			T24	3		T25	1		T70	5
valid_sources[0x60]	938	1			T24	7		T25	1		T70	2
valid_sources[0x61]	662	1			T24	7		T70	5		T50	1
valid_sources[0x62]	447	1			T24	2		T25	6		T64	1
valid_sources[0x63]	610	1			T24	10		T25	1		T70	3
valid_sources[0x64]	532	1			T24	6		T8	1		T20	1
valid_sources[0x65]	785	1			T24	5		T25	203		T8	2
valid_sources[0x66]	836	1			T24	4		T70	1		T46	14
valid_sources[0x67]	593	1			T3	5		T12	3		T23	2
valid_sources[0x68]	609	1			T3	1		T24	11		T25	1
valid_sources[0x69]	533	1			T24	14		T54	1		T46	10
valid_sources[0x6a]	806	1			T24	17		T19	2		T147	1
valid_sources[0x6b]	678	1			T24	6		T8	1		T70	1
valid_sources[0x6c]	1046	1			T3	2		T10	43		T23	434
valid_sources[0x6d]	638	1			T24	11		T25	98		T70	3
valid_sources[0x6e]	558	1			T24	2		T42	2		T64	1
valid_sources[0x6f]	887	1			T3	1		T12	1		T24	14
valid_sources[0x70]	677	1			T3	1		T24	2		T25	115
valid_sources[0x71]	673	1			T24	10		T25	110		T148	1
valid_sources[0x72]	641	1			T24	10		T25	1		T70	8
valid_sources[0x73]	657	1			T24	6		T64	1		T8	1
valid_sources[0x74]	827	1			T24	14		T146	1		T70	1
valid_sources[0x75]	657	1			T24	12		T25	3		T70	3
valid_sources[0x76]	761	1			T23	107		T40	2		T24	6
valid_sources[0x77]	698	1			T3	1		T24	4		T46	15
valid_sources[0x78]	745	1			T24	9		T70	3		T51	1
valid_sources[0x79]	701	1			T24	11		T55	1		T26	1
valid_sources[0x7a]	730	1			T24	7		T25	18		T20	1
valid_sources[0x7b]	833	1			T24	3		T49	1		T70	3
valid_sources[0x7c]	728	1			T24	11		T8	1		T70	2
valid_sources[0x7d]	696	1			T24	15		T25	1		T70	8
valid_sources[0x7e]	940	1			T3	3		T24	14		T70	3
valid_sources[0x7f]	646	1			T3	3		T40	4		T24	13
valid_sources[0x80]	631	1			T23	4		T40	1		T24	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

35977

1

T3

11

T6

3

T23

1061

values[0x0]

all_enables

biggest_size

50586

1

T1

5

T3

13

T5

3

values[0x1]

all_enables

biggest_size

47543

1

T3

5

T5

2

T6

5