Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16249345

1

T3

19500

T4

33738

T5

9571

full_word

155579423

1

T3

194727

T4

339496

T5

94563

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	171828468	1			T3	214227		T4	373234		T5	104134
auto[TlIntgErrCmd]	98	1			T65	5		T66	5		T67	7
auto[TlIntgErrData]	106	1			T65	7		T66	6		T67	7
auto[TlIntgErrBoth]	96	1			T65	8		T66	9		T67	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82971690

1

T3

96935

T4

186661

T5

51935

auto[1]

88857078

1

T3

117292

T4

186573

T5

52199

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7965498	1			T3	8836		T4	16921		T5	4743
auto[TlIntgErrNone]	partial	auto[1]	8283565	1			T3	10664		T4	16817		T5	4828
auto[TlIntgErrNone]	full_word	auto[0]	75006051	1			T3	88099		T4	169740		T5	47192
auto[TlIntgErrNone]	full_word	auto[1]	80573354	1			T3	106628		T4	169756		T5	47371
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T65	3		T66	2		T67	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T65	2		T66	2		T67	5
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T133	1		T134	1		T128	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T66	1		T130	1		T133	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T65	4		T66	5		T67	3
auto[TlIntgErrData]	partial	auto[1]	39	1			T65	2		T67	4		T130	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T65	1		T129	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T66	1		T135	1		T136	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T65	2		T66	5		T67	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T65	6		T66	4		T67	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T133	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T126	2		T137	1		T134	1