Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1113434	1			T3	4251		T6	2554		T7	2
auto[1]	10704779	1			T3	2867		T4	156758		T5	18993
auto[2]	867489	1			T3	2676		T6	1227		T7	1
auto[3]	10399503	1			T3	1448		T4	156795		T5	19013

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14763034	1			T3	8747		T4	259755		T5	31613
auto[1]	2150854	1			T3	1050		T4	25545		T5	3084
auto[2]	2160871	1			T3	1302		T4	25690		T5	3028
auto[3]	4010446	1			T3	143		T4	2563		T5	281

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9310358

1

T3

11241

T5

38005

T6

4223

auto[1]

13774847

1

T3

1

T4

313553

T5

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	375940	1			T3	3521		T6	2092		T7	2
auto[0]	auto[0]	auto[1]	39239	1			T3	356		T6	214		T20	198
auto[0]	auto[0]	auto[2]	38978	1			T3	344		T6	226		T20	211
auto[0]	auto[0]	auto[3]	83031	1			T3	29		T6	22		T20	19
auto[0]	auto[1]	auto[0]	3314865	1			T3	2216		T5	15796		T6	187
auto[0]	auto[1]	auto[1]	347162	1			T3	379		T5	1477		T6	110
auto[0]	auto[1]	auto[2]	347584	1			T3	239		T5	1586		T6	19
auto[0]	auto[1]	auto[3]	272504	1			T3	33		T5	134		T6	14
auto[0]	auto[2]	auto[0]	282216	1			T3	2104		T6	1036		T20	725
auto[0]	auto[2]	auto[1]	34799	1			T3	213		T6	112		T7	1
auto[0]	auto[2]	auto[2]	30523	1			T3	323		T6	74		T20	123
auto[0]	auto[2]	auto[3]	57876	1			T3	36		T6	5		T20	17
auto[0]	auto[3]	auto[0]	3168011	1			T3	905		T5	15816		T6	45
auto[0]	auto[3]	auto[1]	331246	1			T3	102		T5	1607		T6	7
auto[0]	auto[3]	auto[2]	347659	1			T3	396		T5	1442		T6	54
auto[0]	auto[3]	auto[3]	238725	1			T3	45		T5	147		T6	6
auto[1]	auto[0]	auto[0]	18954	1			T3	1		T107	862		T141	1
auto[1]	auto[0]	auto[1]	85876	1			T107	3931		T111	783		T113	4242
auto[1]	auto[0]	auto[2]	85158	1			T107	4001		T111	718		T113	4220
auto[1]	auto[0]	auto[3]	386258	1			T107	18090		T91	1		T111	3269
auto[1]	auto[1]	auto[0]	3793654	1			T4	129901		T11	1		T40	3
auto[1]	auto[1]	auto[1]	648901	1			T4	12713		T44	1		T107	4074
auto[1]	auto[1]	auto[2]	611283	1			T4	12870		T107	700		T108	8924
auto[1]	auto[1]	auto[3]	1368826	1			T4	1274		T107	17997		T108	825
auto[1]	auto[2]	auto[0]	15351	1			T107	821		T141	1		T113	867
auto[1]	auto[2]	auto[1]	69169	1			T107	3728		T113	3921		T142	1131
auto[1]	auto[2]	auto[2]	68790	1			T107	2762		T111	632		T113	3572
auto[1]	auto[2]	auto[3]	308765	1			T107	12148		T111	2980		T113	16226
auto[1]	auto[3]	auto[0]	3794043	1			T4	129854		T5	1		T11	1
auto[1]	auto[3]	auto[1]	594462	1			T4	12832		T107	411		T108	8651
auto[1]	auto[3]	auto[2]	630896	1			T4	12820		T40	1		T107	2745
auto[1]	auto[3]	auto[3]	1294461	1			T4	1289		T107	12520		T108	863