SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.gen_instr_ctrl.u_prim_lc_sync_hw_debug_en | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
89.00 | 100.00 | 100.00 | 100.00 | 95.00 | 50.00 | u_tlul_lc_gate |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
91.90 | 100.00 | 88.89 | 100.00 | 100.00 | 70.59 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 2691 | 2691 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 5382 |
gen_no_flops.OutputDelay_A | 1212974813 | 1212872019 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2691 | 2691 | 0 | 0 |
T1 | 3 | 3 | 0 | 0 |
T2 | 3 | 3 | 0 | 0 |
T3 | 3 | 3 | 0 | 0 |
T4 | 3 | 3 | 0 | 0 |
T5 | 3 | 3 | 0 | 0 |
T6 | 3 | 3 | 0 | 0 |
T9 | 3 | 3 | 0 | 0 |
T10 | 3 | 3 | 0 | 0 |
T11 | 3 | 3 | 0 | 0 |
T12 | 3 | 3 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 4107 | 3957 | 0 | 0 |
T2 | 100764 | 100512 | 0 | 0 |
T3 | 932502 | 932382 | 0 | 0 |
T4 | 1710510 | 1710360 | 0 | 0 |
T5 | 1525689 | 1525524 | 0 | 0 |
T6 | 323022 | 323001 | 0 | 0 |
T9 | 135837 | 135606 | 0 | 0 |
T10 | 592434 | 592236 | 0 | 0 |
T11 | 2296548 | 2296323 | 0 | 0 |
T12 | 393435 | 393432 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 5382 |
T1 | 2738 | 2632 | 0 | 6 |
T2 | 67176 | 67002 | 0 | 6 |
T3 | 621668 | 621564 | 0 | 6 |
T4 | 1140340 | 1140234 | 0 | 6 |
T5 | 1017126 | 1017010 | 0 | 6 |
T6 | 215348 | 215334 | 0 | 6 |
T9 | 90558 | 90398 | 0 | 6 |
T10 | 394956 | 394818 | 0 | 6 |
T11 | 1531032 | 1530876 | 0 | 6 |
T12 | 262290 | 262288 | 0 | 6 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1212974813 | 1212872019 | 0 | 0 |
T1 | 1369 | 1319 | 0 | 0 |
T2 | 33588 | 33504 | 0 | 0 |
T3 | 310834 | 310794 | 0 | 0 |
T4 | 570170 | 570120 | 0 | 0 |
T5 | 508563 | 508508 | 0 | 0 |
T6 | 107674 | 107667 | 0 | 0 |
T9 | 45279 | 45202 | 0 | 0 |
T10 | 197478 | 197412 | 0 | 0 |
T11 | 765516 | 765441 | 0 | 0 |
T12 | 131145 | 131144 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 897 | 897 | 0 | 0 |
OutputsKnown_A | 1212974813 | 1212872019 | 0 | 0 |
gen_flops.OutputDelay_A | 1212974813 | 1212858351 | 0 | 2691 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 897 | 897 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1212974813 | 1212872019 | 0 | 0 |
T1 | 1369 | 1319 | 0 | 0 |
T2 | 33588 | 33504 | 0 | 0 |
T3 | 310834 | 310794 | 0 | 0 |
T4 | 570170 | 570120 | 0 | 0 |
T5 | 508563 | 508508 | 0 | 0 |
T6 | 107674 | 107667 | 0 | 0 |
T9 | 45279 | 45202 | 0 | 0 |
T10 | 197478 | 197412 | 0 | 0 |
T11 | 765516 | 765441 | 0 | 0 |
T12 | 131145 | 131144 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1212974813 | 1212858351 | 0 | 2691 |
T1 | 1369 | 1316 | 0 | 3 |
T2 | 33588 | 33501 | 0 | 3 |
T3 | 310834 | 310782 | 0 | 3 |
T4 | 570170 | 570117 | 0 | 3 |
T5 | 508563 | 508505 | 0 | 3 |
T6 | 107674 | 107667 | 0 | 3 |
T9 | 45279 | 45199 | 0 | 3 |
T10 | 197478 | 197409 | 0 | 3 |
T11 | 765516 | 765438 | 0 | 3 |
T12 | 131145 | 131144 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 897 | 897 | 0 | 0 |
OutputsKnown_A | 1212974813 | 1212872019 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1212974813 | 1212872019 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 897 | 897 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1212974813 | 1212872019 | 0 | 0 |
T1 | 1369 | 1319 | 0 | 0 |
T2 | 33588 | 33504 | 0 | 0 |
T3 | 310834 | 310794 | 0 | 0 |
T4 | 570170 | 570120 | 0 | 0 |
T5 | 508563 | 508508 | 0 | 0 |
T6 | 107674 | 107667 | 0 | 0 |
T9 | 45279 | 45202 | 0 | 0 |
T10 | 197478 | 197412 | 0 | 0 |
T11 | 765516 | 765441 | 0 | 0 |
T12 | 131145 | 131144 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1212974813 | 1212872019 | 0 | 0 |
T1 | 1369 | 1319 | 0 | 0 |
T2 | 33588 | 33504 | 0 | 0 |
T3 | 310834 | 310794 | 0 | 0 |
T4 | 570170 | 570120 | 0 | 0 |
T5 | 508563 | 508508 | 0 | 0 |
T6 | 107674 | 107667 | 0 | 0 |
T9 | 45279 | 45202 | 0 | 0 |
T10 | 197478 | 197412 | 0 | 0 |
T11 | 765516 | 765441 | 0 | 0 |
T12 | 131145 | 131144 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 897 | 897 | 0 | 0 |
OutputsKnown_A | 1212974813 | 1212872019 | 0 | 0 |
gen_flops.OutputDelay_A | 1212974813 | 1212858351 | 0 | 2691 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 897 | 897 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1212974813 | 1212872019 | 0 | 0 |
T1 | 1369 | 1319 | 0 | 0 |
T2 | 33588 | 33504 | 0 | 0 |
T3 | 310834 | 310794 | 0 | 0 |
T4 | 570170 | 570120 | 0 | 0 |
T5 | 508563 | 508508 | 0 | 0 |
T6 | 107674 | 107667 | 0 | 0 |
T9 | 45279 | 45202 | 0 | 0 |
T10 | 197478 | 197412 | 0 | 0 |
T11 | 765516 | 765441 | 0 | 0 |
T12 | 131145 | 131144 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1212974813 | 1212858351 | 0 | 2691 |
T1 | 1369 | 1316 | 0 | 3 |
T2 | 33588 | 33501 | 0 | 3 |
T3 | 310834 | 310782 | 0 | 3 |
T4 | 570170 | 570117 | 0 | 3 |
T5 | 508563 | 508505 | 0 | 3 |
T6 | 107674 | 107667 | 0 | 3 |
T9 | 45279 | 45199 | 0 | 3 |
T10 | 197478 | 197409 | 0 | 3 |
T11 | 765516 | 765438 | 0 | 3 |
T12 | 131145 | 131144 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |